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| REJ09B0294-0100 32 H8SX/1663Group Hardware Manual Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series H8SX/1663 H8SX/1664 R5F61663 R5F61664 Rev.1.00 Revision Date: Jun. 07, 2006 Rev.1.00 Jun. 07, 2006 Page ii of lii Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. Rev.1.00 Jun. 07, 2006 Page iii of lii General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system's operation is not guaranteed if they are accessed. Rev.1.00 Jun. 07, 2006 Page iv of lii Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules * CPU and System-Control Modules * On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. List of Registers 8. Electrical Characteristics 9. Appendix 10. Main Revisions and Additions in this Edition (only for revised versions) The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 11. Index Rev.1.00 Jun. 07, 2006 Page v of lii Preface The H8SX/1663 Group is a single-chip microcomputer made up of the high-speed internal 32-bit H8SX CPU as its core, and the peripheral functions required to configure a system. The H8SX CPU is upward compatible with the H8/300, H8/300H, and H8S CPUs. Target Users: This manual was written for users who will be using the H8SX/1663 Group in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of the H8SX/1663 Group to the target users. Refer to the H8SX Family Software Manual for a detailed description of the instruction set. Notes on reading this manual: * In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics. * In order to understand the details of the CPU's functions Read the H8SX Family Software Manual. * In order to understand the details of a register when its name is known Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bits, and initial values of the registers are summarized in section 24, List of Registers. Examples: Register name: The following notation is used for cases when the same or a similar function, e.g. 16-bit timer pulse unit or serial communication interface, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel number) The MSB is on the left and the LSB is on the right. Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx. An overbar is added to a low-active signal: xxxx Bit order: Number notation: Signal notation: Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/ Rev.1.00 Jun. 07, 2006 Page vi of lii H8SX/1663 Group manuals: Document Title H8SX/1663 Group Hardware Manual H8SX Family Software Manual Document No. This manual REJ09B0102 Rev.1.00 Jun. 07, 2006 Page vii of lii Rev.1.00 Jun. 07, 2006 Page viii of lii Contents Section 1 Overview................................................................................................1 1.1 1.2 1.3 Features.................................................................................................................................. 1 Block Diagram ....................................................................................................................... 2 Pin Assignments..................................................................................................................... 3 1.3.1 Pin Assignments ....................................................................................................... 3 1.3.2 Pin Configuration in Each Operating Mode.............................................................. 4 1.3.3 Pin Functions ............................................................................................................ 9 Section 2 CPU......................................................................................................21 2.1 2.2 Features................................................................................................................................ 21 CPU Operating Modes ......................................................................................................... 23 2.2.1 Normal Mode.......................................................................................................... 23 2.2.2 Middle Mode........................................................................................................... 25 2.2.3 Advanced Mode...................................................................................................... 26 2.2.4 Maximum Mode ..................................................................................................... 27 Instruction Fetch .................................................................................................................. 29 Address Space...................................................................................................................... 29 Registers............................................................................................................................... 30 2.5.1 General Registers .................................................................................................... 31 2.5.2 Program Counter (PC) ............................................................................................ 32 2.5.3 Condition-Code Register (CCR) ............................................................................. 33 2.5.4 Extended Control Register (EXR) .......................................................................... 34 2.5.5 Vector Base Register (VBR)................................................................................... 35 2.5.6 Short Address Base Register (SBR)........................................................................ 35 2.5.7 Multiply-Accumulate Register (MAC) ................................................................... 35 2.5.8 Initial Values of CPU Registers .............................................................................. 35 Data Formats........................................................................................................................ 36 2.6.1 General Register Data Formats ............................................................................... 36 2.6.2 Memory Data Formats ............................................................................................ 37 Instruction Set ...................................................................................................................... 38 2.7.1 Instructions and Addressing Modes........................................................................ 40 2.7.2 Table of Instructions Classified by Function .......................................................... 44 2.7.3 Basic Instruction Formats ....................................................................................... 54 Addressing Modes and Effective Address Calculation ........................................................ 55 2.8.1 Register Direct--Rn................................................................................................ 55 2.8.2 Register Indirect--@ERn ....................................................................................... 56 2.3 2.4 2.5 2.6 2.7 2.8 Rev.1.00 Jun. 07, 2006 Page ix of lii 2.9 Register Indirect with Displacement --@(d:2, ERn), @(d:16, ERn), or @(d:32, ERn) .................................................................................................... 56 2.8.4 Index Register Indirect with Displacement--@(d:16,RnL.B), @(d:32,RnL.B), @(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L)..................... 56 2.8.5 Register Indirect with Post-Increment, Pre-Decrement, Pre-Increment, or Post-Decrement--@ERn+, @-ERn, @+ERn, or @ERn- ................................ 57 2.8.6 Absolute Address--@aa:8, @aa:16, @aa:24, or @aa:32....................................... 58 2.8.7 Immediate--#xx ..................................................................................................... 59 2.8.8 Program-Counter Relative--@(d:8, PC) or @(d:16, PC)....................................... 59 2.8.9 Program-Counter Relative with Index Register--@(RnL.B, PC), @(Rn.W, PC), or @(ERn.L, PC) .................................................................................................... 59 2.8.10 Memory Indirect--@@aa:8 ................................................................................... 60 2.8.11 Extended Memory Indirect--@@vec:7 ................................................................. 61 2.8.12 Effective Address Calculation ................................................................................ 61 2.8.13 MOVA Instruction.................................................................................................. 63 Processing States.................................................................................................................. 64 2.8.3 Section 3 MCU Operating Modes .......................................................................65 3.1 3.2 Operating Mode Selection ................................................................................................... 65 Register Descriptions ........................................................................................................... 66 3.2.1 Mode Control Register (MDCR) ............................................................................ 66 3.2.2 System Control Register (SYSCR) ......................................................................... 68 Operating Mode Descriptions .............................................................................................. 70 3.3.1 Mode 2.................................................................................................................... 70 3.3.2 Mode 4.................................................................................................................... 70 3.3.3 Mode 5.................................................................................................................... 70 3.3.4 Mode 6.................................................................................................................... 71 3.3.5 Mode 7.................................................................................................................... 71 3.3.6 Pin Functions .......................................................................................................... 72 Address Map ........................................................................................................................ 73 3.4.1 Address Map........................................................................................................... 73 3.3 3.4 Section 4 Exception Handling .............................................................................77 4.1 4.2 4.3 Exception Handling Types and Priority............................................................................... 77 Exception Sources and Exception Handling Vector Table .................................................. 78 Reset .................................................................................................................................... 80 4.3.1 Reset Exception Handling ...................................................................................... 80 4.3.2 Interrupts after Reset............................................................................................... 81 4.3.3 On-Chip Peripheral Functions after Reset Release................................................. 81 Traces................................................................................................................................... 83 4.4 Rev.1.00 Jun. 07, 2006 Page x of lii 4.5 4.6 4.7 4.8 4.9 Address Error ....................................................................................................................... 84 4.5.1 Address Error Source.............................................................................................. 84 4.5.2 Address Error Exception Handling ......................................................................... 85 Interrupts.............................................................................................................................. 86 4.6.1 Interrupt Sources..................................................................................................... 86 4.6.2 Interrupt Exception Handling.................................................................................. 87 Instruction Exception Handling ........................................................................................... 87 4.7.1 Trap Instruction....................................................................................................... 87 4.7.2 Sleep Instruction Exception Handling .................................................................... 88 4.7.3 Exception Handling by Illegal Instruction .............................................................. 89 Stack Status after Exception Handling................................................................................. 90 Usage Note........................................................................................................................... 91 Section 5 Interrupt Controller ..............................................................................93 5.1 5.2 5.3 Features................................................................................................................................ 93 Input/Output Pins ................................................................................................................. 95 Register Descriptions ........................................................................................................... 95 5.3.1 Interrupt Control Register (INTCR) ....................................................................... 96 5.3.2 CPU Priority Control Register (CPUPCR) ............................................................. 97 5.3.3 Interrupt Priority Registers A to I, K, L, Q, and R (IPRA to IPRI, IPRK, IPRL, IPRQ, and IPRR)...................................................... 98 5.3.4 IRQ Enable Register (IER) ................................................................................... 100 5.3.5 IRQ Sense Control Registers H and L (ISCRH, ISCRL)...................................... 102 5.3.6 IRQ Status Register (ISR)..................................................................................... 106 5.3.7 Software Standby Release IRQ Enable Register (SSIER) .................................... 107 Interrupt Sources................................................................................................................ 109 5.4.1 External Interrupts ................................................................................................ 109 5.4.2 Internal Interrupts ................................................................................................. 110 Interrupt Exception Handling Vector Table....................................................................... 111 Interrupt Control Modes and Interrupt Operation .............................................................. 116 5.6.1 Interrupt Control Mode 0 ...................................................................................... 116 5.6.2 Interrupt Control Mode 2 ...................................................................................... 118 5.6.3 Interrupt Exception Handling Sequence ............................................................... 120 5.6.4 Interrupt Response Times ..................................................................................... 121 5.6.5 DTC and DMAC Activation by Interrupt ............................................................. 122 CPU Priority Control Function Over DTC and DMAC..................................................... 125 Usage Notes ....................................................................................................................... 128 5.8.1 Conflict between Interrupt Generation and Disabling .......................................... 128 5.8.2 Instructions that Disable Interrupts ....................................................................... 129 5.8.3 Times when Interrupts are Disabled ..................................................................... 129 Rev.1.00 Jun. 07, 2006 Page xi of lii 5.4 5.5 5.6 5.7 5.8 5.8.4 5.8.5 5.8.6 Interrupts during Execution of EEPMOV Instruction........................................... 129 Interrupts during Execution of MOVMD and MOVSD Instructions.................... 129 Interrupts of Peripheral Modules .......................................................................... 130 Section 6 Bus Controller (BSC) ........................................................................ 131 6.1 6.2 Features.............................................................................................................................. 131 Register Descriptions ......................................................................................................... 134 6.2.1 Bus Width Control Register (ABWCR)................................................................ 135 6.2.2 Access State Control Register (ASTCR) .............................................................. 136 6.2.3 Wait Control Registers A and B (WTCRA, WTCRB) ......................................... 137 6.2.4 Read Strobe Timing Control Register (RDNCR) ................................................. 142 6.2.5 CS Assertion Period Control Registers (CSACR) ................................................ 143 6.2.6 Idle Control Register (IDLCR) ............................................................................. 146 6.2.7 Bus Control Register 1 (BCR1) ............................................................................ 148 6.2.8 Bus Control Register 2 (BCR2) ............................................................................ 150 6.2.9 Endian Control Register (ENDIANCR) ............................................................... 151 6.2.10 SRAM Mode Control Register (SRAMCR) ......................................................... 152 6.2.11 Burst ROM Interface Control Register (BROMCR) ............................................ 153 6.2.12 Address/Data Multiplexed I/O Control Register (MPXCR) ................................. 155 6.2.13 DRAM Control Register (DRAMCR) .................................................................. 156 6.2.14 DRAM Access Control Register (DRACCR)....................................................... 160 6.2.15 Synchronous DRAM Control Register (SDCR) ................................................... 162 6.2.16 Refresh Control Register (REFCR) ...................................................................... 163 6.2.17 Refresh Timer Counter (RTCNT)......................................................................... 167 6.2.18 Refresh Time Constant Register (RTCOR) .......................................................... 167 Bus Configuration.............................................................................................................. 168 Multi-Clock Function and Number of Access Cycles ....................................................... 169 External Bus....................................................................................................................... 173 6.5.1 Input/Output Pins.................................................................................................. 173 6.5.2 Area Division........................................................................................................ 177 6.5.3 Chip Select Signals ............................................................................................... 178 6.5.4 External Bus Interface .......................................................................................... 179 6.5.5 Area and External Bus Interface ........................................................................... 184 6.5.6 Endian and Data Alignment.................................................................................. 189 Basic Bus Interface ............................................................................................................ 192 6.6.1 Data Bus ............................................................................................................... 192 6.6.2 I/O Pins Used for Basic Bus Interface .................................................................. 192 6.6.3 Basic Timing......................................................................................................... 193 6.6.4 Wait Control ......................................................................................................... 199 6.6.5 Read Strobe (RD) Timing..................................................................................... 201 6.3 6.4 6.5 6.6 Rev.1.00 Jun. 07, 2006 Page xii of lii 6.6.6 Extension of Chip Select (CS) Assertion Period................................................... 202 6.6.7 DACK Signal Output Timing ............................................................................... 204 6.7 Byte Control SRAM Interface ........................................................................................... 205 6.7.1 Byte Control SRAM Space Setting....................................................................... 205 6.7.2 Data Bus................................................................................................................ 205 6.7.3 I/O Pins Used for Byte Control SRAM Interface ................................................. 206 6.7.4 Basic Timing......................................................................................................... 207 6.7.5 Wait Control ......................................................................................................... 209 6.7.6 Read Strobe (RD).................................................................................................. 211 6.7.7 Extension of Chip Select (CS) Assertion Period................................................... 211 6.7.8 DACK Signal Output Timing ............................................................................... 211 6.8 Burst ROM Interface.......................................................................................................... 213 6.8.1 Burst ROM Space Setting ..................................................................................... 213 6.8.2 Data Bus................................................................................................................ 213 6.8.3 I/O Pins Used for Burst ROM Interface................................................................ 214 6.8.4 Basic Timing......................................................................................................... 215 6.8.5 Wait Control ......................................................................................................... 217 6.8.6 Read Strobe (RD) Timing..................................................................................... 217 6.8.7 Extension of Chip Select (CS) Assertion Period................................................... 217 6.9 Address/Data Multiplexed I/O Interface............................................................................ 218 6.9.1 Address/Data Multiplexed I/O Space Setting ....................................................... 218 6.9.2 Address/Data Multiplex ........................................................................................ 218 6.9.3 Data Bus................................................................................................................ 218 6.9.4 I/O Pins Used for Address/Data Multiplexed I/O Interface .................................. 219 6.9.5 Basic Timing......................................................................................................... 220 6.9.6 Address Cycle Control.......................................................................................... 222 6.9.7 Wait Control ......................................................................................................... 223 6.9.8 Read Strobe (RD) Timing.................................................................................... 223 6.9.9 Extension of Chip Select (CS) Assertion Period................................................... 225 6.9.10 DACK Signal Output Timing ............................................................................... 227 6.10 DRAM Interface ................................................................................................................ 228 6.10.1 Setting DRAM Space............................................................................................ 228 6.10.2 Address Multiplexing............................................................................................ 228 6.10.3 Data Bus................................................................................................................ 229 6.10.4 I/O Pins Used for DRAM Interface ...................................................................... 229 6.10.5 Basic Timing......................................................................................................... 230 6.10.6 Controlling Column Address Output Cycle.......................................................... 231 6.10.7 Controlling Row Address Output Cycle ............................................................... 232 6.10.8 Controlling Precharge Cycle................................................................................. 234 6.10.9 Wait Control ......................................................................................................... 235 Rev.1.00 Jun. 07, 2006 Page xiii of lii 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.18 6.10.10 Controlling Byte and Word Accesses ................................................................... 238 6.10.11 Burst Access Operation ........................................................................................ 240 6.10.12 Refresh Control..................................................................................................... 246 6.10.13 DRAM Interface and Single Address Transfer by DMAC ................................... 251 Synchronous DRAM Interface........................................................................................... 254 6.11.1 Setting SDRAM space .......................................................................................... 254 6.11.2 Address Multiplexing ........................................................................................... 255 6.11.3 Data Bus ............................................................................................................... 255 6.11.4 I/O Pins Used for DRAM Interface ...................................................................... 256 6.11.5 Basic Timing......................................................................................................... 257 6.11.6 CAS Latency Control............................................................................................ 259 6.11.7 Controlling Row Address Output Cycle ............................................................... 261 6.11.8 Controlling Precharge Cycle................................................................................. 263 6.11.9 Controlling Clock Suspend Insertion.................................................................... 265 6.11.10 Controlling Write-Precharge Delay ...................................................................... 266 6.11.11 Controlling Byte and Word Accesses ................................................................... 267 6.11.12 Fast-Page Access Operation ................................................................................. 269 6.11.13 Refresh Control..................................................................................................... 275 6.11.14 Setting SDRAM Mode Register ........................................................................... 281 6.11.15 SDRAM Interface and Single Address Transfer by DMAC................................. 282 Idle Cycle........................................................................................................................... 291 6.12.1 Operation .............................................................................................................. 291 6.12.2 Pin States in Idle Cycle......................................................................................... 303 Bus Release........................................................................................................................ 304 6.13.1 Operation .............................................................................................................. 304 6.13.2 Pin States in External Bus Released State ............................................................ 305 6.13.3 Transition Timing ................................................................................................. 306 Internal Bus........................................................................................................................ 308 6.14.1 Access to Internal Address Space ......................................................................... 308 Write Data Buffer Function ............................................................................................... 309 6.15.1 Write Data Buffer Function for External Data Bus .............................................. 309 6.15.2 Write Data Buffer Function for Peripheral Modules ............................................ 310 Bus Arbitration .................................................................................................................. 311 6.16.1 Operation .............................................................................................................. 311 6.16.2 Bus Transfer Timing............................................................................................. 312 Bus Controller Operation in Reset ..................................................................................... 314 Usage Notes ....................................................................................................................... 314 Section 7 DMA Controller (DMAC).................................................................317 7.1 Features.............................................................................................................................. 317 Rev.1.00 Jun. 07, 2006 Page xiv of lii 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 Input/Output Pins ............................................................................................................... 320 Register Descriptions ......................................................................................................... 321 7.3.1 DMA Source Address Register (DSAR)............................................................... 322 7.3.2 DMA Destination Address Register (DDAR)....................................................... 323 7.3.3 DMA Offset Register (DOFR).............................................................................. 324 7.3.4 DMA Transfer Count Register (DTCR) ............................................................... 325 7.3.5 DMA Block Size Register (DBSR) ...................................................................... 326 7.3.6 DMA Mode Control Register (DMDR)................................................................ 327 7.3.7 DMA Address Control Register (DACR) ............................................................. 336 7.3.8 DMA Module Request Select Register (DMRSR) ............................................... 342 Transfer Modes .................................................................................................................. 342 Operations.......................................................................................................................... 343 7.5.1 Address Modes ..................................................................................................... 343 7.5.2 Transfer Modes ..................................................................................................... 347 7.5.3 Activation Sources................................................................................................ 352 7.5.4 Bus Access Modes ................................................................................................ 354 7.5.5 Extended Repeat Area Function ........................................................................... 356 7.5.6 Address Update Function using Offset ................................................................. 359 7.5.7 Register during DMA Transfer ............................................................................. 363 7.5.8 Priority of Channels .............................................................................................. 368 7.5.9 DMA Basic Bus Cycle.......................................................................................... 370 7.5.10 Bus Cycles in Dual Address Mode ....................................................................... 371 7.5.11 Bus Cycles in Single Address Mode..................................................................... 380 DMA Transfer End ............................................................................................................ 385 Relationship among DMAC and Other Bus Masters ......................................................... 388 7.7.1 CPU Priority Control Function Over DMAC ....................................................... 388 7.7.2 Bus Arbitration among DMAC and Other Bus Masters ....................................... 389 Interrupt Sources................................................................................................................ 390 Notes on Usage .................................................................................................................. 393 Section 8 Data Transfer Controller (DTC) ........................................................395 8.1 8.2 Features.............................................................................................................................. 395 Register Descriptions ......................................................................................................... 397 8.2.1 DTC Mode Register A (MRA) ............................................................................. 398 8.2.2 DTC Mode Register B (MRB).............................................................................. 399 8.2.3 DTC Source Address Register (SAR)................................................................... 400 8.2.4 DTC Destination Address Register (DAR)........................................................... 401 8.2.5 DTC Transfer Count Register A (CRA) ............................................................... 401 8.2.6 DTC Transfer Count Register B (CRB)................................................................ 402 Rev.1.00 Jun. 07, 2006 Page xv of lii 8.2.7 8.3 8.4 8.5 8.6 8.7 8.8 8.9 DTC enable registers A to E, G, and H (DTCERA to DTCERE, DTCERG, and DTCERH) ...................................................................................................... 402 8.2.8 DTC Control Register (DTCCR) .......................................................................... 403 8.2.9 DTC Vector Base Register (DTCVBR)................................................................ 405 Activation Sources............................................................................................................. 405 Location of Transfer Information and DTC Vector Table ................................................. 405 Operation ........................................................................................................................... 409 8.5.1 Bus Cycle Division ............................................................................................... 411 8.5.2 Transfer Information Read Skip Function ............................................................ 413 8.5.3 Transfer Information Writeback Skip Function.................................................... 414 8.5.4 Normal Transfer Mode ......................................................................................... 414 8.5.5 Repeat Transfer Mode .......................................................................................... 415 8.5.6 Block Transfer Mode ............................................................................................ 417 8.5.7 Chain Transfer ...................................................................................................... 418 8.5.8 Operation Timing.................................................................................................. 419 8.5.9 Number of DTC Execution Cycles ....................................................................... 421 8.5.10 DTC Bus Release Timing ..................................................................................... 422 8.5.11 DTC Priority Level Control to the CPU ............................................................... 422 DTC Activation by Interrupt.............................................................................................. 423 Examples of Use of the DTC ............................................................................................. 424 8.7.1 Normal Transfer Mode ......................................................................................... 424 8.7.2 Chain Transfer ...................................................................................................... 424 8.7.3 Chain Transfer when Counter = 0......................................................................... 425 Interrupt Sources................................................................................................................ 427 Usage Notes ....................................................................................................................... 427 8.9.1 Module Stop State Setting .................................................................................... 427 8.9.2 On-Chip RAM ...................................................................................................... 427 8.9.3 DMAC Transfer End Interrupt.............................................................................. 427 8.9.4 DTCE Bit Setting.................................................................................................. 427 8.9.5 Chain Transfer ...................................................................................................... 428 8.9.6 Transfer Information Start Address, Source Address, and Destination Address ....................................................................................... 428 8.9.7 Transfer Information Modification ....................................................................... 428 8.9.8 Endian Format ...................................................................................................... 428 Section 9 I/O Ports.............................................................................................429 9.1 Register Descriptions ......................................................................................................... 436 9.1.1 Data Direction Register (PnDDR) (n = 1, 2, 3, 6, A to F, H, I, and M) ................ 437 9.1.2 Data Register (PnDR) (n = 1, 2, 3, 6, A to F, H, I, and M)................................... 438 9.1.3 Port Register (PORTn) (n = 1, 2, 3, 5, 6, A to F, H, I, and M) ............................. 438 Rev.1.00 Jun. 07, 2006 Page xvi of lii 9.2 9.3 9.4 9.1.4 Input Buffer Control Register (PnICR) (n = 1, 2, 3, 5, 6, A to F, H, I, and M)..... 439 9.1.5 Pull-Up MOS Control Register (PnPCR) (n = D to F, H, and I)........................... 440 9.1.6 Open-Drain Control Register (PnODR) (n = 2 and F) .......................................... 441 Output Buffer Control........................................................................................................ 441 9.2.1 Port 1..................................................................................................................... 442 9.2.2 Port 2..................................................................................................................... 446 9.2.3 Port 3..................................................................................................................... 450 9.2.4 Port 5..................................................................................................................... 454 9.2.5 Port 6..................................................................................................................... 454 9.2.6 Port A.................................................................................................................... 457 9.2.7 Port B .................................................................................................................... 462 9.2.8 Port C .................................................................................................................... 466 9.2.9 Port D.................................................................................................................... 467 9.2.10 Port E .................................................................................................................... 467 9.2.11 Port F .................................................................................................................... 468 9.2.12 Port H.................................................................................................................... 472 9.2.13 Port I ..................................................................................................................... 473 9.2.14 Port M ................................................................................................................... 474 Port Function Controller .................................................................................................... 483 9.3.1 Port Function Control Register 0 (PFCR0) ........................................................... 483 9.3.2 Port Function Control Register 1 (PFCR1) ........................................................... 484 9.3.3 Port Function Control Register 2 (PFCR2) ........................................................... 485 9.3.4 Port Function Control Register 4 (PFCR4) ........................................................... 487 9.3.5 Port Function Control Register 6 (PFCR6) ........................................................... 489 9.3.6 Port Function Control Register 7 (PFCR7) ........................................................... 490 9.3.7 Port Function Control Register 9 (PFCR9) ........................................................... 491 9.3.8 Port Function Control Register B (PFCRB).......................................................... 493 9.3.9 Port Function Control Register C (PFCRC).......................................................... 494 Usage Notes ....................................................................................................................... 496 9.4.1 Notes on Input Buffer Control Register (ICR) Setting ......................................... 496 9.4.2 Notes on Port Function Control Register (PFCR) Settings................................... 496 Section 10 16-Bit Timer Pulse Unit (TPU)........................................................497 10.1 Features.............................................................................................................................. 497 10.2 Input/Output Pins ............................................................................................................... 501 10.3 Register Descriptions ......................................................................................................... 502 10.3.1 Timer Control Register (TCR).............................................................................. 504 10.3.2 Timer Mode Register (TMDR) ............................................................................. 509 10.3.3 Timer I/O Control Register (TIOR) ...................................................................... 510 10.3.4 Timer Interrupt Enable Register (TIER) ............................................................... 528 Rev.1.00 Jun. 07, 2006 Page xvii of lii 10.4 10.5 10.6 10.7 10.8 10.9 10.10 10.3.5 Timer Status Register (TSR)................................................................................. 530 10.3.6 Timer Counter (TCNT)......................................................................................... 534 10.3.7 Timer General Register (TGR) ............................................................................. 534 10.3.8 Timer Start Register (TSTR) ................................................................................ 535 10.3.9 Timer Synchronous Register (TSYR)................................................................... 536 Operation ........................................................................................................................... 537 10.4.1 Basic Functions..................................................................................................... 537 10.4.2 Synchronous Operation......................................................................................... 543 10.4.3 Buffer Operation................................................................................................... 545 10.4.4 Cascaded Operation .............................................................................................. 549 10.4.5 PWM Modes......................................................................................................... 551 10.4.6 Phase Counting Mode........................................................................................... 556 Interrupt Sources................................................................................................................ 563 DTC Activation.................................................................................................................. 565 DMAC Activation.............................................................................................................. 565 A/D Converter Activation.................................................................................................. 565 Operation Timing............................................................................................................... 566 10.9.1 Input/Output Timing ............................................................................................. 566 10.9.2 Interrupt Signal Timing ........................................................................................ 570 Usage Notes ....................................................................................................................... 574 10.10.1 Module Stop State Setting .................................................................................... 574 10.10.2 Input Clock Restrictions ....................................................................................... 574 10.10.3 Caution on Cycle Setting ...................................................................................... 575 10.10.4 Conflict between TCNT Write and Clear Operations........................................... 575 10.10.5 Conflict between TCNT Write and Increment Operations ................................... 576 10.10.6 Conflict between TGR Write and Compare Match............................................... 576 10.10.7 Conflict between Buffer Register Write and Compare Match.............................. 577 10.10.8 Conflict between TGR Read and Input Capture ................................................... 578 10.10.9 Conflict between TGR Write and Input Capture .................................................. 579 10.10.10 Conflict between Buffer Register Write and Input Capture................................ 580 10.10.11 Conflict between Overflow/Underflow and Counter Clearing ........................... 581 10.10.12 Conflict between TCNT Write and Overflow/Underflow .................................. 582 10.10.13 Multiplexing of I/O Pins ..................................................................................... 582 10.10.14 Interrupts and Module Stop Mode ...................................................................... 582 Section 11 Programmable Pulse Generator (PPG)............................................583 11.1 Features.............................................................................................................................. 583 11.2 Input/Output Pins............................................................................................................... 584 11.3 Register Descriptions ......................................................................................................... 585 11.3.1 Next Data Enable Registers H, L (NDERH, NDERL) ......................................... 585 Rev.1.00 Jun. 07, 2006 Page xviii of lii 11.3.2 Output Data Registers H, L (PODRH, PODRL)................................................... 587 11.3.3 Next Data Registers H, L (NDRH, NDRL) .......................................................... 588 11.3.4 PPG Output Control Register (PCR) .................................................................... 591 11.3.5 PPG Output Mode Register (PMR) ...................................................................... 592 11.4 Operation ........................................................................................................................... 594 11.4.1 Output Timing....................................................................................................... 594 11.4.2 Sample Setup Procedure for Normal Pulse Output............................................... 595 11.4.3 Example of Normal Pulse Output (Example of 5-Phase Pulse Output)................ 596 11.4.4 Non-Overlapping Pulse Output............................................................................. 597 11.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output ............................... 599 11.4.6 Example of Non-Overlapping Pulse Output (Example of 4-Phase Complementary Non-Overlapping Pulse Output) ................................... 600 11.4.7 Inverted Pulse Output ........................................................................................... 602 11.4.8 Pulse Output Triggered by Input Capture ............................................................. 603 11.5 Usage Notes ....................................................................................................................... 604 11.5.1 Module Stop State Setting .................................................................................... 604 11.5.2 Operation of Pulse Output Pins............................................................................. 604 Section 12 8-Bit Timers (TMR).........................................................................605 12.1 Features.............................................................................................................................. 605 12.2 Input/Output Pins ............................................................................................................... 610 12.3 Register Descriptions ......................................................................................................... 611 12.3.1 Timer Counter (TCNT)......................................................................................... 613 12.3.2 Time Constant Register A (TCORA).................................................................... 613 12.3.3 Time Constant Register B (TCORB) .................................................................... 614 12.3.4 Timer Control Register (TCR).............................................................................. 614 12.3.5 Timer Counter Control Register (TCCR) ............................................................. 616 12.3.6 Timer Control/Status Register (TCSR)................................................................. 619 12.4 Operation ........................................................................................................................... 623 12.4.1 Pulse Output.......................................................................................................... 623 12.4.2 Reset Input ............................................................................................................ 624 12.5 Operation Timing............................................................................................................... 625 12.5.1 TCNT Count Timing............................................................................................. 625 12.5.2 Timing of CMFA and CMFB Setting at Compare Match..................................... 626 12.5.3 Timing of Timer Output at Compare Match ......................................................... 626 12.5.4 Timing of Counter Clear by Compare Match ....................................................... 627 12.5.5 Timing of TCNT External Reset........................................................................... 627 12.5.6 Timing of Overflow Flag (OVF) Setting .............................................................. 628 12.6 Operation with Cascaded Connection ................................................................................ 628 12.6.1 16-Bit Counter Mode ............................................................................................ 628 Rev.1.00 Jun. 07, 2006 Page xix of lii 12.6.2 Compare Match Count Mode................................................................................ 629 12.7 Interrupt Sources................................................................................................................ 629 12.7.1 Interrupt Sources and DTC Activation ................................................................. 629 12.7.2 A/D Converter Activation..................................................................................... 630 12.8 Usage Notes ....................................................................................................................... 631 12.8.1 Notes on Setting Cycle ......................................................................................... 631 12.8.2 Conflict between TCNT Write and Counter Clear ............................................... 631 12.8.3 Conflict between TCNT Write and Increment...................................................... 632 12.8.4 Conflict between TCOR Write and Compare Match ............................................ 632 12.8.5 Conflict between Compare Matches A and B....................................................... 633 12.8.6 Switching of Internal Clocks and TCNT Operation ............................................. 633 12.8.7 Mode Setting with Cascaded Connection ............................................................. 635 12.8.8 Module Stop State Setting .................................................................................... 635 12.8.9 Interrupts in Module Stop State ............................................................................ 635 Section 13 32K Timer (TM32K).......................................................................637 13.1 Features.............................................................................................................................. 637 13.2 Register Descriptions ......................................................................................................... 638 13.2.1 Timer Counter (TCNT32K).................................................................................. 638 13.2.2 Time Control Register (TCR32K) ........................................................................ 638 13.3 Operation ........................................................................................................................... 639 13.4 Interrupt Source ................................................................................................................. 640 13.5 Usage Notes ....................................................................................................................... 640 13.5.1 Changing Values of Bits CKS1 and CKS0........................................................... 640 13.5.2 Usage Notes on 32K Timer .................................................................................. 640 13.5.3 Note on Reading Timer Counter........................................................................... 640 13.5.4 Note on Register Initialization .............................................................................. 640 Section 14 Watchdog Timer (WDT) .................................................................641 14.1 Features.............................................................................................................................. 641 14.2 Input/Output Pin ................................................................................................................ 642 14.3 Register Descriptions ......................................................................................................... 643 14.3.1 Timer Counter (TCNT)......................................................................................... 643 14.3.2 Timer Control/Status Register (TCSR)................................................................. 643 14.3.3 Reset Control/Status Register (RSTCSR)............................................................. 645 14.4 Operation ........................................................................................................................... 646 14.4.1 Watchdog Timer Mode......................................................................................... 646 14.4.2 Interval Timer Mode............................................................................................. 648 14.5 Interrupt Source ................................................................................................................. 648 14.6 Usage Notes ....................................................................................................................... 649 Rev.1.00 Jun. 07, 2006 Page xx of lii 14.6.1 14.6.2 14.6.3 14.6.4 14.6.5 14.6.6 14.6.7 Notes on Register Access...................................................................................... 649 Conflict between Timer Counter (TCNT) Write and Increment........................... 650 Changing Values of Bits CKS2 to CKS0.............................................................. 650 Switching between Watchdog Timer Mode and Interval Timer Mode................. 650 Internal Reset in Watchdog Timer Mode.............................................................. 651 System Reset by WDTOVF Signal....................................................................... 651 Transition to Watchdog Timer Mode or Software Standby Mode........................ 651 Section 15 Serial Communication Interface (SCI, IrDA, CRC)........................653 15.1 Features.............................................................................................................................. 653 15.2 Input/Output Pins ............................................................................................................... 658 15.3 Register Descriptions ......................................................................................................... 659 15.3.1 Receive Shift Register (RSR) ............................................................................... 661 15.3.2 Receive Data Register (RDR) ............................................................................... 661 15.3.3 Transmit Data Register (TDR).............................................................................. 662 15.3.4 Transmit Shift Register (TSR) .............................................................................. 662 15.3.5 Serial Mode Register (SMR) ................................................................................ 662 15.3.6 Serial Control Register (SCR)............................................................................... 666 15.3.7 Serial Status Register (SSR) ................................................................................. 671 15.3.8 Smart Card Mode Register (SCMR) ..................................................................... 680 15.3.9 Bit Rate Register (BRR) ....................................................................................... 681 15.3.10 Serial Extended Mode Register (SEMR_2) .......................................................... 688 15.3.11 Serial Extended Mode Register 5 and 6 (SEMR_5 and SEMR_6) ....................... 690 15.3.12 IrDA Control Register (IrCR) ............................................................................... 697 15.4 Operation in Asynchronous Mode ..................................................................................... 698 15.4.1 Data Transfer Format............................................................................................ 699 15.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode . 700 15.4.3 Clock..................................................................................................................... 701 15.4.4 SCI Initialization (Asynchronous Mode) .............................................................. 702 15.4.5 Serial Data Transmission (Asynchronous Mode) ................................................. 703 15.4.6 Serial Data Reception (Asynchronous Mode)....................................................... 705 15.5 Multiprocessor Communication Function.......................................................................... 709 15.5.1 Multiprocessor Serial Data Transmission ............................................................. 711 15.5.2 Multiprocessor Serial Data Reception .................................................................. 712 15.6 Operation in Clocked Synchronous Mode (SCI_0, 1, 2, and 4 only)................................. 715 15.6.1 Clock..................................................................................................................... 715 15.6.2 SCI Initialization (Clocked Synchronous Mode) (SCI_0, 1, 2, and 4 only).......... 716 15.6.3 Serial Data Transmission (Clocked Synchronous Mode) (SCI_0, 1, 2, and 4 only)....................................................................................... 717 Rev.1.00 Jun. 07, 2006 Page xxi of lii 15.7 15.8 15.9 15.10 15.11 15.6.4 Serial Data Reception (Clocked Synchronous Mode) (SCI_0, 1, 2, and 4 only)....................................................................................... 719 15.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) (SCI_0, 1, 2, and 4 only)...................................... 720 Operation in Smart Card Interface Mode........................................................................... 722 15.7.1 Sample Connection ............................................................................................... 722 15.7.2 Data Format (Except in Block Transfer Mode) .................................................... 723 15.7.3 Block Transfer Mode ............................................................................................ 724 15.7.4 Receive Data Sampling Timing and Reception Margin ....................................... 725 15.7.5 Initialization.......................................................................................................... 726 15.7.6 Data Transmission (Except in Block Transfer Mode) .......................................... 727 15.7.7 Serial Data Reception (Except in Block Transfer Mode) ..................................... 730 15.7.8 Clock Output Control............................................................................................ 731 IrDA Operation .................................................................................................................. 733 Interrupt Sources................................................................................................................ 736 15.9.1 Interrupts in Normal Serial Communication Interface Mode ............................... 736 15.9.2 Interrupts in Smart Card Interface Mode .............................................................. 737 Usage Notes ....................................................................................................................... 739 15.10.1 Module Stop State Setting .................................................................................... 739 15.10.2 Break Detection and Processing ........................................................................... 739 15.10.3 Mark State and Break Detection ........................................................................... 739 15.10.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) ..................................................................... 739 15.10.5 Relation between Writing to TDR and TDRE Flag .............................................. 740 15.10.6 Restrictions on Using DTC or DMAC.................................................................. 740 15.10.7 SCI Operations during Power-Down State ........................................................... 741 CRC Operation Circuit ...................................................................................................... 744 15.11.1 Features................................................................................................................. 744 15.11.2 Register Descriptions............................................................................................ 745 15.11.3 CRC Operation Circuit Operation ........................................................................ 747 15.11.4 Note on CRC Operation Circuit............................................................................ 750 Section 16 USB Function Module (USB) ......................................................... 751 16.1 Features.............................................................................................................................. 751 16.2 Input/Output Pins............................................................................................................... 752 16.3 Register Descriptions ......................................................................................................... 753 16.3.1 Interrupt Flag Register 0 (IFR0) ........................................................................... 754 16.3.2 Interrupt Flag Register 1 (IFR1) ........................................................................... 756 16.3.3 Interrupt Flag Register 2 (IFR2) ........................................................................... 757 16.3.4 Interrupt Select Register 0 (ISR0)......................................................................... 759 Rev.1.00 Jun. 07, 2006 Page xxii of lii 16.4 16.5 16.6 16.7 16.8 16.3.5 Interrupt Select Register 1 (ISR1)......................................................................... 760 16.3.6 Interrupt Select Register 2 (ISR2)......................................................................... 761 16.3.7 Interrupt Enable Register 0 (IER0) ....................................................................... 762 16.3.8 Interrupt Enable Register 1 (IER1) ....................................................................... 763 16.3.9 Interrupt Enable Register 2 (IER2) ....................................................................... 763 16.3.10 EP0i Data Register (EPDR0i) ............................................................................... 764 16.3.11 EP0o Data Register (EPDR0o) ............................................................................. 765 16.3.12 EP0s Data Register (EPDR0s) .............................................................................. 765 16.3.13 EP1 Data Register (EPDR1) ................................................................................. 766 16.3.14 EP2 Data Register (EPDR2) ................................................................................. 766 16.3.15 EP3 Data Register (EPDR3) ................................................................................. 767 16.3.16 EP0o Receive Data Size Register (EPSZ0o) ........................................................ 767 16.3.17 EP1 Receive Data Size Register (EPSZ1) ............................................................ 768 16.3.18 Trigger Register (TRG)......................................................................................... 768 16.3.19 Data Status Register (DASTS).............................................................................. 770 16.3.20 FIFO Clear Register (FCLR) ................................................................................ 771 16.3.21 DMA Transfer Setting Register (DMA) ............................................................... 772 16.3.22 Endpoint Stall Register (EPSTL).......................................................................... 775 16.3.23 Configuration Value Register (CVR) ................................................................... 776 16.3.24 Control Register (CTLR) ...................................................................................... 776 16.3.25 Endpoint Information Register (EPIR) ................................................................. 778 16.3.26 Transceiver Test Register 0 (TRNTREG0)........................................................... 782 16.3.27 Transceiver Test Register 1 (TRNTREG1)........................................................... 784 Interrupt Sources................................................................................................................ 786 Operation ........................................................................................................................... 788 16.5.1 Cable Connection.................................................................................................. 788 16.5.2 Cable Disconnection ............................................................................................. 789 16.5.3 Suspend and Resume Operations.......................................................................... 790 16.5.4 Control Transfer.................................................................................................... 795 16.5.5 EP1 Bulk-Out Transfer (Dual FIFOs)................................................................... 801 16.5.6 EP2 Bulk-In Transfer (Dual FIFOs) ..................................................................... 802 16.5.7 EP3 Interrupt-In Transfer...................................................................................... 804 Processing of USB Standard Commands and Class/Vendor Commands........................... 805 16.6.1 Processing of Commands Transmitted by Control Transfer ................................. 805 Stall Operations.................................................................................................................. 806 16.7.1 Overview............................................................................................................... 806 16.7.2 Forcible Stall by Application ................................................................................ 806 16.7.3 Automatic Stall by USB Function Module ........................................................... 808 DMA Transfer.................................................................................................................... 809 16.8.1 Overview............................................................................................................... 809 Rev.1.00 Jun. 07, 2006 Page xxiii of lii 16.8.2 DMA Transfer for Endpoint 1 .............................................................................. 809 16.8.3 DMA Transfer for Endpoint 2 .............................................................................. 810 16.9 Example of USB External Circuitry .................................................................................. 811 16.10 Usage Notes ....................................................................................................................... 813 16.10.1 Receiving Setup Data............................................................................................ 813 16.10.2 Clearing the FIFO ................................................................................................. 813 16.10.3 Overreading and Overwriting the Data Registers ................................................. 813 16.10.4 Assigning Interrupt Sources to EP0 ...................................................................... 814 16.10.5 Clearing the FIFO When DMA Transfer is Enabled ............................................ 814 16.10.6 Notes on TR Interrupt ........................................................................................... 814 16.10.7 Restrictions on Peripheral Module Clock (P) Operating Frequency................... 815 Section 17 I C Bus Interface 2 (IIC2)................................................................817 17.1 Features.............................................................................................................................. 817 17.2 Input/Output Pins............................................................................................................... 819 17.3 Register Descriptions ......................................................................................................... 820 2 17.3.1 I C Bus Control Register A (ICCRA) ................................................................... 821 2 17.3.2 I C Bus Control Register B (ICCRB) ................................................................... 822 2 17.3.3 I C Bus Mode Register (ICMR)............................................................................ 824 2 17.3.4 I C Bus Interrupt Enable Register (ICIER) ........................................................... 825 2 17.3.5 I C Bus Status Register (ICSR)............................................................................. 828 17.3.6 Slave Address Register (SAR).............................................................................. 831 2 17.3.7 I C Bus Transmit Data Register (ICDRT) ............................................................ 832 2 17.3.8 I C Bus Receive Data Register (ICDRR).............................................................. 832 2 17.3.9 I C Bus Shift Register (ICDRS)............................................................................ 832 17.4 Operation ........................................................................................................................... 833 2 17.4.1 I C Bus Format...................................................................................................... 833 17.4.2 Master Transmit Operation ................................................................................... 834 17.4.3 Master Receive Operation .................................................................................... 836 17.4.4 Slave Transmit Operation ..................................................................................... 838 17.4.5 Slave Receive Operation....................................................................................... 841 17.4.6 Noise Canceler...................................................................................................... 842 17.4.7 Example of Use..................................................................................................... 843 17.5 Interrupt Request................................................................................................................ 847 17.6 Bit Synchronous Circuit..................................................................................................... 847 17.7 Usage Notes ....................................................................................................................... 848 2 Section 18 A/D Converter .................................................................................849 18.1 Features.............................................................................................................................. 849 18.2 Input/Output Pins............................................................................................................... 851 Rev.1.00 Jun. 07, 2006 Page xxiv of lii 18.3 Register Descriptions ......................................................................................................... 851 18.3.1 A/D Data Registers A to H (ADDRA to ADDRH) .............................................. 852 18.3.2 A/D Control/Status Register (ADCSR) ................................................................ 853 18.3.3 A/D Control Register (ADCR) ............................................................................. 855 18.4 Operation ........................................................................................................................... 856 18.4.1 Single Mode.......................................................................................................... 856 18.4.2 Scan Mode ............................................................................................................ 857 18.4.3 Input Sampling and A/D Conversion Time .......................................................... 859 18.4.4 External Trigger Input Timing.............................................................................. 860 18.5 Interrupt Source ................................................................................................................. 861 18.6 A/D Conversion Accuracy Definitions .............................................................................. 861 18.7 Usage Notes ....................................................................................................................... 863 18.7.1 Module Stop State Setting .................................................................................... 863 18.7.2 Permissible Signal Source Impedance .................................................................. 863 18.7.3 Influences on Absolute Accuracy ......................................................................... 863 18.7.4 Setting Range of Analog Power Supply and Other Pins ....................................... 864 18.7.5 Notes on Board Design ......................................................................................... 864 18.7.6 Notes on Noise Countermeasures ......................................................................... 864 18.7.7 A/D Input Hold Function in Software Standby Mode .......................................... 865 Section 19 D/A Converter..................................................................................867 19.1 Features.............................................................................................................................. 867 19.2 Input/Output Pins ............................................................................................................... 868 19.3 Register Descriptions ......................................................................................................... 868 19.3.1 D/A Data Registers 0 and 1 (DADR0 and DADR1)............................................. 868 19.3.2 D/A Control Register 01 (DACR01) .................................................................... 869 19.4 Operation ........................................................................................................................... 871 19.5 Usage Notes ....................................................................................................................... 872 19.5.1 Module Stop State Setting .................................................................................... 872 19.5.2 D/A Output Hold Function in Software Standby Mode........................................ 872 Section 20 RAM ................................................................................................873 Section 21 Flash Memory (0.18-m F-ZTAT Version) ....................................875 21.1 Features.............................................................................................................................. 875 21.2 Mode Transition Diagram.................................................................................................. 877 21.3 Block Structure .................................................................................................................. 879 21.3.1 Block Diagram of H8SX/1663.............................................................................. 879 21.3.2 Block Diagram of H8SX/1664.............................................................................. 880 21.4 Programming/Erasing Interface ......................................................................................... 881 Rev.1.00 Jun. 07, 2006 Page xxv of lii 21.5 Input/Output Pins............................................................................................................... 883 21.6 Register Descriptions ......................................................................................................... 884 21.6.1 Programming/Erasing Interface Registers ............................................................ 885 21.6.2 Programming/Erasing Interface Parameters ......................................................... 891 21.6.3 RAM Emulation Register (RAMER).................................................................... 902 21.7 On-Board Programming Mode .......................................................................................... 903 21.7.1 SCI Boot Mode ..................................................................................................... 903 21.7.2 USB Boot Mode ................................................................................................... 907 21.7.3 User Program Mode.............................................................................................. 911 21.7.4 On-Chip Program and Storable Area for Program Data ....................................... 921 21.8 Protection ........................................................................................................................... 924 21.8.1 Hardware Protection ............................................................................................. 924 21.8.2 Software Protection............................................................................................... 925 21.8.3 Error Protection .................................................................................................... 925 21.9 Flash Memory Emulation Using RAM .............................................................................. 927 21.10 Programmer Mode ............................................................................................................. 930 21.11 Standard Serial Communication Interface Specifications for Boot Mode ......................... 930 21.12 Usage Notes ....................................................................................................................... 955 Section 22 Clock Pulse Generator.....................................................................957 22.1 Register Description........................................................................................................... 959 22.1.1 System Clock Control Register (SCKCR) ............................................................ 959 22.1.2 Subclock Control Register (SUBCKCR) .............................................................. 961 22.2 Oscillator............................................................................................................................ 963 22.2.1 Connecting Crystal Resonator .............................................................................. 963 22.2.2 External Clock Input............................................................................................. 964 22.3 PLL Circuit ........................................................................................................................ 965 22.4 Frequency Divider ............................................................................................................. 965 22.5 Subclock Oscillator............................................................................................................ 965 22.5.1 Connecting 32.768 kHz Crystal Resonator........................................................... 965 22.5.2 Handling of Pins when the Subclock is Not to be Used ....................................... 966 22.6 Usage Notes ....................................................................................................................... 967 22.6.1 Notes on Clock Pulse Generator ........................................................................... 967 22.6.2 Notes on Resonator............................................................................................... 968 22.6.3 Notes on Board Design ......................................................................................... 968 Section 23 Power-Down Modes ........................................................................971 23.1 Features.............................................................................................................................. 971 23.2 Register Descriptions ......................................................................................................... 973 23.2.1 Standby Control Register (SBYCR) ..................................................................... 974 Rev.1.00 Jun. 07, 2006 Page xxvi of lii 23.3 23.4 23.5 23.6 23.7 23.8 23.9 23.10 23.11 23.2.2 Module Stop Control Registers A and B (MSTPCRA and MSTPCRB) .............. 976 23.2.3 Module Stop Control Register C (MSTPCRC)..................................................... 979 Multi-Clock Function......................................................................................................... 980 23.3.1 Switching of Main Clock ...................................................................................... 980 23.3.2 Switching to Subclock .......................................................................................... 980 Module Stop Function........................................................................................................ 981 Sleep Mode ........................................................................................................................ 981 23.5.1 Transition to Sleep Mode...................................................................................... 981 23.5.2 Clearing Sleep Mode............................................................................................. 981 All-Module-Clock-Stop Mode........................................................................................... 982 Software Standby Mode..................................................................................................... 983 23.7.1 Transition to Software Standby Mode .................................................................. 983 23.7.2 Clearing Software Standby Mode ......................................................................... 983 23.7.3 Setting Oscillation Settling Time after Clearing Software Standby Mode ........... 984 23.7.4 Software Standby Mode Application Example..................................................... 986 Hardware Standby Mode ................................................................................................... 987 23.8.1 Transition to Hardware Standby Mode................................................................. 987 23.8.2 Clearing Hardware Standby Mode........................................................................ 987 23.8.3 Hardware Standby Mode Timing.......................................................................... 987 23.8.4 Timing Sequence at Power-On ............................................................................. 988 Sleep Instruction Exception Handling ............................................................................... 989 Clock Output Control...................................................................................................... 992 Usage Notes ....................................................................................................................... 993 23.11.1 I/O Port Status....................................................................................................... 993 23.11.2 Current Consumption during Oscillation Settling Standby Period ....................... 993 23.11.3 Module Stop Mode of DMAC or DTC ................................................................. 993 23.11.4 On-Chip Peripheral Module Interrupts ................................................................. 993 23.11.5 Writing to MSTPCRA, MSTPCRB, and MSTPCRC ........................................... 993 Section 24 List of Registers ...............................................................................995 24.1 Register Addresses (Address Order).................................................................................. 996 24.2 Register Bits..................................................................................................................... 1008 24.3 Register States in Each Operating Mode.......................................................................... 1025 Section 25 Electrical Characteristics ...............................................................1039 25.1 Absolute Maximum Ratings ............................................................................................ 1039 25.2 DC Characteristics ........................................................................................................... 1040 25.3 AC Characteristics ........................................................................................................... 1043 25.3.1 Clock Timing ...................................................................................................... 1043 25.3.2 Control Signal Timing ........................................................................................ 1046 Rev.1.00 Jun. 07, 2006 Page xxvii of lii 25.4 25.5 25.6 25.7 25.3.3 Bus Timing ......................................................................................................... 1047 25.3.4 DMAC Timing.................................................................................................... 1074 25.3.5 Timing of On-Chip Peripheral Modules ............................................................. 1077 USB Characteristics ......................................................................................................... 1082 A/D Conversion Characteristics....................................................................................... 1084 D/A Conversion Characteristics....................................................................................... 1084 Flash Memory Characteristics ......................................................................................... 1085 25.7.1 H8SX/1663 ......................................................................................................... 1085 25.7.2 H8SX/1664 ......................................................................................................... 1086 Appendix A. B. C. D. .......................................................................................................1087 Port States in Each Pin State ............................................................................................ 1087 Product Lineup................................................................................................................. 1091 Package Dimensions ........................................................................................................ 1092 Treatment of Unused Pins................................................................................................ 1093 Index .......................................................................................................1095 Rev.1.00 Jun. 07, 2006 Page xxviii of lii Figures Section 1 Overview Figure 1.1 Block Diagram .............................................................................................................. 2 Figure 1.2 Pin Assignments ............................................................................................................ 3 Section 2 CPU Figure 2.1 CPU Operating Modes ................................................................................................ 23 Figure 2.2 Exception Vector Table (Normal Mode)..................................................................... 24 Figure 2.3 Stack Structure (Normal Mode) .................................................................................. 24 Figure 2.4 Exception Vector Table (Middle and Advanced Modes) ............................................ 26 Figure 2.5 Stack Structure (Middle and Advanced Modes).......................................................... 27 Figure 2.6 Exception Vector Table (Maximum Modes) ............................................................... 28 Figure 2.7 Stack Structure (Maximum Mode) .............................................................................. 28 Figure 2.8 Memory Map............................................................................................................... 29 Figure 2.9 CPU Registers ............................................................................................................. 30 Figure 2.10 Usage of General Registers ....................................................................................... 31 Figure 2.11 Stack .......................................................................................................................... 32 Figure 2.12 General Register Data Formats.................................................................................. 36 Figure 2.13 Memory Data Formats............................................................................................... 37 Figure 2.14 Instruction Formats.................................................................................................... 54 Figure 2.15 Branch Address Specification in Memory Indirect Mode ......................................... 60 Figure 2.16 State Transitions ........................................................................................................ 64 Section 3 Figure 3.1 Figure 3.1 Figure 3.2 Figure 3.2 MCU Operating Modes Address Map in Each Operating Mode of H8SX/1663 (1).......................................... 73 Address Map in Each Operating Mode of H8SX/1663 (2).......................................... 74 Address Map in Each Operating Mode of H8SX/1664 (1).......................................... 75 Address Map in Each Operating Mode of H8SX/1664 (2).......................................... 76 Section 4 Exception Handling Figure 4.1 Reset Sequence (On-chip ROM Enabled Advanced Mode)........................................ 81 Figure 4.2 Reset Sequence (16-Bit External Access in On-chip ROM Disabled Advanced Mode) ...................... 82 Figure 4.3 Stack Status after Exception Handling ........................................................................ 90 Figure 4.4 Operation when SP Value is Odd ................................................................................ 91 Section 5 Figure 5.1 Figure 5.2 Figure 5.3 Interrupt Controller Block Diagram of Interrupt Controller ........................................................................ 94 Block Diagram of Interrupts IRQn............................................................................ 110 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0... 117 Rev.1.00 Jun. 07, 2006 Page xxix of x lii Figure 5.4 Figure 5.5 Figure 5.6 Figure 5.7 Section 6 Figure 6.1 Figure 6.2 Figure 6.3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2... 119 Interrupt Exception Handling .................................................................................... 120 Block Diagram of DTC, DMAC, and Interrupt Controller ....................................... 123 Conflict between Interrupt Generation and Disabling............................................... 128 Bus Controller (BSC) Block Diagram of Bus Controller.............................................................................. 133 Read Strobe Negation Timing (Example of 3-State Access Space) .......................... 143 CS and Address Assertion Period Extension (Example of Basic Bus Interface, 3-State Access Space, and RDNn = 0)................. 145 Figure 6.4 RAS Assertion Timing (Column Address Output for 2 cycles in Full Access Mode) ................................... 160 Figure 6.5 Internal Bus Configuration ........................................................................................ 168 Figure 6.6 System Clock: External Bus Clock = 4:1, External 2-State Access .......................... 171 Figure 6.7 System Clock: External Bus Clock = 2:1, External 3-State Access .......................... 172 Figure 6.8 Address Space Area Division.................................................................................... 177 Figure 6.9 CSn Signal Output Timing (n = 0 to 7) ..................................................................... 178 Figure 6.10 Timing When CS Signal is Output to the Same Pin................................................ 179 Figure 6.11 Access Sizes and Data Alignment Control for 8-Bit Access Space (Big Endian) ........................................................................................................... 189 Figure 6.12 Access Sizes and Data Alignment Control for 8-Bit Access Space (Little Endian)......................................................................................................... 190 Figure 6.13 Access Sizes and Data Alignment Control for 16-Bit Access Space (Big Endian) ........................................................................................................... 191 Figure 6.14 Access Sizes and Data Alignment Control for 16-Bit Access Space (Little Endian)......................................................................................................... 191 Figure 6.15 16-Bit 2-State Access Space Bus Timing (Byte Access for Even Address)........... 193 Figure 6.16 16-Bit 2-State Access Space Bus Timing (Byte Access for Odd Address) ............ 194 Figure 6.17 16-Bit 2-State Access Space Bus Timing (Word Access for Even Address) ......... 195 Figure 6.18 16-Bit 3-State Access Space Bus Timing (Byte Access for Even Address)........... 196 Figure 6.19 16-Bit 3-State Access Space Bus Timing (Word Access for Odd Address) .......... 197 Figure 6.20 16-Bit 3-State Access Space Bus Timing (Word Access for Even Address) ......... 198 Figure 6.21 Example of Wait Cycle Insertion Timing................................................................ 200 Figure 6.22 Example of Read Strobe Timing ............................................................................. 201 Figure 6.23 Example of Timing when Chip Select Assertion Period is Extended ..................... 203 Figure 6.24 DACK Signal Output Timing.................................................................................. 204 Figure 6.25 16-Bit 2-State Access Space Bus Timing................................................................ 207 Figure 6.26 16-Bit 3-State Access Space Bus Timing................................................................ 208 Figure 6.27 Example of Wait Cycle Insertion Timing................................................................ 210 Figure 6.28 DACK Signal Output Timing.................................................................................. 212 Figure 6.29 Example of Burst ROM Access Timing (ASTn = 1, Two Burst Cycles)................ 215 Rev.1.00 Jun. 07, 2006 Page xxx of lii Figure 6.30 Figure 6.31 Figure 6.32 Figure 6.33 Figure 6.34 Figure 6.35 Figure 6.36 Figure 6.37 Figure 6.38 Figure 6.39 Figure 6.40 Figure 6.41 Figure 6.42 Figure 6.43 Figure 6.44 Figure 6.45 Figure 6.46 Figure 6.47 Figure 6.48 Figure 6.49 Figure 6.50 Figure 6.51 Figure 6.52 Figure 6.53 Figure 6.54 Figure 6.55 Figure 6.56 Figure 6.57 Figure 6.58 Figure 6.59 Figure 6.60 Figure 6.61 Figure 6.62 Example of Burst ROM Access Timing (ASTn = 0, One Burst Cycle) .................. 216 8-Bit Access Space Access Timing (ABWHn = 1, ABWLn = 1) ........................... 220 16-Bit Access Space Access Timing (ABWHn = 0, ABWLn = 1) ......................... 221 Access Timing of 3 Address Cycles (ADDEX = 1) ................................................ 222 Read Strobe Timing................................................................................................. 224 Chip Select (CS) Assertion Period Extension Timing in Data Cycle ...................... 225 Consecutive Read Accesses to Same Area (Address/Data Multiplexed I/O Space)................................................................... 226 DACK Signal Output Timing.................................................................................. 227 DRAM Basic Access Timing (RAS = 0 and CAST = 0) ........................................ 230 Access Timing Example of Column Address Output Cycles for 3 Clock Cycles (RAST = 0) ..................................................................................... 231 Access Timing Example of RAS Signal Driven Low at Start of Tr Cycle (CAST = 0) ............................................................................................................. 232 Access Timing Example when One Trw Cycle is Specified ................................... 233 Access Timing Example of Two Precharge Cycles (RAST = 0 and CAST = 0) .... 234 Example of Wait Cycle Insertion Timing for 2-Cycle Column Address Output..... 236 Example of Wait Cycle Insertion Timing for 3-Cycle Column Address Output..... 237 Timing Example of Byte Control with Use of Two CAS Signals (Write Access with Lowest Bit of Address = B'0, RAST = 0, CAST = 0) ............. 238 Timing Example of Word Control with Use of Two CAS Signals (Read Access with Lowest Bit of Address = B'0, RAST = 0, CAST = 0) .............. 239 Example of Connection for Control with Two CAS Signals................................... 240 Operation Timing of Fast-Page Mode (RAST = 0, CAST = 0)............................... 241 Operation Timing of Fast-Page Mode (RAST = 0, CAST = 1)............................... 242 Timing Example of RAS Down Mode (RAST = 0, CAST = 0).............................. 244 Timing Example of RAS Up Mode (RAST = 0, CAST = 0)................................... 245 RTCNT Operation................................................................................................... 246 Compare Match Timing .......................................................................................... 247 CBR Refresh Timing............................................................................................... 247 CBR Refresh Timing (RCW1 = 0, RCW0 = 1, RLW2 = 0, RLW1 = 0, RLW0 = 0) ................................ 248 Self-Refresh Timing ................................................................................................ 249 Timing Example when 1 Precharge Cycle Added................................................... 250 Output Timing Example of DACK when DDS = 1 (RAST = 0, CAST = 0) .......... 252 Output Timing Example of DACK when DDS = 0 (RAST = 0, CAST = 1) .......... 253 SDRAM Basic Read Access Timing (CAS Latency = 2) ....................................... 257 SDRAM Basic Write Access Timing ...................................................................... 258 Timing Example of CAS Latency (CAS Latency = 3)............................................ 260 Rev.1.00 Jun. 07, 2006 Page xxxi of x lii Figure 6.63 Read Timing Example of Row Address Output Retained for 1 Clock Cycle (RCD1 = 0, RCD0 = 1, CAS Latency = 2) ............................................................. 261 Figure 6.64 Write Timing Example of Row Address Output Retained for 1 Clock Cycle (RCD1 = 0, RCD0 = 1)........................................................................................... 262 Figure 6.65 Read Timing Example of Two Precharge Cycles (TPC1 = 0, TPC0 = 1, CAS Latency = 2)............................................................... 263 Figure 6.66 Write Timing Example of Two Precharge Cycles (TPC1 = 0, TPC0 = 1) .............. 264 Figure 6.67 Read Timing Example when CKSPE = 1 (CAS Latency = 2) ................................ 265 Figure 6.68 Write Timing Example when Write-Precharge Delay Cycle Insertion (TRWL = 1) ............................................................................................................ 266 Figure 6.69 Control Timing Example of Byte Control by DQM in 16-Bit Access Space (Read Access with Lowest Bit of Address = B'0)................................................... 267 Figure 6.70 Control Timing Example of Word Control by DQM in 16-Bit Access Space (Read Access with Lowest Bit of Address = B'0, CAS Latency = 2) ..................... 268 Figure 6.71 Connection Example of DQM Byte/Word Control ................................................. 269 Figure 6.72 Longword Write Timing in 16-Bit Access Space (BE = 1, RCDM = 0)................. 270 Figure 6.73 Word Read Timing in 8-Bit Access Space (BE = 1, RCDM = 0, CAS Latency = 2)................................................................. 271 Figure 6.74 Timing Example of RAS Down Mode (BE = 1, RCDM = 1, CAS Latency = 2) ... 273 Figure 6.75 Timing Example of RAS Down Mode (BE = 1, RCDM = 1, CAS Latency = 2) ... 274 Figure 6.76 Auto-Refresh Operation .......................................................................................... 276 Figure 6.77 Auto-Refresh Timing (TPC1 = 0, TPC0 = 1).......................................................... 277 Figure 6.78 Auto-Refresh Timing (TPC1 = 0, TPC0 = 0, RLW2 = 0, RLW1 = 0, RLW0 = 1).................................... 278 Figure 6.79 Self-Refresh Timing (TPC1 = 0, TPC0 = 0, RCW1 = 0, RCW0 = 0, RLW1 = 0, RLW0 = 0) ................ 279 Figure 6.80 Timing Example when 1 Precharge Cycle Added (TPC2 to TPC0 = H'1, TPC1 = 0, TPC0 = 0) ......................................................... 280 Figure 6.81 Timing of Setting SDRAM Mode Register ............................................................. 282 Figure 6.82 Output Timing Example of DACK when DDS = 1 (Write) .................................... 283 Figure 6.83 Output Timing Example of DACK when DDS = 1 (Read, CAS Latency = 2) ....... 284 Figure 6.84 Output Timing Example of DACK when DDS = 0 (Write) .................................... 285 Figure 6.85 Output Timing Example of DACK when DDS = 0 (Read, CAS Latency = 2) ....... 286 Figure 6.86 Output Timing Example of DACK when TRWL = 1 (Write)................................. 287 Figure 6.87 Output Timing Example of DACK when CKSPE = 1 (Read, CAS Latency = 2).. 288 Figure 6.88 Output Timing Example of DACK when DKC = 1 and DDS = 1 (Write).............. 289 Figure 6.89 Output Timing Example of DACK when DKC = 1 and DDS = 0 (Write).............. 290 Figure 6.90 Example of Idle Cycle Operation (Consecutive Reads in Different Areas) ............ 293 Figure 6.91 Example of Idle Cycle Operation (Write after Read) .............................................. 294 Figure 6.92 Example of Idle Cycle Operation (Read after Write) .............................................. 295 Rev.1.00 Jun. 07, 2006 Page xxxii of lii Figure 6.93 Example of Idle Cycle Operation (Write after Single Address Transfer Write)...... 296 Figure 6.94 Idle Cycle Insertion Example .................................................................................. 297 Figure 6.95 Relationship between Chip Select (CS) and Read (RD).......................................... 298 Figure 6.96 Example of DRAM Full Access after External Read (CAST = 0) .......................... 299 Figure 6.97 Example of SDRAM Full Access after External Read (CAS Latency = 2) ............ 300 Figure 6.98 Example of Idle Cycles in RAS Down Mode (Write after Read)............................ 301 Figure 6.99 Bus Released State Transition Timing (SRAM Interface is Not Used)................... 306 Figure 6.100 Bus Released State Transition Timing (SRAM Interface is Used)........................ 307 Figure 6.101 Example of Timing when Write Data Buffer Function is Used ............................ 309 Figure 6.102 Example of Timing when Peripheral Module Write Data Buffer Function is Used ..................................................................... 310 Section 7 DMA Controller (DMAC) Figure 7.1 Block Diagram of DMAC ......................................................................................... 319 Figure 7.2 Example of Signal Timing in Dual Address Mode.................................................... 344 Figure 7.3 Operations in Dual Address Mode ............................................................................ 344 Figure 7.4 Data Flow in Single Address Mode........................................................................... 345 Figure 7.5 Example of Signal Timing in Single Address Mode ................................................. 346 Figure 7.6 Operations in Single Address Mode.......................................................................... 346 Figure 7.7 Example of Signal Timing in Normal Transfer Mode............................................... 347 Figure 7.8 Operations in Normal Transfer Mode ....................................................................... 348 Figure 7.9 Operations in Repeat Transfer Mode......................................................................... 349 Figure 7.10 Operations in Block Transfer Mode ........................................................................ 350 Figure 7.11 Operation in Single Address Mode in Block Transfer Mode (Block Area Specified) ........................................................................................... 350 Figure 7.12 Operation in Dual Address Mode in Block Transfer Mode (Block Area Not Specified) .................................................................................... 351 Figure 7.13 Example of Timing in Cycle Stealing Mode ........................................................... 355 Figure 7.14 Example of Timing in Burst Mode.......................................................................... 355 Figure 7.15 Example of Extended Repeat Area Operation......................................................... 357 Figure 7.16 Example of Extended Repeat Area Function in Block Transfer Mode ................... 358 Figure 7.17 Address Update Method .......................................................................................... 359 Figure 7.18 Operation of Offset Addition................................................................................... 360 Figure 7.19 XY Conversion Operation Using Offset Addition in Repeat Transfer Mode.......... 361 Figure 7.20 XY Conversion Flowchart Using Offset Addition in Repeat Transfer Mode ......... 362 Figure 7.21 Procedure for Changing Register Setting For Channel being Transferred .............. 366 Figure 7.22 Example of Timing for Channel Priority................................................................. 369 Figure 7.23 Example of Bus Timing of DMA Transfer.............................................................. 370 Figure 7.24 Example of Transfer in Normal Transfer Mode by Cycle Stealing ......................... 371 Figure 7.25 Example of Transfer in Normal Transfer Mode by Cycle Stealing (Transfer Source DSAR = Odd Address and Source Address Increment).............. 372 Rev.1.00 Jun. 07, 2006 Page xxxiii of x lii Figure 7.26 Example of Transfer in Normal Transfer Mode by Cycle Stealing (Transfer Destination DDAR = Odd Address and Destination Address Decrement)............. 372 Figure 7.27 Example of Transfer in Normal Transfer Mode by Burst Access ........................... 373 Figure 7.28 Example of Transfer in Block Transfer Mode......................................................... 374 Figure 7.29 Example of Transfer in Normal Transfer Mode Activated by DREQ Falling Edge ........................................................................................... 375 Figure 7.30 Example of Transfer in Block Transfer Mode Activated by DREQ Falling Edge ........................................................................................... 376 Figure 7.31 Example of Transfer in Normal Transfer Mode Activated by DREQ Low Level .............................................................................................. 377 Figure 7.32 Example of Transfer in Block Transfer Mode Activated by DREQ Low Level .............................................................................................. 378 Figure 7.33 Example of Transfer in Normal Transfer Mode Activated by DREQ Low Level with NRD = 1 ...................................................................... 379 Figure 7.34 Example of Transfer in Single Address Mode (Byte Read) .................................... 380 Figure 7.35 Example of Transfer in Single Address Mode (Byte Write) ................................... 381 Figure 7.36 Example of Transfer in Single Address Mode Activated by DREQ Falling Edge ........................................................................................... 382 Figure 7.37 Example of Transfer in Single Address Mode Activated by DREQ Low Level .............................................................................................. 383 Figure 7.38 Example of Transfer in Single Address Mode Activated by DREQ Low Level with NRD = 1 ...................................................................... 384 Figure 7.39 Interrupt and Interrupt Sources................................................................................ 392 Figure 7.40 Procedure Example of Resuming Transfer by Clearing Interrupt Source ............... 392 Section 8 Figure 8.1 Figure 8.2 Figure 8.3 Figure 8.4 Figure 8.5 Figure 8.6 Figure 8.7 Figure 8.8 Data Transfer Controller (DTC) Block Diagram of DTC ............................................................................................. 396 Transfer Information on Data Area ........................................................................... 406 Correspondence between DTC Vector Address and Transfer Information............... 406 Flowchart of DTC Operation .................................................................................... 410 Bus Cycle Division Example .................................................................................... 412 Transfer Information Read Skip Timing ................................................................... 413 Memory Map in Normal Transfer Mode................................................................... 415 Memory Map in Repeat Transfer Mode (When Transfer Source is Specified as Repeat Area) ............................................... 416 Figure 8.9 Memory Map in Block Transfer Mode (When Transfer Destination is Specified as Block Area) ......................................... 417 Figure 8.10 Operation of Chain Transfer.................................................................................... 418 Figure 8.11 DTC Operation Timing (Example of Short Address Mode in Normal Transfer Mode or Repeat Transfer Mode) .............................................. 419 Rev.1.00 Jun. 07, 2006 Page xxxiv of lii Figure 8.12 DTC Operation Timing (Example of Short Address Mode in Block Transfer Mode with Block Size of 2) ........................................................ 419 Figure 8.13 DTC Operation Timing (Example of Short Address Mode in Chain Transfer) .................................................................................................... 420 Figure 8.14 DTC Operation Timing (Example of Full Address Mode in Normal Transfer Mode or Repeat Transfer Mode) .............................................. 420 Figure 8.15 DTC with Interrupt Activation ................................................................................ 423 Figure 8.16 Chain Transfer when Counter = 0 ........................................................................... 426 Section 10 16-Bit Timer Pulse Unit (TPU) Figure 10.1 Block Diagram of TPU............................................................................................ 500 Figure 10.2 Example of Counter Operation Setting Procedure .................................................. 537 Figure 10.3 Free-Running Counter Operation ............................................................................ 538 Figure 10.4 Periodic Counter Operation..................................................................................... 539 Figure 10.5 Example of Setting Procedure for Waveform Output by Compare Match.............. 539 Figure 10.6 Example of 0-Output/1-Output Operation............................................................... 540 Figure 10.7 Example of Toggle Output Operation ..................................................................... 540 Figure 10.8 Example of Setting Procedure for Input Capture Operation.................................... 541 Figure 10.9 Example of Input Capture Operation....................................................................... 542 Figure 10.10 Example of Synchronous Operation Setting Procedure ........................................ 543 Figure 10.11 Example of Synchronous Operation...................................................................... 544 Figure 10.12 Compare Match Buffer Operation ......................................................................... 545 Figure 10.13 Input Capture Buffer Operation............................................................................. 546 Figure 10.14 Example of Buffer Operation Setting Procedure................................................... 546 Figure 10.15 Example of Buffer Operation (1)........................................................................... 547 Figure 10.16 Example of Buffer Operation (2)........................................................................... 548 Figure 10.17 Example of Cascaded Operation Setting Procedure .............................................. 549 Figure 10.18 Example of Cascaded Operation (1)...................................................................... 550 Figure 10.19 Example of Cascaded Operation (2)...................................................................... 550 Figure 10.20 Example of PWM Mode Setting Procedure .......................................................... 553 Figure 10.21 Example of PWM Mode Operation (1) ................................................................. 553 Figure 10.22 Example of PWM Mode Operation (2) ................................................................. 554 Figure 10.23 Example of PWM Mode Operation (3) ................................................................. 555 Figure 10.24 Example of Phase Counting Mode Setting Procedure........................................... 557 Figure 10.25 Example of Phase Counting Mode 1 Operation .................................................... 558 Figure 10.26 Example of Phase Counting Mode 2 Operation .................................................... 559 Figure 10.27 Example of Phase Counting Mode 3 Operation .................................................... 560 Figure 10.28 Example of Phase Counting Mode 4 Operation .................................................... 561 Figure 10.29 Phase Counting Mode Application Example......................................................... 562 Figure 10.30 Count Timing in Internal Clock Operation............................................................ 566 Figure 10.31 Count Timing in External Clock Operation........................................................... 566 Rev.1.00 Jun. 07, 2006 Page xxxv of x lii Figure 10.32 Figure 10.33 Figure 10.34 Figure 10.35 Figure 10.36 Figure 10.37 Figure 10.38 Figure 10.39 Figure 10.40 Figure 10.41 Figure 10.42 Figure 10.43 Figure 10.44 Figure 10.45 Figure 10.46 Figure 10.47 Figure 10.48 Figure 10.49 Figure 10.50 Figure 10.51 Figure 10.52 Figure 10.53 Figure 10.54 Output Compare Output Timing ........................................................................... 567 Input Capture Input Signal Timing........................................................................ 567 Counter Clear Timing (Compare Match) .............................................................. 568 Counter Clear Timing (Input Capture) .................................................................. 568 Buffer Operation Timing (Compare Match).......................................................... 569 Buffer Operation Timing (Input Capture) ............................................................. 569 TGI Interrupt Timing (Compare Match) ............................................................... 570 TGI Interrupt Timing (Input Capture) ................................................................... 570 TCIV Interrupt Setting Timing.............................................................................. 571 TCIU Interrupt Setting Timing.............................................................................. 571 Timing for Status Flag Clearing by CPU .............................................................. 572 Timing for Status Flag Clearing by DTC or DMAC Activation (1)...................... 573 Timing for Status Flag Clearing by DTC or DMAC Activation (2)...................... 573 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode ................ 574 Conflict between TCNT Write and Clear Operations ........................................... 575 Conflict between TCNT Write and Increment Operations .................................... 576 Conflict between TGR Write and Compare Match ............................................... 576 Conflict between Buffer Register Write and Compare Match .............................. 577 Conflict between TGR Read and Input Capture.................................................... 578 Conflict between TGR Write and Input Capture................................................... 579 Conflict between Buffer Register Write and Input Capture .................................. 580 Conflict between Overflow and Counter Clearing ................................................ 581 Conflict between TCNT Write and Overflow ....................................................... 582 Section 11 Programmable Pulse Generator (PPG) Figure 11.1 Block Diagram of PPG............................................................................................ 583 Figure 11.2 Schematic Diagram of PPG..................................................................................... 594 Figure 11.3 Timing of Transfer and Output of NDR Contents (Example) ................................. 594 Figure 11.4 Setup Procedure for Normal Pulse Output (Example) ............................................ 595 Figure 11.5 Normal Pulse Output Example (5-Phase Pulse Output) .......................................... 596 Figure 11.6 Non-Overlapping Pulse Output ............................................................................... 597 Figure 11.7 Non-Overlapping Operation and NDR Write Timing ............................................. 598 Figure 11.8 Setup Procedure for Non-Overlapping Pulse Output (Example)............................. 599 Figure 11.9 Non-Overlapping Pulse Output Example (4-Phase Complementary) ..................... 600 Figure 11.10 Inverted Pulse Output (Example) .......................................................................... 602 Figure 11.11 Pulse Output Triggered by Input Capture (Example)............................................ 603 Section 12 Figure 12.1 Figure 12.2 Figure 12.3 8-Bit Timers (TMR) Block Diagram of 8-Bit Timer Module (Unit 0) ..................................................... 606 Block Diagram of 8-Bit Timer Module (Unit 1) ..................................................... 607 Block Diagram of 8-Bit Timer Module (Unit 2) ..................................................... 608 Rev.1.00 Jun. 07, 2006 Page xxxvi of lii Figure 12.4 Block Diagram of 8-Bit Timer Module (Unit 3) ..................................................... 609 Figure 12.5 Example of Pulse Output......................................................................................... 624 Figure 12.6 Example of Reset Input ........................................................................................... 624 Figure 12.7 Count Timing for Internal Clock Input.................................................................... 625 Figure 12.8 Count Timing for External Clock Input .................................................................. 625 Figure 12.9 Timing of CMF Setting at Compare Match............................................................. 626 Figure 12.10 Timing of Toggled Timer Output at Compare Match A ....................................... 626 Figure 12.11 Timing of Counter Clear by Compare Match........................................................ 627 Figure 12.12 Timing of Clearance by External Reset (Rising Edge).......................................... 627 Figure 12.13 Timing of Clearance by External Reset (High Level) ........................................... 627 Figure 12.14 Timing of OVF Setting.......................................................................................... 628 Figure 12.15 Conflict between TCNT Write and Clear .............................................................. 631 Figure 12.16 Conflict between TCNT Write and Increment ...................................................... 632 Figure 12.17 Conflict between TCOR Write and Compare Match............................................. 632 Section 13 32K Timer (TM32K) Figure 13.1 Block Diagram of TM32K ...................................................................................... 637 Figure 13.2 32K Timer Operation .............................................................................................. 639 Section 14 Figure 14.1 Figure 14.2 Figure 14.3 Figure 14.4 Figure 14.5 Figure 14.6 Section 15 Figure 15.1 Figure 15.2 Figure 15.3 Figure 15.3 Figure 15.3 Figure 15.4 Figure 15.5 Figure 15.6 Figure 15.7 Figure 15.8 Figure 15.9 Watchdog Timer (WDT) Block Diagram of WDT .......................................................................................... 642 Operation in Watchdog Timer Mode....................................................................... 647 Operation in Interval Timer Mode........................................................................... 648 Writing to TCNT, TCSR, and RSTCSR.................................................................. 649 Conflict between TCNT Write and Increment ........................................................ 650 Circuit for System Reset by WDTOVF Signal (Example)...................................... 651 Serial Communication Interface (SCI, IrDA, CRC) Block Diagram of SCI_0, 1, 2, and 4 ...................................................................... 656 Block Diagram of SCI_5 and SCI_6 ....................................................................... 657 Examples of Base Clock when Average Transfer Rate Is Selected (1) ................... 693 Examples of Base Clock when Average Transfer Rate Is Selected (2) ................... 694 Examples of Base Clock when Average Transfer Rate Is Selected (3) ................... 695 Example of Average Transfer Rate Setting when TMR Clock Is Input .................. 696 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) ................................................. 698 Receive Data Sampling Timing in Asynchronous Mode ........................................ 700 Phase Relation between Output Clock and Transmit Data (Asynchronous Mode) ............................................................................................ 701 Sample SCI Initialization Flowchart ....................................................................... 702 Example of Operation for Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit).................................................... 703 Rev.1.00 Jun. 07, 2006 Page xxxvii of x lii Figure 15.10 Example of Serial Transmission Flowchart........................................................... 704 Figure 15.11 Example of SCI Operation for Reception (Example with 8-Bit Data, Parity, One Stop Bit).................................................. 705 Figure 15.12 Sample Serial Reception Flowchart (1)................................................................. 707 Figure 15.12 Sample Serial Reception Flowchart (2)................................................................. 708 Figure 15.13 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A).......................................... 710 Figure 15.14 Sample Multiprocessor Serial Transmission Flowchart ........................................ 711 Figure 15.15 Example of SCI Operation for Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) ........................................................................................ 712 Figure 15.16 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 713 Figure 15.16 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 714 Figure 15.17 Data Format in Clocked Synchronous Communication (LSB-First)..................... 715 Figure 15.18 Sample SCI Initialization Flowchart ..................................................................... 716 Figure 15.19 Example of Operation for Transmission in Clocked Synchronous Mode ............. 718 Figure 15.20 Sample Serial Transmission Flowchart ................................................................. 718 Figure 15.21 Example of Operation for Reception in Clocked Synchronous Mode .................. 719 Figure 15.22 Sample Serial Reception Flowchart ...................................................................... 720 Figure 15.23 Sample Flowchart of Simultaneous Serial Transmission and Reception .............. 721 Figure 15.24 Pin Connection for Smart Card Interface .............................................................. 722 Figure 15.25 Data Formats in Normal Smart Card Interface Mode ........................................... 723 Figure 15.26 Direct Convention (SDIR = SINV = O/E = 0) ...................................................... 723 Figure 15.27 Inverse Convention (SDIR = SINV = O/E = 1) .................................................... 724 Figure 15.28 Receive Data Sampling Timing in Smart Card Interface Mode (When Clock Frequency is 372 Times the Bit Rate) ............................................ 725 Figure 15.29 Data Re-Transfer Operation in SCI Transmission Mode ...................................... 728 Figure 15.30 TEND Flag Set Timing during Transmission........................................................ 728 Figure 15.31 Sample Transmission Flowchart ........................................................................... 729 Figure 15.32 Data Re-Transfer Operation in SCI Reception Mode............................................ 730 Figure 15.33 Sample Reception Flowchart................................................................................. 731 Figure 15.34 Clock Output Fixing Timing ................................................................................. 731 Figure 15.35 Clock Stop and Restart Procedure......................................................................... 732 Figure 15.36 IrDA Block Diagram ............................................................................................. 733 Figure 15.37 IrDA Transmission and Reception ........................................................................ 734 Figure 15.38 Sample Transmission using DTC in Clocked Synchronous Mode........................ 740 Figure 15.39 Sample Flowchart for Software Standby Mode Transition during Transmission .............................................................................................. 742 Figure 15.40 Port Pin States during Software Standby Mode Transition (Internal Clock, Asynchronous Transmission) ..................................................... 742 Rev.1.00 Jun. 07, 2006 Page xxxviii of lii Figure 15.41 Port Pin States during Software Standby Mode Transition (Internal Clock, Clocked Synchronous Transmission) (Setting is Prohibited in SCI_5 and SCI_6) .......................................................... 743 Figure 15.42 Sample Flowchart for Software Standby Mode Transition during Reception....... 743 Figure 15.43 Block Diagram of CRC Operation Circuit ............................................................ 744 Figure 15.44 LSB-First Data Transmission ................................................................................ 747 Figure 15.45 MSB-First Data Transmission ............................................................................... 747 Figure 15.46 LSB-First Data Reception ..................................................................................... 748 Figure 15.47 MSB-First Data Reception .................................................................................... 749 Figure 15.48 LSB-First and MSB-First Transmit Data .............................................................. 750 Section 16 USB Function Module (USB) Figure 16.1 Block Diagram of USB ........................................................................................... 752 Figure 16.2 Cable Connection Operation ................................................................................... 788 Figure 16.3 Cable Disconnection Operation............................................................................... 789 Figure 16.4 Suspend Operation .................................................................................................. 790 Figure 16.5 Resume Operation from Up-Stream ........................................................................ 791 Figure 16.6 Flow of Transition to and Canceling Software Standby Mode................................ 792 Figure 16.7 Timing of Transition to and Canceling Software Standby Mode ............................ 793 Figure 16.8 Remote-Wakeup ...................................................................................................... 794 Figure 16.9 Transfer Stages in Control Transfer ........................................................................ 795 Figure 16.10 Setup Stage Operation ........................................................................................... 796 Figure 16.11 Data Stage (Control-In) Operation ........................................................................ 797 Figure 16.12 Data Stage (Control-Out) Operation...................................................................... 798 Figure 16.13 Status Stage (Control-In) Operation ...................................................................... 799 Figure 16.14 Status Stage (Control-Out) Operation ................................................................... 800 Figure 16.15 EP1 Bulk-Out Transfer Operation......................................................................... 801 Figure 16.16 EP2 Bulk-In Transfer Operation............................................................................ 802 Figure 16.17 Operation of EP3 Interrupt-In Transfer ................................................................. 804 Figure 16.18 Forcible Stall by Application................................................................................. 807 Figure 16.19 Automatic Stall by USB Function Module............................................................ 808 Figure 16.20 RDFN Bit Operation for EP1 ................................................................................ 809 Figure 16.21 PKTE Bit Operation for EP2 ................................................................................. 810 Figure 16.22 Example of Circuitry in Bus Power Mode ............................................................ 811 Figure 16.23 Example of Circuitry in Self Power Mode ............................................................ 812 Figure 16.24 TR Interrupt Flag Set Timing ................................................................................ 814 Section 17 Figure 17.1 Figure 17.2 Figure 17.3 I2C Bus Interface2 (IIC2) Block Diagram of I2C Bus Interface 2..................................................................... 818 Connections to the External Circuit by the I/O Pins................................................ 819 I2C Bus Formats ...................................................................................................... 833 Rev.1.00 Jun. 07, 2006 Page xxxix of x lii Figure 17.4 I2C Bus Timing........................................................................................................ 833 Figure 17.5 Master Transmit Mode Operation Timing 1............................................................ 835 Figure 17.6 Master Transmit Mode Operation Timing 2............................................................ 835 Figure 17.7 Master Receive Mode Operation Timing 1 ............................................................. 837 Figure 17.8 Master Receive Mode Operation Timing 2 ............................................................. 838 Figure 17.9 Slave Transmit Mode Operation Timing 1.............................................................. 839 Figure 17.10 Slave Transmit Mode Operation Timing 2............................................................ 840 Figure 17.11 Slave Receive Mode Operation Timing 1 ............................................................. 841 Figure 17.12 Slave Receive Mode Operation Timing 2 ............................................................. 842 Figure 17.13 Block Diagram of Noise Canceler......................................................................... 842 Figure 17.14 Sample Flowchart of Master Transmit Mode........................................................ 843 Figure 17.15 Sample Flowchart for Master Receive Mode ........................................................ 844 Figure 17.16 Sample Flowchart for Slave Transmit Mode......................................................... 845 Figure 17.17 Sample Flowchart for Slave Receive Mode .......................................................... 846 Figure 17.18 Timing of the Bit Synchronous Circuit ................................................................. 848 Section 18 Figure 18.1 Figure 18.2 Figure 18.3 A/D Converter Block Diagram of A/D Converter ........................................................................... 850 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) ............ 857 Example of A/D Conversion (Scan Mode, Three Channels (AN0 to AN2) Selected) .......................................... 858 Figure 18.4 A/D Conversion Timing .......................................................................................... 859 Figure 18.5 External Trigger Input Timing ................................................................................ 860 Figure 18.6 A/D Conversion Accuracy Definitions.................................................................... 862 Figure 18.7 A/D Conversion Accuracy Definitions.................................................................... 862 Figure 18.8 Example of Analog Input Circuit ............................................................................ 863 Figure 18.9 Example of Analog Input Protection Circuit ........................................................... 865 Figure 18.10 Analog Input Pin Equivalent Circuit ..................................................................... 865 Section 19 D/A Converter Figure 19.1 Block Diagram of D/A Converter ........................................................................... 867 Figure 19.2 Example of D/A Converter Operation..................................................................... 871 Section 21 Figure 21.1 Figure 21.2 Figure 21.3 Figure 21.4 Figure 21.5 Figure 21.6 Figure 21.7 Figure 21.8 Flash Memory (0.18-m F-ZTAT Version) Block Diagram of Flash Memory............................................................................ 876 Mode Transition of Flash Memory.......................................................................... 877 Block Structure of User MAT ................................................................................. 879 Block Structure of User MAT ................................................................................. 880 Procedure for Creating Procedure Program............................................................. 881 System Configuration in SCI Boot Mode................................................................ 903 Automatic-Bit-Rate Adjustment Operation............................................................. 904 SCI Boot Mode State Transition Diagram .............................................................. 905 Rev.1.00 Jun. 07, 2006 Page xl of lii Figure 21.9 System Configuration in USB Boot Mode .............................................................. 907 Figure 21.10 USB Boot Mode State Transition Diagram ........................................................... 909 Figure 21.11 Programming/Erasing Flow................................................................................... 911 Figure 21.12 RAM Map when Programming/Erasing is Executed ............................................ 912 Figure 21.13 Programming Procedure in User Program Mode .................................................. 913 Figure 21.14 Erasing Procedure in User Program Mode ............................................................ 918 Figure 21.15 Repeating Procedure of Erasing, Programming, and RAM Emulation in User Program Mode ....................................................... 920 Figure 21.16 Transitions to Error Protection State ..................................................................... 926 Figure 21.17 RAM Emulation Flow ........................................................................................... 927 Figure 21.18 Address Map of Overlaid RAM Area (H8SX/1663) ............................................. 928 Figure 21.19 Programming Tuned Data (H8SX/1663)............................................................... 929 Figure 21.20 Boot Program States .............................................................................................. 931 Figure 21.21 Bit-Rate-Adjustment Sequence ............................................................................. 932 Figure 21.22 Communication Protocol Format .......................................................................... 933 Figure 21.23 New Bit-Rate Selection Sequence ......................................................................... 944 Figure 21.24 Programming Sequence......................................................................................... 947 Figure 21.25 Erasure Sequence .................................................................................................. 947 Section 22 Clock Pulse Generator Figure 22.1 Block Diagram of Clock Pulse Generator ............................................................... 958 Figure 22.2 Connection of Crystal Resonator (Example) ........................................................... 963 Figure 22.3 Crystal Resonator Equivalent Circuit ...................................................................... 964 Figure 22.4 External Clock Input (Examples) ............................................................................ 964 Figure 22.5 External Clock Input Timing................................................................................... 965 Figure 22.6 Connection Example of 32.768-kHz Crystal Resonator.......................................... 965 Figure 22.7 Equivalent Circuit for 32.768-kHz Crystal Resonator............................................. 966 Figure 22.8 Pin Handling when Subclock is not Used ............................................................... 966 Figure 22.9 Clock Modification Timing ..................................................................................... 968 Figure 22.10 Note on Board Design for Oscillation Circuit ....................................................... 968 Figure 22.11 Recommended External Circuitry for PLL Circuit................................................ 969 Section 23 Figure 23.1 Figure 23.2 Figure 23.3 Figure 23.4 Figure 23.5 Power-Down Modes Mode Transitions..................................................................................................... 973 Software Standby Mode Application Example ....................................................... 986 Hardware Standby Mode Timing ............................................................................ 987 Timing Sequence at Power-On................................................................................ 988 When Canceling Factor Interrupt is Generated after SLEEP Instruction Execution ......................................................................... 990 Figure 23.6 When Canceling Factor Interrupt is Generated Immediately before SLEEP Instruction Execution (Sleep Instruction Exception Handling Not Initiated) ......... 990 Rev.1.00 Jun. 07, 2006 Page xli of x lii Figure 23.7 When Canceling Factor Interrupt is Generated Immediately before SLEEP Instruction Execution (Sleep Instruction Exception Handling Initiated) ................ 991 Section 25 Electrical Characteristics Figure 25.1 Output Load Circuit .............................................................................................. 1043 Figure 25.2 External Bus Clock Timing ................................................................................... 1044 Figure 25.3 Oscillation Settling Timing after Software Standby Mode ................................... 1044 Figure 25.4 Oscillation Settling Timing ................................................................................... 1045 Figure 25.5 External Input Clock Timing................................................................................. 1045 Figure 25.6 Reset Input Timing................................................................................................ 1046 Figure 25.7 Interrupt Input Timing........................................................................................... 1047 Figure 25.8 Basic Bus Timing: Two-State Access ................................................................... 1052 Figure 25.9 Basic Bus Timing: Three-State Access ................................................................. 1053 Figure 25.10 Basic Bus Timing: Three-State Access, One Wait.............................................. 1054 Figure 25.11 Basic Bus Timing: Two-State Access (CS Assertion Period Extended) ............. 1055 Figure 25.12 Basic Bus Timing: Three-State Access (CS Assertion Period Extended) ........... 1056 Figure 25.13 Byte Control SRAM: Two-State Read/Write Access.......................................... 1057 Figure 25.14 Byte Control SRAM: Three-State Read/Write Access........................................ 1058 Figure 25.15 Burst ROM Access Timing: One-State Burst Access ......................................... 1059 Figure 25.16 Burst ROM Access Timing: Two-State Burst Access......................................... 1060 Figure 25.17 Address/Data Multiplexed Access Timing (No Wait) (Basic, Four-State Access).................................................................................. 1061 Figure 25.18 Address/Data Multiplexed Access Timing (Wait Control) (Address Cycle Program Wait x 1 + Data Cycle Program Wait x 1 + Data Cycle Pin Wait x 1)................................................................................ 1062 Figure 25.19 DRAM Access Timing: Two-State Access ......................................................... 1063 Figure 25.20 DRAM Access Timing: Two-State Access, One Wait........................................ 1064 Figure 25.21 DRAM Access Timing: Two-State Burst Access ............................................... 1065 Figure 25.22 DRAM Access Timing: Three-State Access (RAST = 1) ................................... 1066 Figure 25.23 DRAM Access Timing: Three-State Access, One Wait...................................... 1067 Figure 25.24 DRAM Access Timing: Three-State Burst Access ............................................. 1068 Figure 25.25 CAS Before RAS Refresh Timing ...................................................................... 1069 Figure 25.26 CAS Before RAS Refresh Timing (Wait Cycle Inserted) ................................... 1069 Figure 25.27 Self-Refresh Timing (After Leaving Software Standby: RAST = 0) .................. 1069 Figure 25.28 Self-Refresh Timing (After Leaving Software Standby: RAST = 1) .................. 1070 Figure 25.29 Synchronous DRAM Basic Read Access Timing (CAS Latency 2) ................... 1070 Figure 25.30 Synchronous DRAM Basic Write Access Timing (CAS Latency 2) .................. 1071 Figure 25.31 Extended Read Data Cycle (CAS Latency 2)...................................................... 1072 Figure 25.32 Synchronous DRAM Self-Refresh Timing ......................................................... 1073 Figure 25.33 External Bus Release Timing .............................................................................. 1073 Figure 25.34 External Bus Request Output Timing.................................................................. 1074 Rev.1.00 Jun. 07, 2006 Page xlii of lii Figure 25.35 Figure 25.36 Figure 25.37 Figure 25.38 Figure 25.39 Figure 25.40 Figure 25.41 Figure 25.42 Figure 25.43 Figure 25.44 Figure 25.45 Figure 25.46 Figure 25.47 Figure 25.48 Figure 25.49 Figure 25.50 Figure 25.51 Figure 25.52 DMAC (DREQ) Input Timing ............................................................................ 1074 DMAC (TEND) Output Timing .......................................................................... 1075 DMAC Single-Address Transfer Timing: Two-State Access ............................. 1075 DMAC Single-Address Transfer Timing: Three-State Access ........................... 1076 I/O Port Input/Output Timing.............................................................................. 1079 TPU Input/Output Timing ................................................................................... 1079 TPU Clock Input Timing..................................................................................... 1079 PPG Output Timing............................................................................................. 1079 8-Bit Timer Output Timing ................................................................................. 1080 8-Bit Timer Reset Input Timing .......................................................................... 1080 8-Bit Timer Clock Input Timing ......................................................................... 1080 WDT Output Timing ........................................................................................... 1080 SCK Clock Input Timing..................................................................................... 1080 SCI Input/Output Timing: Clocked Synchronous Mode ..................................... 1081 A/D Converter External Trigger Input Timing.................................................... 1081 I2C Bus Interface2 Input/Output Timing (Option) .............................................. 1081 Data Signal Timing.............................................................................................. 1083 Load Condition.................................................................................................... 1083 Appendix Figure C.1 Package Dimensions (FP-144LV) .......................................................................... 1092 Rev.1.00 Jun. 07, 2006 Page xliii of x lii Rev.1.00 Jun. 07, 2006 Page xliv of lii Tables Section 1 Overview Table 1.1 Pin Configuration in Each Operating Mode.............................................................. 4 Table 1.2 Pin Functions ............................................................................................................ 9 Section 2 CPU Table 2.1 Instruction Classification ........................................................................................ 38 Table 2.2 Combinations of Instructions and Addressing Modes (1)....................................... 40 Table 2.2 Combinations of Instructions and Addressing Modes (2)....................................... 43 Table 2.3 Operation Notation ................................................................................................. 44 Table 2.4 Data Transfer Instructions....................................................................................... 45 Table 2.5 Block Transfer Instructions..................................................................................... 46 Table 2.6 Arithmetic Operation Instructions .......................................................................... 47 Table 2.7 Logic Operation Instructions .................................................................................. 49 Table 2.8 Shift Operation Instructions .................................................................................... 49 Table 2.9 Bit Manipulation Instructions ................................................................................. 50 Table 2.10 Branch Instructions ................................................................................................. 52 Table 2.11 System Control Instructions.................................................................................... 53 Table 2.12 Addressing Modes .................................................................................................. 55 Table 2.13 Absolute Address Access Ranges ........................................................................... 58 Table 2.14 Effective Address Calculation for Transfer and Operation Instructions ................. 62 Table 2.15 Effective Address Calculation for Branch Instructions........................................... 63 Section 3 MCU Operating Modes Table 3.1 MCU Operating Mode Settings .............................................................................. 65 Table 3.2 SDRAM Interface Selection for MCU Operating Mode......................................... 65 Table 3.3 Settings of Bits MDS3 to MDS0............................................................................. 67 Table 3.4 Pin Functions in Each Operating Mode (Advanced Mode) .................................... 72 Section 4 Exception Handling Table 4.1 Exception Types and Priority.................................................................................. 77 Table 4.2 Exception Handling Vector Table........................................................................... 78 Table 4.3 Calculation Method of Exception Handling Vector Table Address........................ 80 Table 4.4 Status of CCR and EXR after Trace Exception Handling....................................... 83 Table 4.5 Bus Cycle and Address Error.................................................................................. 84 Table 4.6 Status of CCR and EXR after Address Error Exception Handling ......................... 85 Table 4.7 Interrupt Sources..................................................................................................... 86 Table 4.8 Status of CCR and EXR after Trap Instruction Exception Handling...................... 88 Table 4.9 Status of CCR and EXR after Sleep Instruction Exception Handling..................... 89 Table 4.10 Status of CCR and EXR after Illegal Instruction Exception Handling ................... 90 Rev.1.00 Jun. 07, 2006 Page xlv of lii Section 5 Interrupt Controller Table 5.1 Pin Configuration.................................................................................................... 95 Table 5.2 Interrupt Sources, Vector Address Offsets, and Interrupt Priority........................ 111 Table 5.3 Interrupt Control Modes ....................................................................................... 116 Table 5.4 Interrupt Response Times ..................................................................................... 121 Table 5.5 Number of Execution States in Interrupt Handling Routine ................................. 122 Table 5.6 Interrupt Source Selection and Clear Control ....................................................... 124 Table 5.7 CPU Priority Control ............................................................................................ 126 Table 5.8 Example of Priority Control Function Setting and Control State ......................... 127 Section 6 Bus Controller (BSC) Table 6.1 Synchronization Clocks and Their Corresponding Functions............................... 169 Table 6.2 Pin Configuration.................................................................................................. 173 Table 6.3 Pin Functions in Each Interface ............................................................................ 176 Table 6.4 Interface Names and Area Names......................................................................... 179 Table 6.5 Areas Specifiable for Each Interface .................................................................... 180 Table 6.6 Number of Access Cycles..................................................................................... 183 Table 6.7 Area 0 External Interface ...................................................................................... 184 Table 6.8 Area 1 External Interface ...................................................................................... 185 Table 6.9 Area 2 External Interface ...................................................................................... 185 Table 6.10 Area 3 External Interface ...................................................................................... 186 Table 6.11 Area 4 External Interface ...................................................................................... 186 Table 6.12 Area 5 External Interface ...................................................................................... 187 Table 6.13 Area 6 External Interface ...................................................................................... 188 Table 6.14 Area 7 External Interface ...................................................................................... 188 Table 6.15 I/O Pins for Basic Bus Interface ........................................................................... 192 Table 6.16 I/O Pins for Byte Control SRAM Interface .......................................................... 206 Table 6.17 I/O Pins Used for Burst ROM Interface................................................................ 214 Table 6.18 Address/Data Multiplex ........................................................................................ 218 Table 6.19 I/O Pins for Address/Data Multiplexed I/O Interface ........................................... 219 Table 6.20 Relationship Among DRAME and DTYPE and Area 2 Interfaces ...................... 228 Table 6.21 Relationship Among MXC1 and MXC0 and Shifted Bit Count........................... 228 Table 6.22 I/O Pins for DRAM Interface ............................................................................... 229 Table 6.23 Pin States during DRAM Refresh Cycle............................................................... 248 Table 6.24 Relationship among DRAME and DTYPE and Area 2 Interfaces ....................... 254 Table 6.25 Relationship Among MXC1 and MXC0 and Shifted Bit Count........................... 255 Table 6.26 I/O Pins for SDRAM Interface ............................................................................. 256 Table 6.27 CAS Latency Setting ............................................................................................ 259 Table 6.28 Number of Idle Cycle Insertion Selection in Each Area....................................... 292 Table 6.29 Number of Idle Cycles Inserted ............................................................................ 292 Table 6.30 Idle Cycles in Mixed Accesses to Normal Space and DRAM/SDRAM Space .... 302 Rev.1.00 Jun. 07, 2006 Page xlvi of lii Table 6.31 Table 6.32 Table 6.33 Table 6.34 Pin States in Idle Cycle ......................................................................................... 303 Pin States in Bus Released State ........................................................................... 305 Number of Access Cycles for On-Chip Memory Spaces...................................... 308 Number of Access Cycles for Registers of On-Chip Peripheral Modules ............ 308 Section 7 DMA Controller (DMAC) Table 7.1 Pin Configuration.................................................................................................. 320 Table 7.2 Data Access Size, Valid Bits, and Settable Size ................................................... 327 Table 7.3 Settings and Areas of Extended Repeat Area ....................................................... 341 Table 7.4 Transfer Modes ..................................................................................................... 342 Table 7.5 List of On-chip module interrupts to DMAC........................................................ 353 Table 7.6 Priority among DMAC Channels.......................................................................... 368 Table 7.7 Interrupt Sources and Priority ............................................................................... 390 Section 8 Data Transfer Controller (DTC) Table 8.1 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs............... 407 Table 8.2 DTC Transfer Modes ............................................................................................ 409 Table 8.3 Chain Transfer Conditions .................................................................................... 411 Table 8.4 Number of Bus Cycle Divisions and Access Size................................................. 411 Table 8.5 Transfer Information Writeback Skip Condition and Writeback Skipped Registers ......................................................................... 414 Table 8.6 Register Function in Normal Transfer Mode ........................................................ 414 Table 8.7 Register Function in Repeat Transfer Mode ......................................................... 416 Table 8.8 Register Function in Block Transfer Mode........................................................... 417 Table 8.9 DTC Execution Status........................................................................................... 421 Table 8.10 Number of Cycles Required for Each Execution State ......................................... 422 Section 9 I/O Ports Table 9.1 Port Functions ....................................................................................................... 429 Table 9.2 Register Configuration in Each Port ..................................................................... 436 Table 9.3 Startup Mode and Initial Value............................................................................. 437 Table 9.4 Input Pull-Up MOS State...................................................................................... 440 Table 9.5 Available Output Signals and Settings in Each Port ............................................. 476 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.1 TPU Functions ...................................................................................................... 498 Table 10.2 Pin Configuration.................................................................................................. 501 Table 10.3 CCLR2 to CCLR0 (Channels 0 and 3) ................................................................. 505 Table 10.4 CCLR2 to CCLR0 (Channels 1, 2, 4, and 5) ........................................................ 505 Table 10.5 Input Clock Edge Selection .................................................................................. 506 Table 10.6 TPSC2 to TPSC0 (Channel 0) .............................................................................. 506 Table 10.7 TPSC2 to TPSC0 (Channel 1) .............................................................................. 506 Rev.1.00 Jun. 07, 2006 Page xlvii of lii Table 10.8 Table 10.9 Table 10.10 Table 10.11 Table 10.12 Table 10.13 Table 10.14 Table 10.15 Table 10.16 Table 10.17 Table 10.18 Table 10.19 Table 10.20 Table 10.21 Table 10.22 Table 10.23 Table 10.24 Table 10.25 Table 10.26 Table 10.27 Table 10.28 Table 10.29 Table 10.30 Table 10.31 Table 10.32 Table 10.33 Table 10.34 Table 10.35 Table 10.36 Table 10.37 TPSC2 to TPSC0 (Channel 2) .............................................................................. 507 TPSC2 to TPSC0 (Channel 3) .............................................................................. 507 TPSC2 to TPSC0 (Channel 4) .......................................................................... 508 TPSC2 to TPSC0 (Channel 5) .......................................................................... 508 MD3 to MD0 .................................................................................................... 510 TIORH_0 .......................................................................................................... 512 TIORL_0........................................................................................................... 513 TIOR_1 ............................................................................................................. 514 TIOR_2 ............................................................................................................. 515 TIORH_3 .......................................................................................................... 516 TIORL_3........................................................................................................... 517 TIOR_4 ............................................................................................................. 518 TIOR_5 ............................................................................................................. 519 TIORH_0 .......................................................................................................... 520 TIORL_0........................................................................................................... 521 TIOR_1 ............................................................................................................. 522 TIOR_2 ............................................................................................................. 523 TIORH_3 .......................................................................................................... 524 TIORL_3........................................................................................................... 525 TIOR_4 ............................................................................................................. 526 TIOR_5 ............................................................................................................. 527 Register Combinations in Buffer Operation ..................................................... 545 Cascaded Combinations.................................................................................... 549 PWM Output Registers and Output Pins .......................................................... 552 Clock Input Pins in Phase Counting Mode ....................................................... 556 Up/Down-Count Conditions in Phase Counting Mode 1.................................. 558 Up/Down-Count Conditions in Phase Counting Mode 2.................................. 559 Up/Down-Count Conditions in Phase Counting Mode 3.................................. 560 Up/Down-Count Conditions in Phase Counting Mode 4.................................. 561 TPU Interrupts .................................................................................................. 563 Section 11 Programmable Pulse Generator (PPG) Table 11.1 Pin Configuration.................................................................................................. 584 Section 12 8-Bit Timers (TMR) Table 12.1 Pin Configuration.................................................................................................. 610 Table 12.2 Clock Input to TCNT and Count Condition (Units 0 and 1)................................. 617 Table 12.3 Clock Input to TCNT and Count Condition (Units 2 and 3)................................. 618 Table 12.4 8-Bit Timer (TMR_0 or TMR_1) Interrupt Sources (in Unit 0 and Unit 1) ......... 629 Table 12.5 8-Bit Timer (TMR_4 or TMR_5) Interrupt Sources (in Unit 2 and Unit 3) ......... 630 Table 12.6 Timer Output Priorities......................................................................................... 633 Rev.1.00 Jun. 07, 2006 Page xlviii of lii Table 12.7 Switching of Internal Clock and TCNT Operation ............................................... 634 Section 13 32K Timer (TM32K) Table 13.1 TM32K Interrupt Source....................................................................................... 640 Section 14 Watchdog Timer (WDT) Table 14.1 Pin Configuration.................................................................................................. 642 Table 14.2 WDT Interrupt Source .......................................................................................... 648 Section 15 Serial Communication Interface (SCI, IrDA, CRC) Table 15.1 Function List of SCI Channels.............................................................................. 655 Table 15.2 Pin Configuration.................................................................................................. 658 Table 15.3 Relationships between N Setting in BRR and Bit Rate B..................................... 681 Table 15.4 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ...... 682 Table 15.4 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) ...... 683 Table 15.5 Maximum Bit Rate for Each Operating Frequency (Asynchronous Mode).......... 684 Table 15.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode) ................ 685 Table 15.7 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)..................... 686 Table 15.8 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) .... 686 Table 15.9 BRR Settings for Various Bit Rates (Smart Card Interface Mode, n = 0, S = 372)........................................................ 687 Table 15.10 Maximum Bit Rate for Each Operating Frequency (Smart Card Interface Mode, S = 372).............................................................. 687 Table 15.11 Serial Transfer Formats (Asynchronous Mode)................................................ 699 Table 15.12 SSR Status Flags and Receive Data Handling .................................................. 706 Table 15.13 IrCKS2 to IrCKS0 Bit Settings......................................................................... 735 Table 15.14 SCI Interrupt Sources (SCI_0, 1, 2, and 4) ....................................................... 736 Table 15.15 SCI Interrupt Sources (SCI_5 and SCI_6) ........................................................ 737 Table 15.16 SCI Interrupt Sources (SCI_0, 1, 2, and 4) ....................................................... 737 Table 15.17 SCI Interrupt Sources (SCI_5 and SCI_6) ........................................................ 737 Section 16 USB Function Module (USB) Table 16.1 Pin Configuration.................................................................................................. 752 Table 16.2 Example of Limitations for Setting Values........................................................... 780 Table 16.3 Example of Setting................................................................................................ 781 Table 16.4 Relationship between TRNTREG0 Setting and Pin Output ................................. 783 Table 16.5 Relationship between Pin Input and TRNTREG1 Monitoring Value................... 785 Table 16.6 Interrupt Sources................................................................................................... 786 Table 16.7 Command Decoding on Application Side............................................................. 805 Table 16.8 Selection of Peripheral Clock (P) when USB is Connected................................ 815 Section 17 I2C Bus Interface2 (IIC2) Table 17.1 Pin Configuration of the I2C Bus Interface 2 ........................................................ 819 Rev.1.00 Jun. 07, 2006 Page xlix of lii Table 17.2 Table 17.3 Table 17.4 Transfer Rate ........................................................................................................ 822 Interrupt Requests ................................................................................................. 847 Time for Monitoring SCL..................................................................................... 848 Section 18 A/D Converter Table 18.1 Pin Configuration.................................................................................................. 851 Table 18.2 Analog Input Channels and Corresponding ADDR Registers .............................. 852 Table 18.3 A/D Conversion Characteristics (Single Mode) ................................................... 860 Table 18.4 A/D Conversion Characteristics (Scan Mode)...................................................... 860 Table 18.5 A/D Converter Interrupt Source............................................................................ 861 Table 18.6 Analog Pin Specifications..................................................................................... 865 Section 19 D/A Converter Table 19.1 Pin Configuration.................................................................................................. 868 Table 19.2 Control of D/A Conversion................................................................................... 870 Section 21 Flash Memory (0.18-m F-ZTAT Version) Table 21.1 Differences between Boot Mode, User Program Mode, and Programmer Mode ......................................................................................... 878 Table 21.2 Pin Configuration.................................................................................................. 883 Table 21.3 Registers/Parameters and Target Modes............................................................... 885 Table 21.4 Parameters and Target Modes............................................................................... 891 Table 21.5 On-Board Programming Mode Setting ................................................................. 903 Table 21.6 System Clock Frequency for Automatic-Bit-Rate Adjustment............................. 904 Table 21.7 Enumeration Information...................................................................................... 908 Table 21.8 Executable Memory MAT .................................................................................... 922 Table 21.9 Usable Area for Programming in User Program Mode......................................... 922 Table 21.10 Usable Area for Erasure in User Program Mode .............................................. 923 Table 21.11 Hardware Protection ......................................................................................... 924 Table 21.12 Software Protection........................................................................................... 925 Table 21.13 Device Types Supported in Programmer Mode................................................ 930 Table 21.14 Inquiry and Selection Commands ..................................................................... 934 Table 21.15 Programming/Erasing Commands .................................................................... 946 Table 21.16 Status Code ....................................................................................................... 953 Table 21.17 Error Code ........................................................................................................ 954 Section 22 Clock Pulse Generator Table 22.1 Selection of Clock Pulse Generator ...................................................................... 958 Table 22.2 Damping Resistance Value ................................................................................... 963 Table 22.3 Crystal Resonator Characteristics ......................................................................... 964 Section 23 Power-Down Modes Table 23.1 Operating States.................................................................................................... 972 Rev.1.00 Jun. 07, 2006 Page l of lii Table 23.2 Table 23.3 Table 23.4 Oscillation Settling Time Settings ........................................................................ 984 Pin (PA7) State in Each Processing State .......................................................... 992 Pin (PB7) State in Each Processing State (SDRAM Interface Enabled)............ 992 Section 25 Electrical Characteristics Table 25.1 Absolute Maximum Ratings ............................................................................... 1039 Table 25.2 DC Characteristics (1)......................................................................................... 1040 Table 25.2 DC Characteristics (2)......................................................................................... 1041 Table 25.3 Permissible Output Currents ............................................................................... 1042 Table 25.4 Clock Timing ...................................................................................................... 1043 Table 25.5 Control Signal Timing ........................................................................................ 1046 Table 25.6 Bus Timing (1).................................................................................................... 1047 Table 25.6 Bus Timing (2).................................................................................................... 1049 Table 25.6 Bus Timing (3).................................................................................................... 1050 Table 25.6 Bus Timing (4).................................................................................................... 1051 Table 25.7 DMAC Timing.................................................................................................... 1074 Table 25.8 Timing of On-Chip Peripheral Modules ............................................................. 1077 Table 25.9 USB Characteristics when On-Chip USB Transceiver is Used (USD+, USD- pin characteristics)...................................................................... 1082 Table 25.10 A/D Conversion Characteristics...................................................................... 1084 Table 25.11 D/A Conversion Characteristics...................................................................... 1084 Table 25.12 Flash Memory Characteristics ........................................................................ 1085 Table 25.13 Flash Memory Characteristics ........................................................................ 1086 Appendix Table A.1 Table D.1 Port States in Each Pin State ............................................................................... 1087 Treatment of Unused Pins................................................................................... 1093 Rev.1.00 Jun. 07, 2006 Page li of lii Rev.1.00 Jun. 07, 2006 Page lii of lii Section 1 Overview Section 1 Overview 1.1 Features * 32-bit high-speed H8SX CPU Upward compatible with the H8/300 CPU, H8/300H CPU, and H8S CPU Object programs for those CPUs are executable Sixteen 16-bit general registers 87 basic instructions * Extensive peripheral functions DMA controller (DMAC) Data transfer controller (DTC) 16-bit timer pulse unit (TPU) Programmable pulse generator (PPG) 8-bit timer (TMR) Watchdog timer (WDT) Serial communication interface (SCI) can be used in asynchronous or clocked synchronous mode Universal Serial Bus Interface (USB) I C bus interface 2 (IIC2) 10-bit A/D converter 8-bit D/A converter Clock pulse generator * On-chip memory Product Classification Flash memory version H8SX/1663 H8SX/1664 Product Model R5F61663 R5F61664 ROM 384 kbytes 512 kbytes RAM 40 kbytes 40 kbytes 2 * General I/O port 92 input/output ports Nine input ports * Supports power-down modes * Small package Rev.1.00 Jun. 07, 2006 Page 1 of 1102 REJ09B0294-0100 Section 1 Overview Package LQFP-144 Note: * Pb-free version Code FP-144LV* Body Size 20.0 x 20.0 mm Pin Pitch 0.50 mm 1.2 Block Diagram TM32K Interrupt controller RAM TMR (unit 0) x 2 channels TMR (unit 1) x 2 channels TMR (unit 2) x 2 channels ROM BSC Peripheral bus Port 1 Port 2 Port 3 Port 5 Port 6 Port A Port B Port C Port D Port E Port F Port H Port I Port M TMR (unit 3) x 2 channels TPU x 6 channels PPG SCI x 6 channels H8SX CPU Internal bus DTC DMAC x 4 channels USB IIC2 x 2 channels A/D converter Main clock oscillator D/A converter Subclock oscillator External bus [Legend] CPU: Central processing unit DTC: Data transfer controller BSC: Bus controller DMAC: DMA controller WDT: Watchdog timer TMR: 8-bit timer TPU: PPG: SCI: USB: IIC2: TM32K: 16-bit timer pulse unit Programmable pulse generator Serial communication interface Universal Serial Bus Interface I2C Bus Interface 2 32K timer Figure 1.1 Block Diagram Rev.1.00 Jun. 07, 2006 Page 2 of 1102 REJ09B0294-0100 Section 1 Overview 1.3 1.3.1 Pin Assignments Pin Assignments P15/TEND1-A/IRQ5-A/TCLKB-B/RxD5/IrRxD/SCL1 P14/DREQ1-A/IRQ4-A/TCLKA-B/TxD5/IrTxD/SDA1 P35/PO13/TIOCA1/TIOCB1/TCLKC-A/DACK1-B P16/DACK1-A/IRQ6-A/TCLKC-B/SDA0 P37/PO15/TIOCA2/TIOCB2/TCLKD-A P60/TMRI2/TxD4/DREQ2/IRQ8-B P61/TMCI2/RxD4/TEND2/IRQ9-B P12/SCK2/DACK0-A/IRQ2-A P17/IRQ7-A/TCLKD-B/SCL0 P36/PO14/TIOCA2 WDTOVF/TDO P13/ADTRG0/IRQ3-A P10/TxD2/DREQ0-A/IRQ0-A P11/RxD2/TEND0-A/IRQ1-A PI7/D15 PI6/D14 PI5/D13 PI4/D12 PI3/D11 PI2/D10 EXTAL OSC1 STBY XTAL OSC2 VCC RES VSS VSS P62/TMO2/SCK4/DACK2/IRQ10-B/TRST PLLVCC P63/TMRI3/DREQ3/IRQ11-B/TMS PLLVSS P64/TMCI3/TEND3/TDI P65/TMO3/DACK3/TCK MD0 PC2/LUCAS/DQMLU PC3/LLCAS/DQMLL P50/AN0/IRQ0-B P51/AN1/IRQ1-B P52/AN2/IRQ2-B AVCC P53/AN3/IRQ3-B AVSS P54/AN4/IRQ4-B Vref P55/AN5/IRQ5-B P56/AN6/DA0/IRQ6-B P57/AN7/DA1/IRQ7-B MD1 PB4/CS4-B/WE PB5/OE/CKE PB6/CS6-D/(RD/WR-B) MD3 PA0/BREQO/BS-A PA1/BACK/(RD/WR-A) PA2/BREQ/WAIT PA3/LLWR/LLB PA4/LHWR/LUB PA5/RD PA6/AS/AH/BS-B VSS PA7/B VCC PB0/CS0/CS4-A/CS5-B 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 109 72 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 1 2 3 4 5 6 7 8 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 VSS VCL PH7/D7 PH6/D6 PH5/D5 PH4/D4 VSS PH3/D3 PH2/D2 PH1/D1 PH0/D0 VCC P34/PO12/TIOCA1/TEND1-B P33/PO11/TIOCC0/TIOCD0/TCLKB-A/DREQ1-B NMI P27/PO7/TIOCA5/TIOCB5 P26/PO6/TIOCA5/TMO1/TxD1 P32/PO10/TIOCC0/TCLKA-A/DACK0-B P31/PO9/TIOCA0/TIOCB0/TEND0-B P30/PO8/TIOCA0/DREQ0-B P25/PO5/TIOCA4/TMCI1/RxD1 P24/PO4/TIOCA4/TIOCB4/TMRI1/SCK1 P23/PO3/TIOCC3/TIOCD3/IRQ11-A P22/PO2/TIOCC3/TMO0/TxD0/IRQ10-A P21/PO1/TIOCA3/TMCI0/RxD0/IRQ9-A VCC P20/PO0/TIOCA3/TIOCB3/TMRI0/SCK0/IRQ8-A VSS MD_CLK VBUS DrVSS USDUSD+ DrVCC PM4 PM3 EMLE* PD0/A0 PD1/A1 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 PI1/D9 PD5/A5 PI0/D8 PD4/A4 FP-144L (top view) 37 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 PB3/CS3-A/CS7-A/CAS VSS VCC VSS VSS PB7/SDRAM VCC MD2 PM2 PB2/CS2-A/CS6-A/RAS PM0/TxD6 PM1/RxD6 PF7/A23 PF6/A22 PF5/A21 PF4/A20 PF3/A19 PF2/A18 PF1/A17 PF0/A16 PE7/A15 PE6/A14 PE5/A13 PE4/A12 PE3/A11 PB1/CS1/CS2-B/CS5-A/CS6-B/CS7-B PE2/A10 PE1/A9 PE0/A8 PD7/A7 PD6/A6 VSS PD3/A3 VCC VSS Note: * This is an on-chip emulator enable pin. Drive this pin low for the connection in normal operating mode. When this pin is driven high, the on-chip emulation function is enabled and pins P62, P63, P64, P65, and WDTOVF are dedicated to the on-chip emulator. For details on a connection example with the E10A, refer to the E10A Emulator User's Manual. Figure 1.2 Pin Assignments Rev.1.00 Jun. 07, 2006 Page 3 of 1102 REJ09B0294-0100 PD2/A2 Section 1 Overview 1.3.2 Table 1.1 Pin Configuration in Each Operating Mode Pin Configuration in Each Operating Mode Operating Mode Pin No. Modes 2, 6, 7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 PB1/CS1/CS2-B/CS5-A/CS6-B/CS7-B PB2/CS2-A/CS6-A/RAS PB3/CS3-A/CS7-A/CAS VSS PB7/SDRAM VCC MD2 PM0/TxD6 PM1/RxD6 PM2 PF7/A23 PF6/A22 PF5/A21 PF4/A20 PF3/A19 VSS PF2/A18 PF1/A17 PF0/A16 PE7/A15 PE6/A14 PE5/A13 VSS PE4/A12 VCC PE3/A11 PE2/A10 PE1/A9 PE0/A8 Modes 4, 5 PB1/CS1/CS2-B/CS5-A/CS6-B/CS7-B PB2/CS2-A/CS6-A/RAS PB3/CS3-A/CS7-A/CAS VSS PB7/SDRAM VCC MD2 PM0/TxD6 PM1/RxD6 PM2 PF7/A23 PF6/A22 PF5/A21 PF4/A20 PF3/A19 VSS PF2/A18 PF1/A17 PF0/A16 PE7/A15 PE6/A14 PE5/A13 VSS PE4/A12 VCC PE3/A11 PE2/A10 PE1/A9 PE0/A8 Rev.1.00 Jun. 07, 2006 Page 4 of 1102 REJ09B0294-0100 Section 1 Overview Operating Mode Pin No. Modes 2, 6, 7 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 PD7/A7 PD6/A6 VSS PD5/A5 PD4/A4 PD3/A3 PD2/A2 PD1/A1 PD0/A0 EMLE PM3 PM4 DrVCC USD+ USDDrVSS VBUS MD_CLK VSS P20/PO0/TIOCA3/TIOCB3/TMRI0/SCK0/IRQ8-A VCC P21/PO1/TIOCA3/TMCI0/RxD0/IRQ9-A P22/PO2/TIOCC3/TMO0/TxD0/IRQ10-A P23/PO3/TIOCC3/TIOCD3/IRQ11-A P24/PO4/TIOCA4/TIOCB4/TMRI1/SCK1 P25/PO5/TIOCA4/TMCI1/RxD1 P30/PO8/TIOCA0/DREQ0-B P31/PO9/TIOCA0/TIOCB0/TEND0-B P32/PO10/TIOCC0/TCLKA-A/DACK0-B P26/PO6/TIOCA5/TMO1/TxD1 P27/PO7/TIOCA5/TIOCB5 Modes 4, 5 PD7/A7 PD6/A6 VSS PD5/A5 PD4/A4 PD3/A3 PD2/A2 PD1/A1 PD0/A0 EMLE PM3 PM4 DrVCC USD+ USDDrVSS VBUS MD_CLK VSS P20/PO0/TIOCA3/TIOCB3/TMRI0/SCK0/IRQ8-A VCC P21/PO1/TIOCA3/TMCI0/RxD0/IRQ9-A P22/PO2/TIOCC3/TMO0/TxD0/IRQ10-A P23/PO3/TIOCC3/TIOCD3/IRQ11-A P24/PO4/TIOCA4/TIOCB4/TMRI1/SCK1 P25/PO5/TIOCA4/TMCI1/RxD1 P30/PO8/TIOCA0/DREQ0-B P31/PO9/TIOCA0/TIOCB0/TEND0-B P32/PO10/TIOCC0/TCLKA-A/DACK0-B P26/PO6/TIOCA5/TMO1/TxD1 P27/PO7/TIOCA5/TIOCB5 Rev.1.00 Jun. 07, 2006 Page 5 of 1102 REJ09B0294-0100 Section 1 Overview Operating Mode Pin No. Modes 2, 6, 7 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 NMI Modes 4, 5 NMI P33/PO11/TIOCC0/TIOCD0/TCLKB-A/DREQ1-B P33/PO11/TIOCC0/TIOCD0/TCLKB-A/DREQ1-B P34/PO12/TIOCA1/TEND1-B VCC PH0/D0 PH1/D1 PH2/D2 PH3/D3 VSS PH4/D4 PH5/D5 PH6/D6 PH7/D7 VCC PI0/D8 PI1/D9 PI2/D10 PI3/D11 VSS PI4/D12 PI5/D13 PI6/D14 PI7/D15 P10/TxD2/DREQ0-A/IRQ0-A P11/RxD2/TEND0-A/IRQ1-A P12/SCK2/DACK0-A/IRQ2-A P13/ADTRG0/IRQ3-A VSS OSC2 OSC1 RES P34/PO12/TIOCA1/TEND1-B VCC PH0/D0 PH1/D1 PH2/D2 PH3/D3 VSS PH4/D4 PH5/D5 PH6/D6 PH7/D7 VCC PI0/D8 PI1/D9 PI2/D10 PI3/D11 VSS PI4/D12 PI5/D13 PI6/D14 PI7/D15 P10/TxD2/DREQ0-A/IRQ0-A P11/RxD2/TEND0-A/IRQ1-A P12/SCK2/DACK0-A/IRQ2-A P13/ADTRG0/IRQ3-A VSS OSC2 OSC1 RES Rev.1.00 Jun. 07, 2006 Page 6 of 1102 REJ09B0294-0100 Section 1 Overview Operating Mode Pin No. Modes 2, 6, 7 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 VCL P14/DREQ1-A/IRQ4-A/TCLKA-B/TxD5/IrTxD/ SDA1 P15/TEND1-A/IRQ5-A/TCLKB-B/RxD5/IrRxD/ SCL1 WDTOVF/TDO VSS XTAL EXTAL VCC P16/DACK1-A/IRQ6-A/TCLKC-B/SDA0 P17/IRQ7-A/TCLKD-B/SCL0 STBY VSS P35/PO13/TIOCA1/TIOCB1/TCLKC-A/DACK1-B P36/PO14/TIOCA2 P37/PO15/TIOCA2/TIOCB2/TCLKD-A P60/TMRI2/TxD4/DREQ2/IRQ8-B P61/TMCI2/RxD4/TEND2/IRQ9-B P62/TMO2/SCK4/DACK2/IRQ10-B/TRST PLLVCC P63/TMRI3/DREQ3/IRQ11-B/TMS PLLVSS P64/TMCI3/TEND3/TDI P65/TMO3/DACK3/TCK MD0 PC2/LUCAS/DQMLU PC3/LLCAS/DQMLL P50/AN0/IRQ0-B P51/AN1/IRQ1-B P52/AN2/IRQ2-B Modes 4, 5 VCL P14/DREQ1-A/IRQ4-A/TCLKA-B/TxD5/IrTxD/ SDA1 P15/TEND1-A/IRQ5-A/TCLKB-B/RxD5/IrRxD/ SCL1 WDTOVF/TDO VSS XTAL EXTAL VCC P16/DACK1-A/IRQ6-A/TCLKC-B/SDA0 P17/IRQ7-A/TCLKD-B/SCL0 STBY VSS P35/PO13/TIOCA1/TIOCB1/TCLKC-A/DACK1-B P36/PO14/TIOCA2 P37/PO15/TIOCA2/TIOCB2/TCLKD-A P60/TMRI2/TxD4/DREQ2/IRQ8-B P61/TMCI2/RxD4/TEND2/IRQ9-B P62/TMO2/SCK4/DACK2/IRQ10-B/TRST PLLVCC P63/TMRI3/DREQ3/IRQ11-B/TMS PLLVSS P64/TMCI3/TEND3/TDI P65/TMO3/DACK3/TCK MD0 PC2/LUCAS/DQMLU PC3/LLCAS/DQMLL P50/AN0/IRQ0-B P51/AN1/IRQ1-B P52/AN2/IRQ2-B Rev.1.00 Jun. 07, 2006 Page 7 of 1102 REJ09B0294-0100 Section 1 Overview Operating Mode Pin No. Modes 2, 6, 7 Modes 4, 5 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 AVCC P53/AN3/IRQ3-B AVSS P54/AN4/IRQ4-B Vref P55/AN5/IRQ5-B P56/AN6/DA0/IRQ6-B P57/AN7/DA1/IRQ7-B MD1 PB4/CS4-B/WE PB5/OE/CKE PB6/CS6-D/(RD/WR-B) MD3 PA0/BREQO/BS-A PA1/BACK/(RD/WR-A) PA2/BREQ/WAIT PA3/LLWR/LLB PA4/LHWR/LUB PA5/RD PA6/AS/AH/BS-B VSS PA7/B VCC PB0/CS0/CS4-A/CS5-B AVCC P53/AN3/IRQ3-B AVSS P54/AN4/IRQ4-B Vref P55/AN5/IRQ5-B P56/AN6/DA0/IRQ6-B P57/AN7/DA1/IRQ7-B MD1 PB4/CS4-B/WE PB5/OE/CKE PB6/CS6-D/(RD/WR-B) MD3 PA0/BREQO/BS-A PA1/BACK/(RD/WR-A) PA2/BREQ/WAIT PA3/LLWR/LLB PA4/LHWR/LUB PA5/RD PA6/AS/AH/BS-B VSS PA7/B VCC PB0/CS0/CS4-A/CS5-B Rev.1.00 Jun. 07, 2006 Page 8 of 1102 REJ09B0294-0100 Section 1 Overview 1.3.3 Table 1.2 Pin Functions Pin Functions Abbreviation VCC Pin No. (FP-144LV) 6, 25, 50, 64, 74, 99, 143 92 I/O Input Description Power supply pins. Connect to the system power supply. Connect this pin to VSS via a 0.1-F capacitor. (The capacitor should be placed close to the pin.) Ground pins. Connect to the system power supply (0 V). Classification Power supply VCL Input VSS 4, 16, 23, 32, 48, 69, 79, 88, 96, 103, 141 110 112 42 45 97 98 Input PLLVCC PLLVSS DrVCC DrVSS Clock XTAL EXTAL Input Input Input Input Input Input Power supply pin for the PLL circuits. Connect to the system power supply. Ground pin for the PLL circuits. Power supply pin for USB on-chip transceiver. Connect to the system power supply. Ground pin for USB on-chip transceiver Pins for a crystal resonator. External clock can be input to the EXTAL pin. For a connection example, see section 22, Clock Pulse Generator. Connects the 32.768-kHz crystal resonator. Connect the 32.768-kHz crystal resonator. OSC1 OSC2 B SDRAM 90 89 142 5 Input Input Output Outputs the system clock for external devices. Output Connects to the CLK pin of synchronous DRAM when synchronous DRAM is connected. For details, see section 6, Bus Controller (BSC). Input Pins for setting the operating mode. The signal levels of these pins must not be changed during operation. Pin for changing the multiplication ratio of the clock pulse generator. The signal levels of this pin must not be changed during operation. Operating mode MD3 control MD2 MD1 MD0 MD_CLK 133 7 129 115 47 Input Rev.1.00 Jun. 07, 2006 Page 9 of 1102 REJ09B0294-0100 Section 1 Overview Pin No. (FP-144LV) 91 102 39 Classification System control Abbreviation RES STBY EMLE I/O Input Input Input Description Reset signal input pin. This LSI enters the reset state when this signal goes low. This LSI enters hardware standby mode when this signal goes low. Input pin for on-chip emulator enable signal. If the on-chip emulator is used, the signal level should be fixed high. If the on-chip emulator is not used, the signal level should be fixed low. On-chip emulator pins. When the EMLE pin is driven high, these pins are dedicated for the on-chip emulator. On-chip emulator TRST TMS TDI TCK TDO 109 111 113 114 95 11 12 13 14 15 17 18 19 20 21 22 24 26 27 28 29 30 31 33 34 35 36 37 38 Input Input Input Input Output Address bus A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Output Output pins for the addresses. Rev.1.00 Jun. 07, 2006 Page 10 of 1102 REJ09B0294-0100 Section 1 Overview Pin No. (FP-144LV) 83 82 81 80 78 77 76 75 73 72 71 70 68 67 66 65 136 134 Classification Data bus Abbreviation D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BREQ BREQO I/O Description Input/ Bidirectional data bus. These pins also output output addresses when accessing the address/data multiplexed I/O interface space. Bus control Input External bus masters request the bus by this signal. Output The internal bus masters request the bus to access the external space in the external bus released state. Output Bus acknowledge signal which indicates that the bus has been released. Output Indicates the start of a bus cycle. Output Strobe signal which indicates that the output address on the address bus is valid when accessing the basic bus interface or byte control SRAM interface space. Output This signal is used to hold the address when accessing the address/data multiplexed I/O interface space. Output Strobe signal to indicates that the basic bus interface space is being read from. Output Indicates the direction (input/output) of the data bus. Output Strobe signal which indicates that the upper byte (D15 to D8) is valid when accessing the basic bus interface space. Output Strobe signal which indicates that the lower byte (D7 to D0) is valid when accessing the basic bus interface space. BACK BS-A/BS-B AS 135 134/140 140 AH 140 RD RD/WR-A/RD/WR-B LHWR 139 135/132 138 LLWR 137 Rev.1.00 Jun. 07, 2006 Page 11 of 1102 REJ09B0294-0100 Section 1 Overview Pin No. (FP-144LV) 138 Classification Bus control Abbreviation LUB I/O Description Output Strobe signal which indicates that the upper byte (D15 to D8) is valid when accessing the byte control SRAM interface space. Output Strobe signal which indicates that the lower byte (D7 to D0) is valid when accessing the byte control SRAM interface space. Output Select signals for areas 7 to 0. LLB 137 CS0 CS1 CS2-A/CS2-B CS3-A CS4-A/CS4-B CS5-A/CS5-B CS6-A/CS6-B/CS6-D CS7-A/CS7-B WAIT RAS 144 1 2/1 3 144/130 1/144 2/1/132 3/1 136 2 Input Requests wait cycles when accessing the external space. Row address strobe signal for DRAM when area 2 is specified as DRAM interface space. * Row address strobe signal when area 2 is specified as synchronous DRAM interface space. Output * CAS 3 Output Column address strobe signal when area 2 is specified as synchronous DRAM interface space. Output * * Write enable signal for DRAM space. Write enable signal when area 2 is specified as synchronous DRAM interface space. WE 130 OE/CKE 131 Output * * Output enable signal for DRAM interface space. Clock enable signal for synchronous DRAM interface space. Rev.1.00 Jun. 07, 2006 Page 12 of 1102 REJ09B0294-0100 Section 1 Overview Pin No. (FP-144LV) I/O 116 Classification Bus control Abbreviation LUCAS/DQMLU Description Upper-column address strobe signal for 16-bit DRAM interface space. Output * * LLCAS/DQMLL 117 Output * * * * Interrupt NMI 61 Input Upper-data mask enable signal for 16-bit synchronous DRAM interface space. Lower-column address strobe signal for 16-bit DRAM interface space Column address strobe signal for 8-bit DRAM interface space. Lower-data mask enable signal for 16-bit synchronous DRAM interface space. Data mask enable signal for 8-bit synchronous DRAM interface space Non-maskable interrupt request signal. When this pin is not in use, this signal must be fixed high. Maskable interrupt request signal. IRQ11-A/IRQ11-B IRQ10-A/IRQ10-B IRQ9-A/IRQ9-B IRQ8-A/IRQ8-B IRQ7-A/IRQ7-B IRQ6-A/IRQ6-B IRQ5-A/IRQ5-B IRQ4-A/IRQ4-B IRQ3-A/IRQ3-B IRQ2-A/IRQ2-B IRQ1-A/IRQ1-B IRQ0-A/IRQ0-B DMA controller (DMAC) DREQ0-A/DREQ0-B DREQ1-A/DREQ1-B DREQ2 DREQ3 DACK0-A/DACK0-B DACK1-A/DACK1-B DACK2 DACK3 TEND0-A/TEND0-B TEND1-A/TEND1-B TEND2 TEND3 53/111 52/109 51/108 49/107 101/128 100/127 94/126 93/124 87/122 86/120 85/119 84/118 84/56 93/62 107 111 86/58 100/104 109 114 85/57 94/63 108 113 Input Input Requests DMAC activation. Output DMAC single address transfer acknowledge signal. Output Indicates DMAC data transfer end. Rev.1.00 Jun. 07, 2006 Page 13 of 1102 REJ09B0294-0100 Section 1 Overview Pin No. (FP-144LV) 58/93 62/94 104/100 106/101 56, 57 57 58, 62 62 63, 104 104 105, 106 106 49, 51 49 52, 53 53 54, 55 54 59, 60 60 106 105 104 63 62 58 57 56 60 59 55 54 53 52 51 49 Classification 16-bit timer pulse unit (TPU) Abbreviation TCLKA-A/TCLKA-B TCLKB-A/TCLKB-B TCLKC-A/TCLKC-B TCLKD-A/TCLKD-B TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 TIOCB4 TIOCA5 TIOCB5 I/O Description Input/ Input pins for the external clocks. output Input/ Signals for TGRA0 to TGRD0. These are used output for the input capture inputs/output compare outputs/PWM outputs. Input/ Signals for TGRA_1 and TGRB_1. These are output used for the input capture inputs/output compare outputs/PWM outputs. Input/ Signals for TGRA_2 and TGRB_2. These are output used for the input capture inputs/output compare outputs/PWM outputs. Input/ Signals for TGRA_3 and TGRB_3. These are output used for the input capture inputs/output compare outputs/PWM outputs. Input/ Signals for TGRA_4 and TGRB_4. These are output used for the input capture inputs/output compare outputs/PWM outputs. Input/ Signals for TGRA_5 and TGRB_5. These are output used for the input capture inputs/output compare outputs/PWM outputs. Output Output pins for the pulse signals. Programmable pulse generator (PPG) PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 PO7 PO6 PO5 PO4 PO3 PO2 PO1 PO0 Rev.1.00 Jun. 07, 2006 Page 14 of 1102 REJ09B0294-0100 Section 1 Overview Pin No. (FP-144LV) 52 59 109 114 51 55 108 113 49 54 107 111 95 52 59 84 107 93 8 51 55 85 108 94 9 49 54 86 109 93 94 Classification 8-bit timer (TMR) Abbreviation TMO0 TMO1 TMO2 TMO3 TMCI0 TMCI1 TMCI2 TMCI3 TMRI0 TMRI1 TMRI2 TMRI3 I/O Description Output Output pins for the compare match signals. Input Input pins for the external clock signals used for the counters. Input Input pins for the counter reset signals. Watchdog timer WDTOVF (WDT) Serial communication interface (SCI) TxD0 TxD1 TxD2 TxD4 TxD5 TxD6 RxD0 RxD1 RxD2 RxD4 RxD5 RxD6 SCK0 SCK1 SCK2 SCK4 SCI with IrDA (SCI) IrTxD IrRxD Output Output pin for the counter overflow signal in watchdog timer mode. Output Output pins for transmit data. Input Input pins for receive data. Input/ Input/output pins for clock signals. output Output Output pin that outputs decoded data for IrDA Input Input pin that inputs decoded data for IrDA Rev.1.00 Jun. 07, 2006 Page 15 of 1102 REJ09B0294-0100 Section 1 Overview Pin No. (FP-144LV) 101, 94 100, 93 43 44 46 128 127 126 124 122 120 119 118 87 128 127 121 Classification 2 Abbreviation I/O Description I C bus interface SCL0, SCL1 2 (IIC2) SDA0, SDA1 Universal Serial USD+ Bus Interface USD- (USB) VBUS A/D converter AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 ADTRG0 D/A converter A/D converter, D/A converter DA1 DA0 AVCC Input/ Input/output pin for IIC clock. Bus can be output directly driven by the NMOS open drain output. Input/ Input/output pin for IIC data. Bus can be output directly driven by the NMOS open drain output. Input/ Input/output pin for USB data output Input Input Pin for monitoring USB cable connection Input pins for the analog signals for the A/D converter. Input Input pin for the external trigger signal to start A/D conversion. Output Output pins for the analog signals for the D/A converter. Input Analog power supply pin for the A/D and D/A converters. When the A/D and D/A converters are not in use, connect to the system power supply. Ground pin for the A/D and D/A converters. Connect to the system power supply (0 V). Reference power supply pin for the A/D and D/A converters. When the A/D and D/A converters are not in use, connect to the system power supply. AVSS Vref 123 125 Input Input Rev.1.00 Jun. 07, 2006 Page 16 of 1102 REJ09B0294-0100 Section 1 Overview Pin No. (FP-144LV) 101 100 94 93 87 86 85 84 60 59 55 54 53 52 51 49 106 105 104 63 62 58 57 56 128 127 126 124 122 120 119 118 114 113 111 109 108 107 Classification I/O port Abbreviation P17 P16 P15 P14 P13 P12 P11 P10 P27 P26 P25 P24 P23 P22 P21 P20 P37 P36 P35 P34 P33 P32 P31 P30 P57 P56 P55 P54 P53 P52 P51 P50 P65 P64 P63 P62 P61 P60 I/O Description Input/ 8-bit input/output pins. output Input/ 8-bit input/output pins. output Input/ 8-bit input/output pins. output Input 8-bit input pins. Input/ 6-bit input/output pins. output Rev.1.00 Jun. 07, 2006 Page 17 of 1102 REJ09B0294-0100 Section 1 Overview Pin No. (FP-144LV) 142 140 139 138 137 136 135 134 5 132 131 130 3 2 1 144 117 116 30 31 33 34 35 36 37 38 20 21 22 24 26 27 28 29 Classification I/O port Abbreviation PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC3 PC2 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 I/O Input Description Input-only pin Input/ 7-bit input/output pins. output Input/ 8-bit input/output pins. output Input/ 2-bit input/output pins. output Input/ 8-bit input/output pins. output Input/ 8-bit input/output pins. output Rev.1.00 Jun. 07, 2006 Page 18 of 1102 REJ09B0294-0100 Section 1 Overview Pin No. (FP-144LV) 11 12 13 14 15 17 18 19 73 72 71 70 68 67 66 65 83 82 81 80 78 77 76 75 41 40 10 9 8 Classification I/O port Abbreviation PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 PI7 PI6 PI5 PI4 PI3 PI2 PI1 PI0 PM4 PM3 PM2 PM1 PM0 I/O Description Input/ 8-bit input/output pins. output Input/ 8-bit input/output pins. output Input/ 8-bit input/output pins. output Input/ 5-bit input/output pins. output Rev.1.00 Jun. 07, 2006 Page 19 of 1102 REJ09B0294-0100 Section 1 Overview Rev.1.00 Jun. 07, 2006 Page 20 of 1102 REJ09B0294-0100 Section 2 CPU Section 2 CPU The H8SX CPU is a high-speed CPU with an internal 32-bit architecture that is upward compatible with the H8/300, H8/300H, and H8S CPUs. The H8SX CPU has sixteen 16-bit general registers, can handle a 4-Gbyte linear address space, and is ideal for a realtime control system. 2.1 Features * Upward-compatible with H8/300, H8/300H, and H8S CPUs Can execute H8/300, H8/300H, and H8S/2000 object programs * Sixteen 16-bit general registers Also usable as sixteen 8-bit registers or eight 32-bit registers * 87 basic instructions 8/16/32-bit arithmetic and logic instructions Multiply and divide instructions Bit field transfer instructions Powerful bit-manipulation instructions Bit condition branch instructions Multiply-and-accumulate instruction * Eleven addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:2,ERn), @(d:16,ERn), or @(d:32,ERn)] Index register indirect with displacement [@(d:16,RnL.B), @(d:32,RnL.B), @(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L)] Register indirect with pre-/post-increment or pre-/post-decrement [@+ERn, @-ERn, @ERn+, or @ERn-] Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] Immediate [#xx:3, #xx:4, #xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8,PC) or @(d:16,PC)] Program-counter relative with index register [@(RnL.B,PC), @(Rn.W,PC), or @(ERn.L,PC)] Memory indirect [@@aa:8] Extended memory indirect [@@vec:7] Rev.1.00 Jun. 07, 2006 Page 21 of 1102 REJ09B0294-0100 Section 2 CPU * Two base registers Vector base register Short address base register * 4-Gbyte address space Program: 4 Gbytes Data: 4 Gbytes * High-speed operation All frequently-used instructions executed in one or two states 8/16/32-bit register-register add/subtract: 1 state 8 x 8-bit register-register multiply: 16 / 8-bit register-register divide: 16 x 16-bit register-register multiply: 32 / 16-bit register-register divide: 32 x 32-bit register-register multiply: 32 / 32-bit register-register divide: * Four CPU operating modes Normal mode Middle mode Advanced mode Maximum mode * Power-down modes Transition is made by execution of SLEEP instruction Choice of CPU operating clocks 1 state 10 states 1 state 18 states 5 states 18 states Rev.1.00 Jun. 07, 2006 Page 22 of 1102 REJ09B0294-0100 Section 2 CPU 2.2 CPU Operating Modes The H8SX CPU has four operating modes: normal, middle, advanced and maximum modes. For details on mode settings, see section 3.1, Operating Mode Selection. Maximum 64 kbytes for program Normal mode and data areas combined Maximum 16-Mbyte program Middle mode CPU operating modes Advanced mode area and 64-kbyte data area, maximum 16 Mbytes for program and data areas combined Maximum 16-Mbyte program area and 4-Gbyte data area, maximum 4 Gbytes for program and data areas combined Maximum mode Maximum 4 Gbytes for program and data areas combined Figure 2.1 CPU Operating Modes 2.2.1 Normal Mode The exception vector table and stack have the same structure as in the H8/300 CPU. Note: Normal mode is not supported in this LSI. * Address Space The maximum address space of 64 kbytes can be accessed. * Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When the extended register En is used as a 16-bit register it can contain any value, even when the corresponding general register Rn is used as an address register. (If the general register Rn is referenced in the register indirect addressing mode with pre-/post-increment or pre-/post-decrement and a carry or borrow occurs, however, the value in the corresponding extended register En will be affected.) * Instruction Set All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid. Rev.1.00 Jun. 07, 2006 Page 23 of 1102 REJ09B0294-0100 Section 2 CPU * Exception Vector Table and Memory Indirect Branch Addresses In normal mode, the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The structure of the exception vector table is shown in figure 2.2. H'0000 H'0001 H'0002 H'0003 Reset exception vector Reset exception vector Exception vector table Figure 2.2 Exception Vector Table (Normal Mode) The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes are used in the JMP and JSR instructions. An 8-bit absolute address included in the instruction code specifies a memory location. Execution branches to the contents of the memory location. * Stack Structure The stack structure of PC at a subroutine branch and that of PC and CCR at an exception handling are shown in figure 2.3. The PC contents are saved or restored in 16-bit units. SP PC (16 bits) SP *2 (SP ) EXR*1 Reserved*1, *3 CCR CCR*3 PC (16 bits) (a) Subroutine Branch (b) Exception Handling Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used. 3. Ignored on return. Figure 2.3 Stack Structure (Normal Mode) Rev.1.00 Jun. 07, 2006 Page 24 of 1102 REJ09B0294-0100 Section 2 CPU 2.2.2 Middle Mode The program area in middle mode is extended to 16 Mbytes as compared with that in normal mode. * Address Space The maximum address space of 16 Mbytes can be accessed as a total of the program and data areas. For individual areas, up to 16 Mbytes of the program area or up to 64 kbytes of the data area can be allocated. * Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When the extended register En is used as a 16-bit register (in other than the JMP and JSR instructions), it can contain any value even when the corresponding general register Rn is used as an address register. (If the general register Rn is referenced in the register indirect addressing mode with pre-/post-increment or pre-/postdecrement and a carry or borrow occurs, however, the value in the corresponding extended register En will be affected.) * Instruction Set All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid and the upper eight bits are sign-extended. * Exception Vector Table and Memory Indirect Branch Addresses In middle mode, the top area starting at H'000000 is allocated to the exception vector table. One branch address is stored per 32 bits. The upper eight bits are ignored and the lower 24 bits are stored. The structure of the exception vector table is shown in figure 2.4. The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes are used in the JMP and JSR instructions. An 8-bit absolute address included in the instruction code specifies a memory location. Execution branches to the contents of the memory location. In middle mode, an operand is a 32-bit (longword) operand, providing a 32-bit branch address. The upper eight bits are reserved and assumed to be H'00. * Stack Structure The stack structure of PC at a subroutine branch and that of PC and CCR at an exception handling are shown in figure 2.5. The PC contents are saved or restored in 24-bit units. Rev.1.00 Jun. 07, 2006 Page 25 of 1102 REJ09B0294-0100 Section 2 CPU 2.2.3 Advanced Mode The data area is extended to 4 Gbytes as compared with that in middle mode. * Address Space The maximum address space of 4 Gbytes can be linearly accessed. For individual areas, up to 16 Mbytes of the program area and up to 4 Gbytes of the data area can be allocated. * Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. * Instruction Set All instructions and addressing modes can be used. * Exception Vector Table and Memory Indirect Branch Addresses In advanced mode, the top area starting at H'00000000 is allocated to the exception vector table. One branch address is stored per 32 bits. The upper eight bits are ignored and the lower 24 bits are stored. The structure of the exception vector table is shown in figure 2.4. H'00000000 H'00000001 H'00000002 H'00000003 H'00000004 H'00000005 H'00000006 H'00000007 Reserved Exception vector table Reset exception vector Reserved Figure 2.4 Exception Vector Table (Middle and Advanced Modes) The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes are used in the JMP and JSR instructions. An 8-bit absolute address included in the instruction code specifies a memory location. Execution branches to the contents of the memory location. In advanced mode, an operand is a 32-bit (longword) operand, providing a 32-bit branch address. The upper eight bits are reserved and assumed to be H'00. Rev.1.00 Jun. 07, 2006 Page 26 of 1102 REJ09B0294-0100 Section 2 CPU * Stack Structure The stack structure of PC at a subroutine branch and that of PC and CCR at an exception handling are shown in figure 2.5. The PC contents are saved or restored in 24-bit units. SP SP Reserved PC (24 bits) (SP *2 ) EXR*1 Reserved*1, *3 CCR PC (24 bits) (a) Subroutine Branch (b) Exception Handling Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used. 3. Ignored on return. Figure 2.5 Stack Structure (Middle and Advanced Modes) 2.2.4 Maximum Mode The program area is extended to 4 Gbytes as compared with that in advanced mode. * Address Space The maximum address space of 4 Gbytes can be linearly accessed. * Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers or as the upper 16-bit segments of 32-bit registers or address registers. * Instruction Set All instructions and addressing modes can be used. * Exception Vector Table and Memory Indirect Branch Addresses In maximum mode, the top area starting at H'00000000 is allocated to the exception vector table. One branch address is stored per 32 bits. The structure of the exception vector table is shown in figure 2.6. Rev.1.00 Jun. 07, 2006 Page 27 of 1102 REJ09B0294-0100 Section 2 CPU H'00000000 H'00000001 H'00000002 H'00000003 H'00000004 H'00000005 H'00000006 H'00000007 Exception vector table Reset exception vector Figure 2.6 Exception Vector Table (Maximum Modes) The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes are used in the JMP and JSR instructions. An 8-bit absolute address included in the instruction code specifies a memory location. Execution branches to the contents of the memory location. In maximum mode, an operand is a 32-bit (longword) operand, providing a 32-bit branch address. * Stack Structure The stack structure of PC at a subroutine branch and that of PC and CCR at an exception handling are shown in figure 2.7. The PC contents are saved or restored in 32-bit units. The EXR contents are saved or restored regardless of whether or not EXR is in use. SP PC (32 bits) SP EXR CCR PC (32 bits) (a) Subroutine Branch (b) Exception Handling Figure 2.7 Stack Structure (Maximum Mode) Rev.1.00 Jun. 07, 2006 Page 28 of 1102 REJ09B0294-0100 Section 2 CPU 2.3 Instruction Fetch The H8SX CPU has two modes for instruction fetch: 16-bit and 32-bit modes. It is recommended that the mode be set according to the bus width of the memory in which a program is stored. The instruction-fetch mode setting does not affect operation other than instruction fetch such as data accesses. Whether an instruction is fetched in 16- or 32-bit mode is selected by the FETCHMD bit in SYSCR. For details, see section 3.2.2, System Control Register (SYSCR). 2.4 Address Space Figure 2.8 shows a memory map of the H8SX CPU. The address space differs depending on the CPU operating mode. Normal mode H'0000 H'000000 H'007FFF Program area Data area (64 kbytes) Middle mode H'00000000 Advanced mode H'00000000 Maximum mode H'FFFF Program area (16 Mbytes) Program area (16 Mbytes) Data area (64 kbytes) H'FF8000 H'FFFFFF H'00FFFFFF Program area Data area (4 Gbytes) Data area (4 Gbytes) H'FFFFFFFF H'FFFFFFFF Figure 2.8 Memory Map Rev.1.00 Jun. 07, 2006 Page 29 of 1102 REJ09B0294-0100 Section 2 CPU 2.5 Registers The H8SX CPU has the internal registers shown in figure 2.9. There are two types of registers: general registers and control registers. The control registers are the 32-bit program counter (PC), 8-bit extended control register (EXR), 8-bit condition-code register (CCR), 32-bit vector base register (VBR), 32-bit short address base register (SBR), and 64-bit multiply-accumulate register (MAC). General Registers and Extended Registers 15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 (SP) Control Registers 31 PC 76543210 CCR I UI H U N Z V C 76543210 EXR 31 VBR 31 SBR 63 MAC 31 U: N: Z: V: C: EXR: User bit Negative flag Zero flag Overflow flag Carry flag Extended control register T: I2 to I0: VBR: SBR: MAC: Sign extension MACL [Legend] SP: PC: CCR: I: UI: H: 0 Trace bit Interrupt mask bits Vector base register Short address base register Multiply-accumulate register 41 MACH 12 (Reserved) 8 (Reserved) 32 0 T -- -- -- -- I2 I1 I0 0 0 E0 E1 E2 E3 E4 E5 E6 E7 07 R0H R1H R2H R3H R4H R5H R6H R7H 07 R0L R1L R2L R3L R4L R5L R6L R7L 0 Stack pointer Program counter Condition-code register Interrupt mask bit User bit or interrupt mask bit Half-carry flag Figure 2.9 CPU Registers Rev.1.00 Jun. 07, 2006 Page 30 of 1102 REJ09B0294-0100 Section 2 CPU 2.5.1 General Registers The H8SX CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.10 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). When the general registers are used as 16-bit registers, the ER registers are divided into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. When the general registers are used as 8-bit registers, the R registers are divided into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers. The general registers ER (ER0 to ER7), R (R0 to R7), and RL (R0L to R7L) are also used as index registers. The size in the operand field determines which register is selected. The usage of each register can be selected independently. * 16-bit registers General registers E (E0 to E7) * 8-bit registers * 16-bit registers * 16-bit index registers General registers R (R0 to R7) General registers RH (R0H to R7H) * 8-bit registers * 8-bit index registers General registers RL (R0L to R7L) * Address registers * 32-bit registers * 32-bit index registers General registers ER (ER0 to ER7) Figure 2.10 Usage of General Registers Rev.1.00 Jun. 07, 2006 Page 31 of 1102 REJ09B0294-0100 Section 2 CPU General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine branches. Figure 2.11 shows the stack. Free area SP (ER7) Stack area Figure 2.11 Stack 2.5.2 Program Counter (PC) PC is a 32-bit counter that indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 16 bits (one word) or a multiple of 16 bits, so the least significant bit is ignored. (When the instruction code is fetched, the least significant bit is regarded as 0. Rev.1.00 Jun. 07, 2006 Page 32 of 1102 REJ09B0294-0100 Section 2 CPU 2.5.3 Condition-Code Register (CCR) CCR is an 8-bit register that contains internal CPU status information, including an interrupt mask (I) and user (UI, U) bits and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branch conditions for conditional branch (Bcc) instructions. Bit 7 Bit Name I Initial Value 1 R/W R/W Description Interrupt Mask Bit Masks interrupts when set to 1. This bit is set to 1 at the start of an exception handling. 6 UI Undefined R/W User Bit Can be written to and read from by software using the LDC, STC, ANDC, ORC, and XORC instructions. 5 H Undefined R/W Half-Carry Flag When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. 4 U Undefined R/W User Bit Can be written to and read from by software using the LDC, STC, ANDC, ORC, and XORC instructions. 3 N Undefined R/W Negative Flag Stores the value of the most significant bit (regarded as sign bit) of data. Rev.1.00 Jun. 07, 2006 Page 33 of 1102 REJ09B0294-0100 Section 2 CPU Bit 2 Bit Name Z Initial Value R/W Description Zero Flag Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. Undefined R/W 1 V Undefined R/W Overflow Flag Set to 1 when an arithmetic overflow occurs, and cleared to 0 otherwise. 0 C Undefined R/W Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise. A carry has the following types: * * * Carry from the result of addition Borrow from the result of subtraction Carry from the result of shift or rotation The carry flag is also used as a bit accumulator by bit manipulation instructions. 2.5.4 Extended Control Register (EXR) EXR is an 8-bit register that contains the trace bit (T) and three interrupt mask bits (I2 to I0). Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC instructions. For details, see section 4, Exception Handling. Bit 7 Bit Name T Initial Value 0 R/W R/W Description Trace Bit When this bit is set to 1, a trace exception is generated each time an instruction is executed. When this bit is cleared to 0, instructions are executed in sequence. 6 to 3 2 1 0 -- I2 I1 I0 All 1 1 1 1 R/W R/W R/W R/W Reserved These bits are always read as 1. Interrupt Mask Bits These bits designate the interrupt mask level (0 to 7). Rev.1.00 Jun. 07, 2006 Page 34 of 1102 REJ09B0294-0100 Section 2 CPU 2.5.5 Vector Base Register (VBR) VBR is a 32-bit register in which the upper 20 bits are valid. The lower 12 bits of this register are read as 0s. This register is a base address of the vector area for exception handlings other than a reset and a CPU address error (extended memory indirect is also out of the target). The initial value is H'00000000. The VBR contents are changed with the LDC and STC instructions. 2.5.6 Short Address Base Register (SBR) SBR is a 32-bit register in which the upper 24 bits are valid. The lower eight bits are read as 0s. In 8-bit absolute address addressing mode (@aa:8), this register is used as the upper address. The initial value is H'FFFFFF00. The SBR contents are changed with the LDC and STC instructions. 2.5.7 Multiply-Accumulate Register (MAC) MAC is a 64-bit register that stores the results of multiply-and-accumulate operations. It consists of two 32-bit registers denoted MACH and MACL. The lower 10 bits of MACH are valid; the upper bits are sign extended. The MAC contents are changed with the MAC, CLRMAC, LDMAC, and STMAC instructions. 2.5.8 Initial Values of CPU Registers Reset exception handling loads the start address from the vector table into the PC, clears the T bit in EXR to 0, and sets the I bits in CCR and EXR to 1. The general registers, MAC, and the other bits in CCR are not initialized. In particular, the initial value of the stack pointer (ER7) is undefined. The SP should therefore be initialized using an MOV.L instruction executed immediately after a reset. Rev.1.00 Jun. 07, 2006 Page 35 of 1102 REJ09B0294-0100 Section 2 CPU 2.6 Data Formats The H8SX CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.6.1 General Register Data Formats Figure 2.12 shows the data formats in general registers. 7 0 76543210 1-bit data 1-bit data 4-bit BCD data 4-bit BCD data Byte data Byte data Word data Word data Longword data 15 MSB 31 MSB RnH RnL RnH RnL Don't care 7 0 76543210 Don't care 7 Upper 43 0 Lower Don't care 7 43 Upper Lower 0 RnH 7 RnL MSB Rn Don't care 0 Don't care LSB 7 Don't care MSB 15 0 LSB 0 LSB En ERn MSB 0 LSB 16 15 En 0 Rn LSB [Legend] ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2.12 General Register Data Formats Rev.1.00 Jun. 07, 2006 Page 36 of 1102 REJ09B0294-0100 Section 2 CPU 2.6.2 Memory Data Formats Figure 2.13 shows the data formats in memory. The H8SX CPU can access word data and longword data which are stored at any addresses in memory. When word data begins at an odd address or longword data begins at an address other than a multiple of 4, a bus cycle is divided into two or more accesses. For example, when longword data begins at an odd address, the bus cycle is divided into byte, word, and byte accesses. In this case, these accesses are assumed to be individual bus cycles. However, instructions to be fetched, word and longword data to be accessed during execution of the stack manipulation, branch table manipulation, block transfer instructions, and MAC instruction should be located to even addresses. When SP (ER7) is used as an address register to access the stack, the operand size should be word size or longword size. Data Type Address 7 1-bit data Address L 7 6 5 4 3 2 1 0 0 Data Format Byte data Address L MSB LSB Word data Address 2M MSB Address 2M + 1 LSB Longword data Address 2N MSB Address 2N + 1 Address 2N + 2 Address 2N + 3 LSB Figure 2.13 Memory Data Formats Rev.1.00 Jun. 07, 2006 Page 37 of 1102 REJ09B0294-0100 Section 2 CPU 2.7 Instruction Set The H8SX CPU has 87 types of instructions. The instructions are classified by function as shown in table 2.1. The arithmetic operation, logic operation, shift, and bit manipulation instructions are called operation instruction in this manual. Table 2.1 Function Data transfer Instruction Classification Instructions MOV MOVFPE* , MOVTPE* POP, PUSH* LDM, STM MOVA 1 6 6 Size B/W/L B W/L L B/W* B B/W/L B B/W/L B L B/W W/L L W/L B -- -- -- B/W/L B/W/L B B B 2 Types 6 Block transfer EEPMOV MOVMD MOVSD 3 Arithmetic operations ADD, ADDX, SUB, SUBX, CMP, NEG, INC, DEC DAA, DAS ADDS, SUBS MULXU, DIVXU, MULXS, DIVXS MULU, DIVU, MULS, DIVS MULU/U, MULS/U EXTU, EXTS TAS MAC LDMAC, STMAC CLRMAC 27 Logic operations Shift Bit manipulation AND, OR, XOR, NOT SHLL, SHLR, SHAL, SHAR, ROTL, ROTR, ROTXL, ROTXR BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST BSET/EQ, BSET/NE, BCLR/EQ, BCLR/NE, BSTZ, BISTZ BFLD, BFST 4 8 20 Rev.1.00 Jun. 07, 2006 Page 38 of 1102 REJ09B0294-0100 Section 2 CPU Function Branch Instructions BRA/BS, BRA/BC, BSR/BS, BSR/BC Bcc* , JMP, BSR, JSR, RTS RTS/L BRA/S 5 Size B* -- L* -- -- L* 5 5 3 Types 9 System control TRAPA, RTE, SLEEP, NOP RTE/L LDC, STC, ANDC, ORC, XORC 10 B/W/L Total 87 [Legend] B: Byte size W: Word size L: Longword size Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @-SP. 2. Size of data to be added with a displacement 3. Size of data to specify a branch condition 4. Bcc is the generic designation of a conditional branch instruction. 5. Size of general register to be restored 6. Not available in this LSI. Rev.1.00 Jun. 07, 2006 Page 39 of 1102 REJ09B0294-0100 Section 2 CPU 2.7.1 Instructions and Addressing Modes Table 2.2 indicates the combinations of instructions and addressing modes that the H8SX CPU can use. Table 2.2 Combinations of Instructions and Addressing Modes (1) Addressing Mode @(d, RnL.B/ Rn.W/ @ERn @(d,ERn) ERn.L) SD SD SD @-ERn/ @ERn+/ @ERn-/ @aa:16/ @+ERn @aa:8 @aa:32 -- SD S/D S/D* S/D* S/D* S S S S 2 2 1 Classification Data transfer Instruction MOV Size B/W/L B #xx S Rn SD S/D S/D S/D S/D S SD MOVFPE, 12 MOVTPE* POP, PUSH LDM, STM MOVA* Block transfer 4 B W/L L B/W B B/W/L B B B B B W/L S S S S SD* SD* SD* 3 3 3 EEPMOV MOVMD MOVSD Arithmetic ADD, CMP operations D S D SD S D D D S SD SD D D S SD SD SD D D S SD SD D D S SD SD D D S SD SD D D S SD SD D D S SD SD D D S SD SD D D S D D S SD SD SUB B B B B W/L D D S D D S SD SD S S S S SD SD ADDX, SUBX B/W/L B/W/L B/W/L INC, DEC DAA, DAS MULXU, DIVXU B/W/L B B/W ADDS, SUBS L SD* D D D 5 S:4 S:4 SD SD MULU, DIVU W/L Rev.1.00 Jun. 07, 2006 Page 40 of 1102 REJ09B0294-0100 Section 2 CPU Addressing Mode @(d, RnL.B/ Rn.W/ @ERn @(d,ERn) ERn.L) @-ERn/ @ERn+/ @ERn-/ @aa:16/ @+ERn @aa:8 @aa:32 -- Classification Instruction Size B/W W/L B W/L W/L B -- -- -- -- #xx S:4 S:4 Rn SD SD D D D Arithmetic MULXS, operations DIVXS MULS, DIVS NEG EXTU, EXTS TAS MAC CLRMAC LDMAC STMAC D D D D D D D D D D D D D D D D D O S D S D S SD D D D 6 7 Logic AND, OR, XOR B operations B B W/L NOT Shift SHLL, SHLR B W/L B B/W/L* B/W/L* SHAL, SHAR ROTL, ROTR ROTXL, ROTXR Bit manipulation BSET, BCLR, BNOT, BTST, BSET/cc, BCLR/cc B W/L D S SD SD D D D D D D D S SD SD D D D D D D D S SD SD D D D D D D D S SD SD D D D D D D D S D S SD SD D D D D D D D D D D D D D B D D D D BAND, BIAND, B BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST, BSTZ, BISTZ D D D D Rev.1.00 Jun. 07, 2006 Page 41 of 1102 REJ09B0294-0100 Section 2 CPU Addressing Mode @(d, RnL.B/ Rn.W/ @ERn @(d,ERn) ERn.L) S D S S 9 ClassifiInstruction cation Bit manipulation Branch System control BFLD BFST BRA/BS, BRA/BC* BSR/BS, BSR/BC* LDC (CCR, EXR) LDC (VBR, SBR) STC (CCR, EXR) STC (VBR, SBR) ANDC, ORC, XORC SLEEP NOP 8 8 Size B B B B B/W* L B/W* L B -- -- 9 #xx Rn D S @-ERn/ @ERn+/ @ERn-/ @aa:16/ @+ERn @aa:8 @aa:32 -- S D S S S D S S S S S S D D S S S* 10 D D D* 11 D S O O [Legend] d: d:16 or d:32 S: Can be specified as a source operand. D: Can be specified as a destination operand. SD: Can be specified as either a source or destination operand or both. S/D: Can be specified as either a source or destination operand. S:4: 4-bit immediate data can be specified as a source operand. Notes: 1. Only @aa:16 is available. 2. @ERn+ as a source operand and @-ERn as a destination operand 3. Specified by ER5 as a source address and ER6 as a destination address for data transfer. 4. Size of data to be added with a displacement 5. Only @ERn- is available 6. When the number of bits to be shifted is 1, 2, 4, 8, or 16 7. When the number of bits to be shifted is specified by 5-bit immediate data or a general register 8. Size of data to specify a branch condition 9. Byte when immediate or register direct, otherwise, word 10. Only @ERn+ is available 11. Only @-ERn is available 12. Not available in this LSI. Rev.1.00 Jun. 07, 2006 Page 42 of 1102 REJ09B0294-0100 Section 2 CPU Table 2.2 Combinations of Instructions and Addressing Modes (2) Addressing Mode @(RnL. B/Rn.W/ Classification Branch ERn.L, Instruction BRA/BS, BRA/BC BSR/BS, BSR/BC Bcc BRA BRA/S JMP BSR JSR Size @ERn @(d,PC) PC) @ @aa:24 aa:32 @@vec: @@ aa:8 7 -- -- -- -- -- -- -- -- -- O O O O O O O* O O O O O O O O O O O O O RTS, RTS/L -- System control TRAPA -- RTE, RTE/L -- [Legend] d: d:8 or d:16 Note: * Only @(d:8, PC) is available. Rev.1.00 Jun. 07, 2006 Page 43 of 1102 REJ09B0294-0100 Section 2 CPU 2.7.2 Table of Instructions Classified by Function Tables 2.4 to 2.11 summarize the instructions in each functional category. The notation used in these tables is defined in table 2.3. Table 2.3 Operation Notation Description General register (destination)* General register (source)* General register* General register (32-bit register) Destination operand Source operand Extended control register Condition-code register Vector base register Short address base register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Logical exclusive OR Move Logical not (logical complement) 8-, 16-, 24-, or 32-bit length * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). Operation Notation Rd Rs Rn ERn (EAd) (EAs) EXR CCR VBR SBR N Z V C PC SP #IMM disp + - x / :8/:16/:24/:32 Note: Rev.1.00 Jun. 07, 2006 Page 44 of 1102 REJ09B0294-0100 Section 2 CPU Table 2.4 Instruction MOV MOVFPE* MOVTPE* POP PUSH LDM Data Transfer Instructions Size B/W/L B B W/L W/L L Function #IMM (EAd), (EAs) (EAd) Transfers data between immediate data, general registers, and memory. (EAs) Rd Rs (EAs) @SP+ Rn Restores the data from the stack to a general register. Rn @-SP Saves general register contents on the stack. @SP+ Rn (register list) Restores the data from the stack to multiple general registers. Two, three, or four general registers which have serial register numbers can be specified. STM L Rn (register list) @-SP Saves the contents of multiple general registers on the stack. Two, three, or four general registers which have serial register numbers can be specified. MOVA B/W EA Rd Zero-extends and shifts the contents of a specified general register or memory data and adds them with a displacement. The result is stored in a general register. Note: Not available in this LSI. Rev.1.00 Jun. 07, 2006 Page 45 of 1102 REJ09B0294-0100 Section 2 CPU Table 2.5 Instruction EEPMOV.B EEPMOV.W Block Transfer Instructions Size B Function Transfers a data block. Transfers byte data which begins at a memory location specified by ER5 to a memory location specified by ER6. The number of byte data to be transferred is specified by R4 or R4L. B Transfers a data block. Transfers byte data which begins at a memory location specified by ER5 to a memory location specified by ER6. The number of byte data to be transferred is specified by R4. MOVMD.B MOVMD.W W Transfers a data block. Transfers word data which begins at a memory location specified by ER5 to a memory location specified by ER6. The number of word data to be transferred is specified by R4. MOVMD.L L Transfers a data block. Transfers longword data which begins at a memory location specified by ER5 to a memory location specified by ER6. The number of longword data to be transferred is specified by R4. MOVSD.B B Transfers a data block with zero data detection. Transfers byte data which begins at a memory location specified by ER5 to a memory location specified by ER6. The number of byte data to be transferred is specified by R4. When zero data is detected during transfer, the transfer stops and execution branches to a specified address. Rev.1.00 Jun. 07, 2006 Page 46 of 1102 REJ09B0294-0100 Section 2 CPU Table 2.6 Instruction ADD SUB Arithmetic Operation Instructions Size B/W/L Function (EAd) #IMM (EAd), (EAd) (EAs) (EAd) Performs addition or subtraction on data between immediate data, general registers, and memory. Immediate byte data cannot be subtracted from byte data in a general register. (EAd) #IMM C (EAd), (EAd) (EAs) C (EAd) Performs addition or subtraction with carry on data between immediate data, general registers, and memory. The addressing mode which specifies a memory location can be specified as register indirect with post-decrement or register indirect. Rd 1 Rd, Rd 2 Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.) Rd 1 Rd, Rd 2 Rd, Rd 4 Rd Adds or subtracts the value 1, 2, or 4 to or from data in a general register. Rd (decimal adjust) Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 2-digit 4-bit BCD data. Rd x Rs Rd Performs unsigned multiplication on data in two general registers: either 8 bits x 8 bits 16 bits, or 16 bits x 16 bits 32 bits. Rd x Rs Rd Performs unsigned multiplication on data in two general registers: either 8 bits x 8 bits 16 bits, or 16 bits x 16 bits 32 bits. Rd x Rs Rd Performs unsigned multiplication on data in two general registers (32 bits x 32 bits upper 32 bits). Rd x Rs Rd Performs signed multiplication on data in two general registers: either 8 bits x 8 bits 16 bits, or 16 bits x 16 bits 32 bits. Rd x Rs Rd Performs signed multiplication on data in two general registers: either 16 bits x 16 bits 16 bits, or 32 bits x 32 bits 32 bits. Rd x Rs Rd Performs signed multiplication on data in two general registers (32 bits x 32 bits upper 32 bits). Rd / Rs Rd Performs unsigned division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder, or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. ADDX SUBX B/W/L INC DEC ADDS SUBS DAA DAS MULXU B/W/L L B B/W MULU W/L MULU/U L MULXS B/W MULS W/L MULS/U L DIVXU B/W Rev.1.00 Jun. 07, 2006 Page 47 of 1102 REJ09B0294-0100 Section 2 CPU Instruction DIVU Size W/L Function Rd / Rs Rd Performs unsigned division on data in two general registers: either 16 bits / 16 bits 16-bit quotient, or 32 bits / 32 bits 32-bit quotient. Rd / Rs Rd Performs signed division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder, or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. Rd / Rs Rd Performs signed division on data in two general registers: either 16 bits / 16 bits 16-bit quotient, or 32 bits / 32 bits 32-bit quotient. (EAd) - #IMM, (EAd) - (EAs) Compares data between immediate data, general registers, and memory and stores the result in CCR. 0 - (EAd) (EAd) Takes the two's complement (arithmetic complement) of data in a general register or the contents of a memory location. (EAd) (zero extension) (EAd) Performs zero-extension on the lower 8 or 16 bits of data in a general register or memory to word or longword size. The lower 8 bits to word or longword, or the lower 16 bits to longword can be zero-extended. (EAd) (sign extension) (EAd) Performs sign-extension on the lower 8 or 16 bits of data in a general register or memory to word or longword size. The lower 8 bits to word or longword, or the lower 16 bits to longword can be sign-extended. @ERd - 0, 1 ( DIVXS B/W DIVS W/L CMP B/W/L NEG B/W/L EXTU W/L EXTS W/L TAS MAC B -- CLRMAC LDMAC STMAC -- -- -- Rev.1.00 Jun. 07, 2006 Page 48 of 1102 REJ09B0294-0100 Section 2 CPU Table 2.7 Instruction AND Logic Operation Instructions Size B/W/L Function (EAd) #IMM (EAd), (EAd) (EAs) (EAd) Performs a logical AND operation on data between immediate data, general registers, and memory. OR B/W/L (EAd) #IMM (EAd), (EAd) (EAs) (EAd) Performs a logical OR operation on data between immediate data, general registers, and memory. XOR B/W/L (EAd) #IMM (EAd), (EAd) (EAs) (EAd) Performs a logical exclusive OR operation on data between immediate data, general registers, and memory. NOT B/W/L (EAd) (EAd) Takes the one's complement of the contents of a general register or a memory location. Table 2.8 Instruction SHLL SHLR Shift Operation Instructions Size B/W/L Function (EAd) (shift) (EAd) Performs a logical shift on the contents of a general register or a memory location. The contents of a general register or a memory location can be shifted by 1, 2, 4, 8, or 16 bits. The contents of a general register can be shifted by any bits. In this case, the number of bits is specified by 5-bit immediate data or the lower 5 bits of the contents of a general register. SHAL SHAR B/W/L (EAd) (shift) (EAd) Performs an arithmetic shift on the contents of a general register or a memory location. 1-bit or 2-bit shift is possible. ROTL ROTR ROTXL ROTXR B/W/L (EAd) (rotate) (EAd) Rotates the contents of a general register or a memory location. 1-bit or 2-bit rotation is possible. B/W/L (EAd) (rotate) (EAd) Rotates the contents of a general register or a memory location with the carry bit. 1-bit or 2-bit rotation is possible. Rev.1.00 Jun. 07, 2006 Page 49 of 1102 REJ09B0294-0100 Section 2 CPU Table 2.9 Instruction BSET Bit Manipulation Instructions Size B Function 1 ( BSET/cc B BCLR B BCLR/cc B BNOT B BTST B BAND B BIAND B BOR B Rev.1.00 Jun. 07, 2006 Page 50 of 1102 REJ09B0294-0100 Section 2 CPU Instruction BIOR Size B Function C [~ ( BXOR B C ( BIXOR B C [~ ( BLD B ( BILD B ~ ( BST B C ( BSTZ B Z ( BIST B C ( Rev.1.00 Jun. 07, 2006 Page 51 of 1102 REJ09B0294-0100 Section 2 CPU Instruction BISTZ Size B Function Z ( BFLD B (EAs) (bit field) Rd Transfers a specified bit field in memory location contents to the lower bits of a specified general register. BFST B Rs (EAd) (bit field) Transfers the lower bits of a specified general register to a specified bit field in memory location contents. Table 2.10 Branch Instructions Instruction BRA/BS BRA/BC BSR/BS BSR/BC Bcc BRA/S -- -- B Size B Function Tests a specified bit in memory location contents. If the specified condition is satisfied, execution branches to a specified address. Tests a specified bit in memory location contents. If the specified condition is satisfied, execution branches to a subroutine at a specified address. Branches to a specified address if the specified condition is satisfied. Branches unconditionally to a specified address after executing the next instruction. The next instruction should be a 1-word instruction except for the block transfer and branch instructions. Branches unconditionally to a specified address. Branches to a subroutine at a specified address. Branches to a subroutine at a specified address. Returns from a subroutine. Returns from a subroutine, restoring data from the stack to multiple general registers. JMP BSR JSR RTS RTS/L -- -- -- -- -- Rev.1.00 Jun. 07, 2006 Page 52 of 1102 REJ09B0294-0100 Section 2 CPU Table 2.11 System Control Instructions Instruction TRAPA RTE RTE/L SLEEP LDC Size -- -- -- -- B/W Function Starts trap-instruction exception handling. Returns from an exception-handling routine. Returns from an exception-handling routine, restoring data from the stack to multiple general registers. Causes a transition to a power-down state. #IMM CCR, (EAs) CCR, #IMM EXR, (EAs) EXR Loads immediate data or the contents of a general register or a memory location to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. L STC B/W Rs VBR, Rs SBR Transfers the general register contents to VBR or SBR. CCR (EAd), EXR (EAd) Transfers the contents of CCR or EXR to a general register or memory. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. L ANDC ORC XORC NOP B B B -- VBR Rd, SBR Rd Transfers the contents of VBR or SBR to a general register. CCR #IMM CCR, EXR #IMM EXR Logically ANDs the CCR or EXR contents with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically ORs the CCR or EXR contents with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically exclusive-ORs the CCR or EXR contents with immediate data. PC + 2 PC Only increments the program counter. Rev.1.00 Jun. 07, 2006 Page 53 of 1102 REJ09B0294-0100 Section 2 CPU 2.7.3 Basic Instruction Formats The H8SX CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Figure 2.14 shows examples of instruction formats. (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rn rm ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension op EA (disp) (4) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:16, etc rn rm MOV.B @(d:16, Rn), Rm, etc. Figure 2.14 Instruction Formats * Operation Field Indicates the function of the instruction, and specifies the addressing mode and operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. * Register Field Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. * Effective Address Extension 8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. * Condition Field Specifies the branch condition of Bcc instructions. Rev.1.00 Jun. 07, 2006 Page 54 of 1102 REJ09B0294-0100 Section 2 CPU 2.8 Addressing Modes and Effective Address Calculation The H8SX CPU supports the 11 addressing modes listed in table 2.12. Each instruction uses a subset of these addressing modes. Bit manipulation instructions use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2.12 Addressing Modes No. Addressing Mode 1 2 3 4 5 Register direct Register indirect Register indirect with displacement Index register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Register indirect with pre-increment Register indirect with post-decrement 6 7 8 9 10 11 Absolute address Immediate Program-counter relative Program-counter relative with index register Memory indirect Extended memory indirect Symbol Rn @ERn @(d:2,ERn)/@(d:16,ERn)/@(d:32,ERn) @(d:16, RnL.B)/@(d:16,Rn.W)/@(d:16,ERn.L) @(d:32, RnL.B)/@(d:32,Rn.W)/@(d:32,ERn.L) @ERn+ @-ERn @+ERn @ERn- @aa:8/@aa:16/@aa:24/@aa:32 #xx:3/#xx:4/#xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @(RnL.B,PC)/@(Rn.W,PC)/@(ERn.L,PC) @@aa:8 @@vec:7 2.8.1 Register Direct--Rn The operand value is the contents of an 8-, 16-, or 32-bit general register which is specified by the register field in the instruction code. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. Rev.1.00 Jun. 07, 2006 Page 55 of 1102 REJ09B0294-0100 Section 2 CPU 2.8.2 Register Indirect--@ERn The operand value is the contents of the memory location which is pointed to by the contents of an address register (ERn). ERn is specified by the register field of the instruction code. In advanced mode, if this addressing mode is used in a branch instruction, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00). 2.8.3 Register Indirect with Displacement --@(d:2, ERn), @(d:16, ERn), or @(d:32, ERn) The operand value is the contents of a memory location which is pointed to by the sum of the contents of an address register (ERn) and a 16- or 32-bit displacement. ERn is specified by the register field of the instruction code. The displacement is included in the instruction code and the 16-bit displacement is sign-extended when added to ERn. This addressing mode has a short format (@(d:2, ERn)). The short format can be used when the displacement is 1, 2, or 3 and the operand is byte data, when the displacement is 2, 4, or 6 and the operand is word data, or when the displacement is 4, 8, or 12 and the operand is longword data. 2.8.4 Index Register Indirect with Displacement--@(d:16,RnL.B), @(d:32,RnL.B), @(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L) The operand value is the contents of a memory location which is pointed to by the sum of the following operation result and a 16- or 32-bit displacement: a specified bits of the contents of an address register (RnL, Rn, ERn) specified by the register field in the instruction code are zeroextended to 32-bit data and multiplied by 1, 2, or 4. The displacement is included in the instruction code and the 16-bit displacement is sign-extended when added to ERn. If the operand is byte data, ERn is multiplied by 1. If the operand is word or longword data, ERn is multiplied by 2 or 4, respectively. Rev.1.00 Jun. 07, 2006 Page 56 of 1102 REJ09B0294-0100 Section 2 CPU 2.8.5 Register Indirect with Post-Increment, Pre-Decrement, Pre-Increment, or Post-Decrement--@ERn+, @-ERn, @+ERn, or @ERn- * Register indirect with post-increment--@ERn+ The operand value is the contents of a memory location which is pointed to by the contents of an address register (ERn). ERn is specified by the register field of the instruction code. After the memory location is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word access, or 4 for longword access. * Register indirect with pre-decrement--@-ERn The operand value is the contents of a memory location which is pointed to by the following operation result: the value 1, 2, or 4 is subtracted from the contents of an address register (ERn). ERn is specified by the register field of the instruction code. After that, the operand value is stored in the address register. The value subtracted is 1 for byte access, 2 for word access, or 4 for longword access. * Register indirect with pre-increment--@+ERn The operand value is the contents of a memory location which is pointed to by the following operation result: the value 1, 2, or 4 is added to the contents of an address register (ERn). ERn is specified by the register field of the instruction code. After that, the operand value is stored in the address register. The value added is 1 for byte access, 2 for word access, or 4 for longword access. * Register indirect with post-decrement--@ERn- The operand value is the contents of a memory location which is pointed to by the contents of an address register (ERn). ERn is specified by the register field of the instruction code. After the memory location is accessed, 1, 2, or 4 is subtracted from the address register contents and the remainder is stored in the address register. The value subtracted is 1 for byte access, 2 for word access, or 4 for longword access. using this addressing mode, data to be written is the contents of the general register after calculating an effective address. If the same general register is specified in an instruction and two effective addresses are calculated, the contents of the general register after the first calculation of an effective address is used in the second calculation of an effective address. Example 1: MOV.W R0, @ER0+ When ER0 before execution is H'12345678, H'567A is written at H'12345678. Rev.1.00 Jun. 07, 2006 Page 57 of 1102 REJ09B0294-0100 Section 2 CPU Example 2: MOV.B @ER0+, @ER0+ When ER0 before execution is H'00001000, H'00001000 is read and the contents is written at H'00001001. After execution, ER0 is H'00001002. 2.8.6 Absolute Address--@aa:8, @aa:16, @aa:24, or @aa:32 The operand value is the contents of a memory location which is pointed to by an absolute address included in the instruction code. There are 8-bit (@aa:8), 16-bit (@aa:16), 24-bit (@aa:24), and 32-bit (@aa:32) absolute addresses. To access the data area, the absolute address of 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) is used. For an 8-bit absolute address, the upper 24 bits are specified by SBR. For a 16bit absolute address, the upper 16 bits are sign-extended. A 32-bit absolute address can access the entire address space. To access the program area, the absolute address of 24 bits (@aa:24) or 32 bits (@aa:32) is used. For a 24-bit absolute address, the upper 8 bits are all assumed to be 0 (H'00). Table 2.13 shows the accessible absolute address ranges. Table 2.13 Absolute Address Access Ranges Absolute Address Data area 8 bits (@aa:8) 16 bits (@aa:16) 32 bits (@aa:32) Program area 24 bits (@aa:24) 32 bits (@aa:32) Normal Mode Middle Mode Advanced Mode Maximum Mode A consecutive 256-byte area (the upper address is set in SBR) H'0000 to H'FFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF H'000000 to H'FFFFFF H'00000000 to H'00007FFF, H'FFFF8000 to H'FFFFFFFF H'00000000 to H'FFFFFFFF H'00000000 to H'00FFFFFF H'00000000 to H'00FFFFFF H'00000000 to H'FFFFFFFF Rev.1.00 Jun. 07, 2006 Page 58 of 1102 REJ09B0294-0100 Section 2 CPU 2.8.7 Immediate--#xx The operand value is 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) data included in the instruction code. This addressing mode has short formats in which 3- or 4-bit immediate data can be used. When the size of immediate data is less than that of the destination operand value (byte, word, or longword) the immediate data is zero-extended. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, for specifying a bit number. The BFLD and BFST instructions contain 8-bit immediate data in the instruction code, for specifying a bit field. The TRAPA instruction contains 2-bit immediate data in the instruction code, for specifying a vector address. 2.8.8 Program-Counter Relative--@(d:8, PC) or @(d:16, PC) This mode is used in the Bcc and BSR instructions. The operand value is a 32-bit branch address, which is the sum of an 8- or 16-bit displacement in the instruction code and the 32-bit address of the PC contents. The 8-bit or 16-bit displacement is sign-extended to 32 bits when added to the PC contents. The PC contents to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is -126 to +128 bytes (-63 to +64 words) or -32766 to +32768 bytes (-16383 to +16384 words) from the branch instruction. The resulting value should be an even number. In advanced mode, only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). 2.8.9 Program-Counter Relative with Index Register--@(RnL.B, PC), @(Rn.W, PC), or @(ERn.L, PC) This mode is used in the Bcc and BSR instructions. The operand value is a 32-bit branch address, which is the sum of the following operation result and the 32-bit address of the PC contents: the contents of an address register specified by the register field in the instruction code (RnL, Rn, or ERn) is zero-extended and multiplied by 2. The PC contents to which the displacement is added is the address of the first byte of the next instruction. In advanced mode, only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). Rev.1.00 Jun. 07, 2006 Page 59 of 1102 REJ09B0294-0100 Section 2 CPU 2.8.10 Memory Indirect--@@aa:8 This mode can be used by the JMP and JSR instructions. The operand value is a branch address, which is the contents of a memory location pointed to by an 8-bit absolute address in the instruction code. The upper bits of an 8-bit absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in other modes). In normal mode, the memory location is pointed to by word-size data and the branch address is 16 bits long. In other modes, the memory location is pointed to by longword-size data. In middle or advanced mode, the first byte of the longword-size data is assumed to be all 0 (H'00). Note that the top part of the address range is also used as the exception handling vector area. A vector address of an exception handling other than a reset or a CPU address error can be changed by VBR. Figure 2.15 shows an example of specification of a branch address using this addressing mode. Specified by @aa:8 Branch address Specified by @aa:8 Reserved Branch address (a) Normal Mode (b) Advanced Mode Figure 2.15 Branch Address Specification in Memory Indirect Mode Rev.1.00 Jun. 07, 2006 Page 60 of 1102 REJ09B0294-0100 Section 2 CPU 2.8.11 Extended Memory Indirect--@@vec:7 This mode can be used by the JMP and JSR instructions. The operand value is a branch address, which is the contents of a memory location pointed to by the following operation result: the sum of 7-bit data in the instruction code and the value of H'80 is multiplied by 2 or 4. The address range to store a branch address is H'0100 to H'01FF in normal mode and H'000200 to H'0003FF in other modes. In assembler notation, an address to store a branch address is specified. In normal mode, the memory location is pointed to by word-size data and the branch address is 16 bits long. In other modes, the memory location is pointed to by longword-size data. In middle or advanced mode, the first byte of the longword-size data is assumed to be all 0 (H'00). 2.8.12 Effective Address Calculation Tables 2.14 and 2.15 show how effective addresses are calculated in each addressing mode. The lower bits of the effective address are valid and the upper bits are ignored (zero extended or sign extended) according to the CPU operating mode. The valid bits in middle mode are as follows: * The lower 16 bits of the effective address are valid and the upper 16 bits are sign-extended for the transfer and operation instructions. * The lower 24 bits of the effective address are valid and the upper eight bits are zero-extended for the branch instructions. Rev.1.00 Jun. 07, 2006 Page 61 of 1102 REJ09B0294-0100 Section 2 CPU Table 2.14 Effective Address Calculation for Transfer and Operation Instructions No. 1 Addressing Mode and Instruction Format Immediate op IMM Effective Address Calculation Effective Address (EA) 2 Register direct op rm rn 31 General register contents op r 31 General register contents op disp r 31 Sign extension 31 General register contents op r disp disp 15 disp 0 0 0 0 31 0 3 Register indirect 4 Register indirect with 16-bit displacement + 31 0 Register indirect with 32-bit displacement + 31 0 5 Index register indirect with 16-bit displacement 31 0 Zero extension Contents of general register (RL, R, or ER) 1, 2, or 4 15 Sign extension disp 0 x + 31 0 op disp r 31 Index register indirect with 32-bit displacement 31 0 Zero extension Contents of general register (RL, R, or ER) 1, 2, or 4 0 disp x + 31 0 op r disp 31 6 Register indirect with post-increment or post-decrement op r 31 General register contents 0 1, 2, or 4 31 0 Register indirect with pre-increment or pre-decrement op r 31 General register contents 0 1, 2, or 4 31 0 7 8-bit absolute address 31 op aa SBR 7 aa 0 31 0 16-bit absolute address op aa 31 Sign extension 15 aa 0 31 0 32-bit absolute address op aa 31 aa 0 31 0 Rev.1.00 Jun. 07, 2006 Page 62 of 1102 REJ09B0294-0100 Section 2 CPU Table 2.15 Effective Address Calculation for Branch Instructions No. 1 Addressing Mode and Instruction Format Register indirect op r Effective Address Calculation 31 General register contents 0 Effective Address (EA) 31 0 2 Program-counter relative with 8-bit displacement 31 PC contents 31 op disp Sign extension 7 disp 0 0 + 31 0 Program-counter relative with 16-bit displacement 31 PC contents op disp 31 Sign extension 15 disp 0 0 31 0 + 3 Program-counter relative with index register 31 Zero extension Contents of general register (RL, R, or ER) 0 op r 31 PC contents 2 0 x + 31 0 4 24-bit absolute address op aa Zero 31 extension 23 aa 0 31 0 32-bit absolute address op aa 31 aa 0 31 0 5 Memory indirect 31 op aa 31 Memory contents Zero extension 7 aa 0 31 0 0 6 Extended memory indirect 31 op vec Zero extension 7 1 0 vec 2 or 4 x 31 31 Memory contents 0 0 31 0 2.8.13 MOVA Instruction The MOVA instruction stores the effective address in a general register. 1. Firstly, data is obtained by the addressing mode shown in item 2 of table 2.14. 2. Next, the effective address is calculated using the obtained data as the index by the addressing mode shown in item 5 of table 2.14. The obtained data is used instead of the general register. The result is stored in a general register. For details, see H8SX Family Software Manual. Rev.1.00 Jun. 07, 2006 Page 63 of 1102 REJ09B0294-0100 Section 2 CPU 2.9 Processing States The H8SX CPU has five main processing states: the reset state, exception-handling state, program execution state, bus-released state, and program stop state. Figure 2.16 indicates the state transitions. * Reset state In this state the CPU and internal peripheral modules are all initialized and stopped. When the RES input goes low, all current processing stops and the CPU enters the reset state. All interrupts are masked in the reset state. Reset exception handling starts when the RES signal changes from low to high. For details, see section 4, Exception Handling. The reset state can also be entered by a watchdog timer overflow when available. * Exception-handling state The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to activation of an exception source, such as, a reset, trace, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception handling vector table and branches to that address. For further details, see section 4, Exception Handling. * Program execution state In this state the CPU executes program instructions in sequence. * Bus-released state The bus-released state occurs when the bus has been released in response to a bus request from a bus master other than the CPU. While the bus is released, the CPU halts operations. * Program stop state This is a power-down state in which the CPU stops operating. The program stop state occurs when a SLEEP instruction is executed or the CPU enters hardware standby mode. For details, see section 23, Power-Down Modes. Reset state* RES = high Exception-handling state Request for exception handling RES = low Interrupt request Bus-released state Bus request Bus request End of bus request Program stop state SLEEP instruction End of bus request End of exception handling Program execution state Note: * A transition to the reset state occurs whenever the RES signal goes low. A transition can also be made to the reset state when the watchdog timer overflows. Figure 2.16 State Transitions Rev.1.00 Jun. 07, 2006 Page 64 of 1102 REJ09B0294-0100 Section 3 MCU Operating Modes Section 3 MCU Operating Modes 3.1 Operating Mode Selection This LSI has five operating modes (modes 2, 4, 5, 6, and 7). The operating mode is selected by the setting of mode pins MD2 to MD0. The setting of mode pin MD3 determines whether the various operating modes are with the SDRAM interface enabled or disabled. Table 3.1 lists MCU operating mode settings. Table 3.1 MCU Operating Mode Settings CPU Operating Mode Advanced Address Space LSI Initiation Mode On-chip ROM disabled extended mode On-chip ROM enabled extended mode Single-chip mode On-Chip ROM Enabled Disabled Disabled Enabled External Data Bus Width Default Max. 8 bits 16 bits 8 bits 8 bits 16 bits 16 bits 16 bits 16 bits MCU Operating Mode MD2 2 4 5 6 0 1 1 1 MD1 1 0 0 1 MD0 0 0 1 0 16 Mbytes Boot mode 7 1 1 1 Enabled 8 bits 16 bits Table 3.2 MD3 0 1 SDRAM Interface Selection for MCU Operating Mode SDRAM Interface Disabled Enabled In this LSI, an advanced mode as the CPU operating mode and a 16-Mbyte address space are available. The initial external bus widths are eight or 16 bits. As the LSI initiation mode, the external extended mode, on-chip ROM initiation mode, or single-chip initiation mode can be selected. Mode 2 is the boot mode in which the flash memory can be programmed and erased. For details on the boot mode, see section 21, Flash Memory (0.18-m F-ZTAT Version). Rev.1.00 Jun. 07, 2006 Page 65 of 1102 REJ09B0294-0100 Section 3 MCU Operating Modes Mode 7 is a single-chip initiation mode. In the initial state, all areas are designated to 8-bit access space and all I/O ports can be used as general input/output ports. The external address space cannot be accessed in the initial state, but setting the EXPE bit in the system control register (SYSCR) to 1 enables to use the external address space. After the external address space is enabled, ports D, E, and F can be used as an address output bus and ports H and I as a data bus by specifying the data direction register (DDR) for each port. Modes 4 to 6 are external extended modes, in which the external memory and devices can be accessed. In the external extended modes, the external address space can be designated as 8-bit or 16-bit address space for each area by the bus controller after starting program execution. If 16-bit address space is designated for any one area, it is called the 16-bit bus widths mode. If 8bit address space is designated for all areas, it is called the 8-bit bus width mode. 3.2 Register Descriptions The following registers are related to the operating mode setting. * Mode control register (MDCR) * System control register (SYSCR) 3.2.1 Mode Control Register (MDCR) MDCR indicates the current operating mode. When MDCR is read from, the states of signals MD3 to MD0 are latched. Latching is released by a reset. Bit Bit Name 15 MDS7 14 1 R 6 1 R 13 0 R 5 0 R 12 1 R 4 1 R 11 MDS3 Undefined* R 3 Undefined* R 10 MDS2 Undefined* R 2 Undefined* R 9 MDS1 Undefined* R 1 Undefined* R 8 MDS0 Undefined* R 0 Undefined* R Initial Value Undefined* R/W Bit Bit Name R 7 Initial Value Undefined* R/W R Note: * Determined by pins MD3 to MD0. Rev.1.00 Jun. 07, 2006 Page 66 of 1102 REJ09B0294-0100 Section 3 MCU Operating Modes Bit 15 Bit Name MDS7 Initial Value R/W Undefined* R Descriptions Indicates the value set by mode pin (MD3). When MDCR is read, the input level on the MD3 pin is latched. This latching is released by a reset. 14 13 12 11 10 9 8 MDS3 MDS2 MDS1 MDS0 1 0 1 Undefined* Undefined* Undefined* Undefined* R R R R R R R Reserved These are read-only bits and cannot be modified. Mode Select 3 to 0 These bits indicate the operating mode selected by the mode pins (MD2 to MD0) (see table 3.2). When MDCR is read, the signal levels input on pins MD2 to MD0 are latched into these bits. These latches are released by a reset. Reserved These are read-only bits and cannot be modified. 7 6 5 4 3 2 1 0 Note: * Undefined* 1 0 1 Undefined* Undefined* Undefined* Undefined* R R R R R R R R Determined by pins MD3 to MD0. Table 3.3 Settings of Bits MDS3 to MDS0 Mode Pins MD2 0 1 1 1 1 MD1 1 0 0 1 1 MD0 0 0 1 0 1 MDS3 1 0 0 0 0 MDS2 1 0 0 1 1 MDCR MDS1 0 1 0 0 0 MDS0 0 0 1 1 0 MCU Operating Mode 2 4 5 6 7 Rev.1.00 Jun. 07, 2006 Page 67 of 1102 REJ09B0294-0100 Section 3 MCU Operating Modes 3.2.2 System Control Register (SYSCR) SYSCR controls MAC saturation operation, selects bus width mode for instruction fetch, sets external bus mode, enables/disables the on-chip RAM, and selects the DTC address mode. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 1 R/W 7 0 R/W 14 1 R/W 6 0 R/W 13 MACS 0 R/W 5 0 R/W 12 1 R/W 4 0 R/W 11 FETCHMD 0 R/W 3 0 R/W 10 Undefined* R 2 0 R/W 9 EXPE Undefined* R/W 1 DTCMD 1 R/W 8 RAME 1 R/W 0 1 R/W Note: * The initial value depends on the startup mode. Bit 15 14 13 Bit Name MACS Initial Value 1 1 0 R/W R/W R/W R/W Descriptions Reserved These bits are always read as 1. The write value should always be 1. MAC Saturation Operation Control Selects either saturation operation or non-saturation operation for the MAC instruction. 0: MAC instruction is non-saturation operation 1: MAC instruction is saturation operation 12 1 R/W Reserved This bit is always read as 1. The write value should always be 1. 11 FETCHMD 0 R/W Instruction Fetch Mode Select This LSI can prefetch an instruction in units of 16 bits or 32 bits. Select the bus width for instruction fetch depending on the used memory for the storage of 1 programs* . 0: 32-bit mode 1: 16-bit mode Rev.1.00 Jun. 07, 2006 Page 68 of 1102 REJ09B0294-0100 Section 3 MCU Operating Modes Bit 10 Bit Name Initial Value Undefined* 2 R/W R Descriptions Reserved This bit is fixed at 1 in on-chip ROM enabled mode, and 0 in on-chip ROM disabled mode. This bit cannot be changed. 9 EXPE Undefined* 2 R/W External Bus Mode Enable Selects external bus mode. In external extended mode, this bit is fixed 1 and cannot be changed. In single-chip mode, the initial value of this bit is 0, and can be read from or written to. When writing 0 to this bit after reading EXPE = 1, an external bus cycle should not be executed. The external bus cycle may be carried out in parallel with the internal bus cycle depending on the setting of the write data buffer function. 0: External bus disabled 1: External bus enabled 8 RAME 1 R/W RAM Enable Enables or disables the on-chip RAM. This bit is initialized when the reset state is released. Do not write 0 during access to the on-chip RAM. 0: On-chip RAM disabled 1: On-chip RAM enabled 7 to 2 All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. 1 DTCMD 1 R/W DTC Mode Select Selects DTC operating mode. 0: DTC is in full-address mode 1: DTC is in short address mode 0 1 R/W Reserved This bit is always read as 1. The write value should always be 1. Notes: 1. For details on instruction fetch mode, see section 2.3, Instruction Fetch. 2. The initial value depends on the LSI initiation mode. Rev.1.00 Jun. 07, 2006 Page 69 of 1102 REJ09B0294-0100 Section 3 MCU Operating Modes 3.3 3.3.1 Operating Mode Descriptions Mode 2 This is the boot mode for the flash memory. The LSI operates in the same way as in mode 7 except for programming and erasing of the flash memory. For details, see section 21, Flash Memory (0.18-m F-ZTAT Version). 3.3.2 Mode 4 The CPU operating mode is advanced mode in which the address space is 16 Mbytes, and the onchip ROM is disabled. The initial bus width mode immediately after a reset is 16 bits, with 16-bit access to all areas. Ports D, E, and F function as an address bus, ports H and I function as a data bus, and parts of ports A and B function as bus control signals. However, if all areas are designated as an 8-bit access space by the bus controller, the bus mode switches to eight bits, and only port H functions as a data bus. 3.3.3 Mode 5 The CPU operating mode is advanced mode in which the address space is 16 Mbytes, and the onchip ROM is disabled. The initial bus width mode immediately after a reset is eight bits, with 8-bit access to all areas. Ports D, E, and F function as an address bus, port H functions as a data bus, and parts of ports A and B function as bus control signals. However, if any area is designated as a 16-bit access space by the bus controller, the bus width mode switches to 16 bits, and ports H and I function as a data bus. Rev.1.00 Jun. 07, 2006 Page 70 of 1102 REJ09B0294-0100 Section 3 MCU Operating Modes 3.3.4 Mode 6 The CPU operating mode is advanced mode in which the address space is 16 Mbytes, and the onchip ROM is enabled. The initial bus width mode immediately after a reset is eight bits, with 8-bit access to all areas. Ports D, E, and F function as input ports, but they can be used as an address bus by specifying the data direction register (DDR) for each port. For details, see section 9, I/O Ports. Port H functions as a data bus, and parts of ports A and B function as bus control signals. However, if any area is designated as a 16-bit access space by the bus controller, the bus width mode switches to 16 bits, and ports H and I function as a data bus. 3.3.5 Mode 7 The CPU operating mode is advanced mode in which the address space is 16 Mbytes, and the onchip ROM is enabled. In the initial state, all areas are designated to 8-bit access space and all I/O ports can be used as general input/output ports. The external address space cannot be accessed in the initial state, but setting the EXPE bit in the system control register (SYSCR) to 1 enables the external address space. After the external address space is enabled, ports D, E, and F can be used as an address output bus and ports H and I as a data bus by specifying the data direction register (DDR) for each port. For details, see section 9, I/O Ports. Rev.1.00 Jun. 07, 2006 Page 71 of 1102 REJ09B0294-0100 Section 3 MCU Operating Modes 3.3.6 Pin Functions Table 3.4 lists the pin functions in each operating mode. Table 3.4 Port Port A PA7 PA6 to PA3 PA2 to PA0 Port B PB7 to PB1 PB0 Port C Port D Port E Port F PF4 to PF0 PF7 to PF5 Port H Port I PC3, PC2 Pin Functions in Each Operating Mode (Advanced Mode) Mode 2 P*/C P*/C P*/C P*/C P*/C P*/C P*/A P*/A P*/A P*/A P*/D P*/D Mode 4 P/C* P/C* P*/C P*/C P/C* P*/C A A A P*/A D P/D* Mode 5 P/C* P/C* P*/C P*/C P/C* P*/C A A A P*/A D P*/D Mode 6 P/C* P/C* P*/C P*/C P*/C P*/C P*/A P*/A P*/A P*/A D P*/D Mode 7 P*/C P*/C P*/C P*/C P*/C P*/C P*/A P*/A P*/A P*/A P*/D P*/D [Legend] P: I/O port A: Address bus output D: Data bus input/output C: Control signals, clock input/output *: Immediately after a reset Rev.1.00 Jun. 07, 2006 Page 72 of 1102 REJ09B0294-0100 Section 3 MCU Operating Modes 3.4 3.4.1 Address Map Address Map Figures 3.1 and 3.2 show the address map in each operating mode. Mode 2 Boot mode (Advanced mode) H'000000 On-chip ROM H'000000 Mode 4 On-chip ROM disabled extended mode (Advanced mode) H'060000 H'080000 Access prohibited area External address space External address space/ reserved area*1, *3 H'FD9000 H'FDC000 Access prohibited area External address space/ reserved area*1, *3 H'FD9000 H'FDC000 Access prohibited area External address space H'FF0000 H'FF2000 Access prohibited area On-chip RAM/ external address space*4 External address space H'FFEA00 H'FFFF00 H'FFFF20 H'FFFFFF On-chip I/O registers External address space On-chip I/O registers H'FF0000 H'FF2000 Access prohibited area On-chip RAM*2 H'FFC000 External address space/ reserved area*1, *3 H'FFEA00 On-chip I/O registers H'FFC000 H'FFFF00 External address space/ reserved area*1, *3 H'FFFF20 On-chip I/O registers H'FFFFFF Notes: 1. 2. 3. 4. This area is specified as the external address space when EXPE = 1 and the reserved area when EXPE = 0. The on-chip RAM is used for flash memory programming. Do not clear the RAME bit to 0. Do not access the reserved areas. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0. Figure 3.1 Address Map in Each Operating Mode of H8SX/1663 (1) Rev.1.00 Jun. 07, 2006 Page 73 of 1102 REJ09B0294-0100 Section 3 MCU Operating Modes Mode 5 On-chip ROM disabled extended mode (Advanced mode) H'000000 H'000000 Mode 6 On-chip ROM enabled extended mode (Advanced mode) H'000000 Mode 7 Single-chip mode (Advanced mode) On-chip ROM On-chip ROM H'060000 External address space H'080000 Access prohibited area H'060000 H'080000 Access prohibited area External address space External address space/ reserved area*1, *3 H'FD9000 H'FDC000 Access prohibited area H'FD9000 H'FDC000 Access prohibited area H'FD9000 H'FDC000 Access prohibited area External address space/ reserved area*1, *3 Access prohibited area On-chip RAM/ external address space*2 External address space/ reserved area*1, *3 On-chip I/O registers External address space/ reserved area*1, *3 On-chip I/O registers External address space H'FF0000 H'FF2000 Access prohibited area On-chip RAM/ external address space*2 External address space H'FFEA00 H'FFFF00 H'FFFF20 H'FFFFFF On-chip I/O registers External address space On-chip I/O registers H'FFEA00 H'FFFF00 H'FFFF20 H'FFFFFF H'FF0000 H'FF2000 External address space Access prohibited area On-chip RAM/ external address space*2 External address space On-chip I/O registers External address space On-chip I/O registers H'FFEA00 H'FFFF00 H'FFFF20 H'FFFFFF H'FF0000 H'FF2000 H'FFC000 H'FFC000 H'FFC000 Notes: 1. This area is specified as the external address space when EXPE = 1 and the reserved area when EXPE = 0. 2. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0. 3. Do not access the reserved areas. Figure 3.1 Address Map in Each Operating Mode of H8SX/1663 (2) Rev.1.00 Jun. 07, 2006 Page 74 of 1102 REJ09B0294-0100 Section 3 MCU Operating Modes Mode 2 Boot mode (Advanced mode) H'000000 On-chip ROM H'000000 Mode 4 On-chip ROM disabled extended mode (Advanced mode) H'080000 External address space External address space/ reserved area*1, *3 H'FD9000 H'FDC000 Access prohibited area External address space/ reserved area*1, *3 H'FD9000 H'FDC000 Access prohibited area External address space H'FF0000 H'FF2000 Access prohibited area On-chip RAM/ external address space*4 External address space H'FFEA00 H'FFFF00 H'FFFF20 H'FFFFFF On-chip I/O registers External address space On-chip I/O registers H'FF0000 H'FF2000 Access prohibited area On-chip RAM*2 H'FFC000 External address space/ reserved area*1, *3 H'FFEA00 On-chip I/O registers H'FFC000 H'FFFF00 External address space/ reserved area*1, *3 H'FFFF20 On-chip I/O registers H'FFFFFF Notes: 1. 2. 3. 4. This area is specified as the external address space when EXPE = 1 and the reserved area when EXPE = 0. The on-chip RAM is used for flash memory programming. Do not clear the RAME bit to 0. Do not access the reserved areas. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0. Figure 3.2 Address Map in Each Operating Mode of H8SX/1664 (1) Rev.1.00 Jun. 07, 2006 Page 75 of 1102 REJ09B0294-0100 Section 3 MCU Operating Modes Mode 5 On-chip ROM disabled extended mode (Advanced mode) H'000000 H'000000 Mode 6 On-chip ROM enabled extended mode (Advanced mode) H'000000 Mode 7 Single-chip mode (Advanced mode) On-chip ROM On-chip ROM H'080000 External address space External address space H'080000 External address space/ reserved area*1, *3 H'FD9000 H'FDC000 Access prohibited area H'FD9000 H'FDC000 Access prohibited area H'FD9000 H'FDC000 Access prohibited area External address space/ reserved area*1, *3 Access prohibited area On-chip RAM/ external address space*2 External address space/ reserved area*1, *3 On-chip I/O registers External address space/ reserved area*1, *3 On-chip I/O registers External address space H'FF0000 H'FF2000 Access prohibited area On-chip RAM/ external address space*2 External address space H'FFEA00 H'FFFF00 H'FFFF20 H'FFFFFF On-chip I/O registers External address space On-chip I/O registers H'FFEA00 H'FFFF00 H'FFFF20 H'FFFFFF H'FF0000 H'FF2000 External address space Access prohibited area On-chip RAM/ external address space*2 External address space On-chip I/O registers External address space On-chip I/O registers H'FFEA00 H'FFFF00 H'FFFF20 H'FFFFFF H'FF0000 H'FF2000 H'FFC000 H'FFC000 H'FFC000 Notes: 1. This area is specified as the external address space when EXPE = 1 and the reserved area when EXPE = 0. 2. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0. 3. Do not access the reserved areas. Figure 3.2 Address Map in Each Operating Mode of H8SX/1664 (2) Rev.1.00 Jun. 07, 2006 Page 76 of 1102 REJ09B0294-0100 Section 4 Exception Handling Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling is caused by a reset, a trace, an address error, an interrupt, a trap instruction, a sleep instruction, and an illegal instruction (general illegal instruction or slot illegal instruction). Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Exception sources, the stack structure, and operation of the CPU vary depending on the interrupt control mode. For details on the interrupt control mode, see section 5, Interrupt Controller. Table 4.1 Priority High Exception Types and Priority Exception Type Reset Exception Handling Start Timing Exception handling starts at the timing of level change from low to high on the RES pin, or when the watchdog timer overflows. The CPU enters the reset state when the RES pin is low. Exception handling starts when an undefined code is executed. Exception handling starts after execution of the current instruction or exception handling, if the trace (T) bit in EXR is set to 1. After an address error has occurred, exception handling starts on completion of instruction execution. Exception handling starts after execution of the current instruction or exception handling, if an interrupt request has 2 occurred.* Exception handling starts by execution of a sleep instruction (SLEEP), if the SSBY bit in SBYCR is set to 0 and the SLPIE bit in SBYCR is set to 1. Exception handling starts by execution of a trap instruction (TRAPA). Illegal instruction Trace* 1 Address error Interrupt Sleep instruction Trap instruction* Low 3 Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not executed after execution of an RTE instruction. 2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC instruction execution, or on completion of reset exception handling. 3. Trap instruction exception handling requests and sleep instruction exception handling requests are accepted at all times in program execution state. Rev.1.00 Jun. 07, 2006 Page 77 of 1102 REJ09B0294-0100 Section 4 Exception Handling 4.2 Exception Sources and Exception Handling Vector Table Different vector table address offsets are assigned to different exception sources. The vector table addresses are calculated from the contents of the vector base register (VBR) and vector table address offset of the vector number. The start address of the exception service routine is fetched from the exception handling vector table indicated by this vector table address. Table 4.2 shows the correspondence between the exception sources and vector table address offsets. Table 4.3 shows the calculation method of exception handling vector table addresses. Table 4.2 Exception Handling Vector Table Vector Table Address Offset* Exception Source Reset Reserved for system use Vector Number 0 1 2 3 Illegal instruction Trace Reserved for system use Interrupt (NMI) Trap instruction (#0) (#1) (#2) (#3) CPU address error DMA address error* 3 1 Normal Mode* 2 Advanced, Middle* , 2 Maximum* Modes H'0000 to H'0003 H'0004 to H'0007 H'0008 to H'000B H'000C to H'000F H'0010 to H'0013 H'0014 to H'0017 H'0018 to H'001B H'001C to H'001F H'0020 to H'0023 H'0024 to H'0027 H'0028 to H'002B H'002C to H'002F H'0030 to H'0033 H'0034 to H'0037 H'0038 to H'003B H'0044 to H'0047 H'0048 to H'004B 2 H'0000 to H'0001 H'0002 to H'0003 H'0004 to H'0005 H'0006 to H'0007 H'0008 to H'0009 H'000A to H'000B H'000C to H'000D H'000E to H'000F H'0010 to H'0011 H'0012 to H'0013 H'0014 to H'0015 H'0016 to H'0017 H'0018 to H'0019 H'001A to H'001B H'001C to H'001D H'0022 to H'0023 H'0024 to H'0025 4 5 6 7 8 9 10 11 12 13 14 17 18 Reserved for system use Sleep interrupt Rev.1.00 Jun. 07, 2006 Page 78 of 1102 REJ09B0294-0100 Section 4 Exception Handling Vector Table Address Offset* Exception Source Reserved for system use Vector Number 19 23 24 63 64 65 66 67 68 69 70 71 72 73 74 75 76 79 80 255 Normal Mode* 2 1 Advanced, Middle* , 2 Maximum* Modes H'004C to H'004F H'005C to H'005F H'0060 to H'0063 H'00FC to H'00FF H'0100 to H'0103 H'0104 to H'0107 H'0108 to H'010B H'010C to H'010F H'0110 to H'0113 H'0114 to H'0117 H'0118 to H'011B H'011C to H'011F H'0120 to H'0123 H'0124 to H'0127 H'0128 to H'012B H'012C to H'012F H'0130 to H'0133 H'013C to H'013F H'0140 to H'0143 H'03FC to H'03FF 2 H'0026 to H'0027 H'002E to H'002F H'0030 to H'0031 H'007E to H'007F H'0080 to H'0081 H'0082 to H'0083 H'0084 to H'0085 H'0086 to H'0087 H'0088 to H'0089 H'008A to H'008B H'008C to H'008D H'008E to H'008F H'0090 to H'0091 H'0092 to H'0093 H'0094 to H'0095 H'0096 to H'0097 H'0098 to H'0099 H'009E to H'009F H'00A0 to H'00A1 H'01FE to H'01FF User area (not used) External interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 Reserved for system use Internal interrupt* 4 Notes: 1. 2. 3. 4. Lower 16 bits of the address. Not available in this LSI. A DMA address error is generated by the DTC and DMAC. For details of internal interrupt vectors, see section 5.5, Interrupt Exception Handling Vector Table. Rev.1.00 Jun. 07, 2006 Page 79 of 1102 REJ09B0294-0100 Section 4 Exception Handling Table 4.3 Calculation Method of Exception Handling Vector Table Address Calculation Method of Vector Table Address Vector table address = (vector table address offset) Vector table address = VBR + (vector table address offset) Exception Source Reset, CPU address error Other than above [Legend] VBR: Vector base register Vector table address offset: See table 4.2. 4.3 Reset A reset has priority over any other exception. When the RES pin goes low, all processing halts and this LSI enters the reset state. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms with the STBY pin driven high when the power is turned on. When operation is in progress, hold the RES pin low for at least 20 cycles. The chip can also be reset by overflow of the watchdog timer. For details, see section 14, Watchdog Timer (WDT). A reset initializes the internal state of the CPU and the registers of the on-chip peripheral modules. The interrupt control mode is 0 immediately after a reset. 4.3.1 Reset Exception Handling When the RES pin goes high after being held low for the necessary time, this LSI starts reset exception handling as follows: 1. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized, VBR is cleared to H'00000000, the T bit is cleared to 0 in EXR, and the I bits are set to 1 in EXR and CCR. 2. The reset exception handling vector address is read and transferred to the PC, and program execution starts from the address indicated by the PC. Figures 4.1 and 4.2 show examples of the reset sequence. Rev.1.00 Jun. 07, 2006 Page 80 of 1102 REJ09B0294-0100 Section 4 Exception Handling 4.3.2 Interrupts after Reset If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.L #xx: 32, SP). 4.3.3 On-Chip Peripheral Functions after Reset Release After the reset state is released, MSTPCRA and MSTPCRB are initialized to H'0FFF and H'FFFF, respectively, and all modules except the DTC and DMAC enter the module stop state. Consequently, on-chip peripheral module registers cannot be read or written to. Register reading and writing is enabled when the module stop state is canceled. First instruction prefetch Vector fetch Internal operation I RES Internal address bus (1) (3) Internal read signal Internal write signal Internal data bus (2) High (4) (1): Reset exception handling vector address (when reset, (1) = H'000000) (2): Start address (contents of reset exception handling vector address) (3) Start address ((3) = (2)) (4) First instruction in the exception handling routine Figure 4.1 Reset Sequence (On-chip ROM Enabled Advanced Mode) Rev.1.00 Jun. 07, 2006 Page 81 of 1102 REJ09B0294-0100 Section 4 Exception Handling Vector fetch Internal First instruction operation prefetch * B * * RES Address bus (1) (3) (5) RD HWR, LWR High D15 to D0 (2) (4) (6) (1)(3) Reset exception handling vector address (when reset, (1) = H'000000, (3) = H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ((5) = (2)(4)) (6) First instruction in the exception handling routine Note: * Seven program wait cycles are inserted. Figure 4.2 Reset Sequence (16-Bit External Access in On-chip ROM Disabled Advanced Mode) Rev.1.00 Jun. 07, 2006 Page 82 of 1102 REJ09B0294-0100 Section 4 Exception Handling 4.4 Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. Before changing interrupt control modes, the T bit must be cleared. For details on interrupt control modes, see section 5, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction. Trace mode is not affected by interrupt masking by CCR. Table 4.4 shows the state of CCR and EXR after execution of trace exception handling. Trace mode is canceled by clearing the T bit in EXR to 0 during the trace exception handling. However, the T bit saved on the stack retains its value of 1, and when control is returned from the trace exception handling routine by the RTE instruction, trace mode resumes. Trace exception handling is not carried out after execution of the RTE instruction. Interrupts are accepted even within the trace exception handling routine. Table 4.4 Status of CCR and EXR after Trace Exception Handling CCR Interrupt Control Mode 0 2 I UI T EXR I2 to I0 Trace exception handling cannot be used. 1 0 [Legend] 1: Set to 1 0: Cleared to 0 : Retains the previous value. Rev.1.00 Jun. 07, 2006 Page 83 of 1102 REJ09B0294-0100 Section 4 Exception Handling 4.5 4.5.1 Address Error Address Error Source Instruction fetch, stack operation, or data read/write shown in table 4.5 may cause an address error. Table 4.5 Bus Cycle and Address Error Bus Cycle Type Instruction fetch Bus Master CPU Description Fetches instructions from even addresses Fetches instructions from odd addresses Fetches instructions from areas other than on-chip peripheral module space*1 Fetches instructions from on-chip peripheral module space*1 Fetches instructions from external memory space in single-chip mode Fetches instructions from access prohibited area.*2 Stack operation CPU Accesses stack when the stack pointer value is even address Accesses stack when the stack pointer value is odd Data read/write CPU Accesses word data from even addresses Accesses word data from odd addresses Accesses external memory space in single-chip mode Accesses to access prohibited area*2 Data read/write DTC or DMAC Accesses word data from even addresses Accesses word data from odd addresses Accesses external memory space in single-chip mode Accesses to access prohibited area*2 Single address transfer DMAC Address Error No (normal) Occurs No (normal) Occurs Occurs Occurs No (normal) Occurs No (normal) No (normal) Occurs Occurs No (normal) No (normal) Occurs Occurs Address access space is the external memory space for No (normal) single address transfer Address access space is not the external memory space Occurs for single address transfer Notes: 1. For on-chip peripheral module space, see section 6, Bus Controller (BSC). 2. For the access prohibited area, refer to figure 3.1 in section 3.4, Address Map. Rev.1.00 Jun. 07, 2006 Page 84 of 1102 REJ09B0294-0100 Section 4 Exception Handling 4.5.2 Address Error Exception Handling When an address error occurs, address error exception handling starts after the bus cycle causing the address error ends and current instruction execution completes. The address error exception handling is as follows: 1. The contents of PC, CCR, and EXR are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. An exception handling vector table address corresponding to the address error is generated, the start address of the exception service routine is loaded from the vector table to PC, and program execution starts from that address. Even though an address error occurs during a transition to an address error exception handling, the address error is not accepted. This prevents an address error from occurring due to stacking for exception handling, thereby preventing infinitive stacking. If the SP contents are not a multiple of 2 when an address error exception handling occurs, the stacked values (PC, CCR, and EXR) are undefined. When an address error occurs, the following is performed to halt the DTC and DMAC. * The ERR bit of DTCCR in the DTC is set to 1. * The ERRF bit of DMDR_0 in the DMAC is set to 1. * The DTE bits of DMDRs for all channels in the DMAC are cleared to 0 to forcibly terminate transfer. Table 4.6 shows the state of CCR and EXR after execution of the address error exception handling. Table 4.6 Status of CCR and EXR after Address Error Exception Handling CCR Interrupt Control Mode 0 2 I 1 1 UI T 0 EXR I2 to I0 7 [Legend] 1: Set to 1 0: Cleared to 0 : Retains the previous value. Rev.1.00 Jun. 07, 2006 Page 85 of 1102 REJ09B0294-0100 Section 4 Exception Handling 4.6 4.6.1 Interrupts Interrupt Sources Interrupt sources are NMI, IRQ0 to IRQ11, and on-chip peripheral modules, as shown in table 4.7. Table 4.7 Type NMI IRQ0 to IRQ11 On-chip peripheral module Interrupt Sources Source NMI pin (external input) Pins IRQ0 to IRQ11 (external input) DMA controller (DMAC) Watchdog timer (WDT) A/D converter 16-bit timer pulse unit (TPU) 8-bit timer (TMR) Serial communications interface (SCI) I C bus interface 2 (IIC2) USB function module (USB) 2 Number of Sources 1 12 8 1 1 26 16 24 2 5 Different vector numbers and vector table offsets are assigned to different interrupt sources. For vector number and vector table offset, refer to table 5.2, Interrupt Sources, Vector Address Offsets, and Interrupt Priority in section 5, Interrupt Controller. Rev.1.00 Jun. 07, 2006 Page 86 of 1102 REJ09B0294-0100 Section 4 Exception Handling 4.6.2 Interrupt Exception Handling Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt control modes and can assign interrupts other than NMI to eight priority/mask levels to enable multiple-interrupt control. The source to start interrupt exception handling and the vector address differ depending on the product. For details, refer to section 5, Interrupt Controller. The interrupt exception handling is as follows: 1. The contents of PC, CCR, and EXR are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. An exception handling vector table address corresponding to the interrupt source is generated, the start address of the exception service routine is loaded from the vector table to PC, and program execution starts from that address. 4.7 Instruction Exception Handling There are three instructions that cause exception handling: trap instruction, sleep instruction, and illegal instruction. 4.7.1 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The trap instruction exception handling is as follows: 1. The contents of PC, CCR, and EXR are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. An exception handling vector table address corresponding to the vector number specified in the TRAPA instruction is generated, the start address of the exception service routine is loaded from the vector table to PC, and program execution starts from that address. A start address is read from the vector table corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 4.8 shows the state of CCR and EXR after execution of trap instruction exception handling. Rev.1.00 Jun. 07, 2006 Page 87 of 1102 REJ09B0294-0100 Section 4 Exception Handling Table 4.8 Status of CCR and EXR after Trap Instruction Exception Handling CCR EXR T 0 I2 to I0 Interrupt Control Mode 0 2 I 1 1 UI [Legend] 1: Set to 1 0: Cleared to 0 : Retains the previous value. 4.7.2 Sleep Instruction Exception Handling The sleep instruction exception handling starts when a sleep instruction is executed with the SSBY bit in SBYCR set to 0 and the SLPIE bit in SBYCR set to 1. The sleep instruction exception handling can always be executed in the program execution state. In the exception handling, the CPU operates as follows. 1. The contents of PC, CCR, and EXR are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. An exception handling vector table address corresponding to the vector number specified in the SLEEP instruction is generated, the start address of the exception service routine is loaded from the vector table to PC, and program execution starts from that address. Bus masters other than the CPU may gain the bus mastership after a sleep instruction has been executed. In such cases the sleep instruction will be started when the transactions of a bus master other than the CPU has been completed and the CPU has gained the bus mastership. Table 4.9 shows the state of CCR and EXR after execution of sleep instruction exception handling. Rev.1.00 Jun. 07, 2006 Page 88 of 1102 REJ09B0294-0100 Section 4 Exception Handling Table 4.9 Status of CCR and EXR after Sleep Instruction Exception Handling CCR EXR T 0 I2 to I0 7 Interrupt Control Mode 0 2 I 1 1 UI [Legend] 1: Set to 1 0: Cleared to 0 : Retains the previous value. 4.7.3 Exception Handling by Illegal Instruction The illegal instructions are general illegal instructions and slot illegal instructions. The exception handling by the general illegal instruction starts when an undefined code is executed. The exception handling by the slot illegal instruction starts when a particular instruction (e.g. its code length is two words or more, or it changes the PC contents) at a delay slot (immediately after a delayed branch instruction) is executed. The exception handling by the general illegal instruction and slot illegal instruction is always executable in the program execution state. The exception handling is as follows: 1. The contents of PC, CCR, and EXR are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. An exception handling vector table address corresponding to the occurred exception is generated, the start address of the exception service routine is loaded from the vector table to PC, and program execution starts from that address. Table 4.10 shows the state of CCR and EXR after execution of illegal instruction exception handling. Rev.1.00 Jun. 07, 2006 Page 89 of 1102 REJ09B0294-0100 Section 4 Exception Handling Table 4.10 Status of CCR and EXR after Illegal Instruction Exception Handling CCR Interrupt Control Mode 0 2 I 1 1 UI T 0 EXR I2 to I0 [Legend] 1: Set to 1 0: Cleared to 0 : Retains the previous value. 4.8 Stack Status after Exception Handling Figure 4.3 shows the stack after completion of exception handling. Advanced mode SP EXR Reserved* SP CCR PC (24 bits) CCR PC (24 bits) Interrupt control mode 0 Interrupt control mode 2 Note: * Ignored on return. Figure 4.3 Stack Status after Exception Handling Rev.1.00 Jun. 07, 2006 Page 90 of 1102 REJ09B0294-0100 Section 4 Exception Handling 4.9 Usage Note When performing stack-manipulating access, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by a word transfer instruction or a longword transfer instruction, and the value of the stack pointer (SP: ER7) should always be kept even. Use the following instructions to save registers: PUSH.W PUSH.L Rn ERn (or MOV.W Rn, @-SP) (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.W POP.L Rn ERn (or MOV.W @SP+, Rn) (or MOV.L @SP+, ERn) Performing stack manipulation while SP is set to an odd value leads to an address error. Figure 4.4 shows an example of operation when the SP value is odd. Address CCR SP PC SP R1L H'FFFEFA H'FFFEFB PC H'FFFEFC H'FFFEFD H'FFFEFE SP H'FFFEFF TRAPA instruction executed SP set to H'FFFEFF MOV.B R1L, @-ER7 executed Contents of CCR lost Data saved above SP (Address error occurred) [Legend] CCR : PC : R1L : SP : Condition code register Program counter General register R1L Stack pointer Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced mode. Figure 4.4 Operation when SP Value is Odd Rev.1.00 Jun. 07, 2006 Page 91 of 1102 REJ09B0294-0100 Section 4 Exception Handling Rev.1.00 Jun. 07, 2006 Page 92 of 1102 REJ09B0294-0100 Section 5 Interrupt Controller Section 5 Interrupt Controller 5.1 Features * Two interrupt control modes Any of two interrupt control modes can be set by means of bits INTM1 and INTM0 in the interrupt control register (INTCR). * Priority can be assigned by the interrupt priority register (IPR) IPR provides for setting interrupt priory. Eight levels can be set for each module for all interrupts except for the interrupt requests listed below. The following seven interrupt requests are given priority of 8, therefore they are accepted at all times. NMI Illegal instructions Trace Trap instructions CPU address error DMA address error (occurred in the DTC and DMAC) Sleep instruction * Independent vector addresses All interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. * Thirteen external interrupts NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge detection can be selected for NMI. Falling edge, rising edge, or both edge detection, or level sensing, can be selected for IRQ11 to IRQ0. * DTC and DMAC control DTC and DMAC can be activated by means of interrupts. * CPU priority control function The priority levels can be assigned to the CPU, DTC, and DMAC. The priority level of the CPU can be automatically assigned on an exception generation. Priority can be given to the CPU interrupt exception handling over that of the DTC and DMAC transfer. Rev.1.00 Jun. 07, 2006 Page 93 of 1102 REJ09B0294-0100 Section 5 Interrupt Controller A block diagram of the interrupt controller is shown in figure 5.1. INTM1, INTM0 INTCR NMIEG IPR I I2 to I0 NMI input IRQ11 to HRQ0 input TM32K IRQ input unit IRQ15 input ISCR IER SSIER DMAC activation permission CPU interrupt request CPU vector Priority determination CPU CCR EXR NMI input unit ISR DMAC DMAC priority control DMDR Internal interrupt sources WOVI to RESUME Source selector CPU priority DTC activation request DTCER DTCCR CPUPCR DTC priority Interrupt controller [Legend] INTCR: Interrupt control register CPUPCR: CPU priority control register IRQ sense control register ISCR: IRQ enable register IER: IRQ status register ISR: SSIER: IPR: DTCER: DTCCR: Software standby release IRQ enable register Interrupt priority register DTC enable register DTC control register DTC priority control DTC vector Activation request clear signal DTC Figure 5.1 Block Diagram of Interrupt Controller Rev.1.00 Jun. 07, 2006 Page 94 of 1102 REJ09B0294-0100 Section 5 Interrupt Controller 5.2 Input/Output Pins Table 5.1 shows the pin configuration of the interrupt controller. Table 5.1 Name NMI IRQ11 to IRQ0 Pin Configuration I/O Input Input Function Nonmaskable External Interrupt Rising or falling edge can be selected. Maskable External Interrupts Rising, falling, or both edges, or level sensing, can be independently selected. 5.3 Register Descriptions The interrupt controller has the following registers. * Interrupt control register (INTCR) * CPU priority control register (CPUPCR) * Interrupt priority registers A to C, E to I, K, L, Q, and R (IPRA to IPRC, IPRE to IPRI, IPRK, IPRL, IPRQ, and IPRR) * IRQ enable register (IER) * IRQ sense control registers H and L (ISCRH, ISCRL) * IRQ status register (ISR) * Software standby release IRQ enable register (SSIER) Rev.1.00 Jun. 07, 2006 Page 95 of 1102 REJ09B0294-0100 Section 5 Interrupt Controller 5.3.1 Interrupt Control Register (INTCR) INTCR selects the interrupt control mode, and the detected edge for NMI. Bit Bit Name Initial Value R/W 7 0 R 6 0 R 5 INTM1 0 R/W 4 INTM0 0 R/W 3 NMIEG 0 R/W 2 0 R 1 0 R 0 0 R Bit 7 6 5 4 Bit Name INTM1 INTM0 Initial Value 0 0 0 0 R/W R R R/W R/W Description Reserved These are read-only bits and cannot be modified. Interrupt Control Select Mode 1 and 0 These bits select either of two interrupt control modes for the interrupt controller. 00: Interrupt control mode 0 Interrupts are controlled by I bit in CCR. 01: Setting prohibited. 10: Interrupt control mode 2 Interrupts are controlled by bits I2 to I0 in EXR, and IPR. 11: Setting prohibited. 3 NMIEG 0 R/W NMI Edge Select Selects the input edge for the NMI pin. 0: Interrupt request generated at falling edge of NMI input 1: Interrupt request generated at rising edge of NMI input 2 to 0 All 0 R Reserved These are read-only bits and cannot be modified. Rev.1.00 Jun. 07, 2006 Page 96 of 1102 REJ09B0294-0100 Section 5 Interrupt Controller 5.3.2 CPU Priority Control Register (CPUPCR) CPUPCR sets whether or not the CPU has priority over the DTC and DMAC. The interrupt exception handling by the CPU can be given priority over that of the DTC and DMAC transfer. The priority level of the DTC is set by bits DTCP2 to DTCP0 in CPUPCR. The priority level of the DMAC is set by the DMAC control register for each channel. Bit Bit Name Initial Value R/W 7 CPUPCE 0 R/W 6 DTCP2 0 R/W 5 DTCP1 0 R/W 4 DTCP0 0 R/W 3 IPSETE 0 R/W 2 CPUP2 0 R/(W)* 1 CPUP1 0 R/(W)* 0 CPUP0 0 R/(W)* Note: * When the IPSETE bit is set to 1, the CPU priority is automatically updated, so these bits cannot be modified. Bit 7 Bit Name CPUPCE Initial Value 0 R/W R/W Description CPU Priority Control Enable Controls the CPU priority control function. Setting this bit to 1 enables the CPU priority control over the DTC and DMAC. 0: CPU always has the lowest priority 1: CPU priority control enabled DTC Priority Level 2 to 0 These bits set the DTC priority level. 000: Priority level 0 (lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (highest) Interrupt Priority Set Enable Controls the function which automatically assigns the interrupt priority level of the CPU. Setting this bit to 1 automatically sets bits CPUP2 to CPUP0 by the CPU interrupt mask bit (I bit in CCR or bits I2 to I0 in EXR). 0: Bits CPUP2 to CPUP0 are not updated automatically 1: The interrupt mask bit value is reflected in bits CPUP2 to CPUP0 6 5 4 DTCP2 DTCP1 DTCP0 0 0 0 R/W R/W R/W 3 IPSETE 0 R/W Rev.1.00 Jun. 07, 2006 Page 97 of 1102 REJ09B0294-0100 Section 5 Interrupt Controller Bit 2 1 0 Bit Name CPUP2 CPUP1 CPUP0 Initial Value 0 0 0 R/W R/(W)* R/(W)* R/(W)* Description CPU Priority Level 2 to 0 These bits set the CPU priority level. When the CPUPCE is set to 1, the CPU priority control function over the DTC and DMAC becomes valid and the priority of CPU processing is assigned in accordance with the settings of bits CPUP2 to CPUP0. 000: Priority level 0 (lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (highest) Note: * When the IPSETE bit is set to 1, the CPU priority is automatically updated, so these bits cannot be modified. 5.3.3 Interrupt Priority Registers A to I, K, L, Q, and R (IPRA to IPRI, IPRK, IPRL, IPRQ, and IPRR) IPR sets priory (levels 7 to 0) for interrupts other than NMI. Setting a value in the range from B'000 to B'111 in the 3-bit groups of bits 14 to 12, 10 to 8, 6 to 4, and 2 to 0 assigns a priority level to the corresponding interrupt. For the correspondence between the interrupt sources and the IPR settings, see table 5.2. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 0 R 7 0 R 14 IPR14 1 R/W 6 IPR6 1 R/W 13 IPR13 1 R/W 5 IPR5 1 R/W 12 IPR12 1 R/W 4 IPR4 1 R/W 11 0 R 3 0 R 10 IPR10 1 R/W 2 IPR2 1 R/W 9 IPR9 1 R/W 1 IPR1 1 R/W 8 IPR8 1 R/W 0 IPR0 1 R/W Rev.1.00 Jun. 07, 2006 Page 98 of 1102 REJ09B0294-0100 Section 5 Interrupt Controller Bit 15 14 13 12 Bit Name IPR14 IPR13 IPR12 Initial Value 0 1 1 1 R/W R R/W R/W R/W Description Reserved This is a read-only bit and cannot be modified. Sets the priority level of the corresponding interrupt source. 000: Priority level 0 (lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (highest) Reserved This is a read-only bit and cannot be modified. Sets the priority level of the corresponding interrupt source. 000: Priority level 0 (lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (highest) Reserved This is a read-only bit and cannot be modified. Sets the priority level of the corresponding interrupt source. 000: Priority level 0 (lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (highest) 11 10 9 8 IPR10 IPR9 IPR8 0 1 1 1 R R/W R/W R/W 7 6 5 4 IPR6 IPR5 IPR4 0 1 1 1 R R/W R/W R/W Rev.1.00 Jun. 07, 2006 Page 99 of 1102 REJ09B0294-0100 Section 5 Interrupt Controller Bit 3 2 1 0 Bit Name IPR2 IPR1 IPR0 Initial Value 0 1 1 1 R/W R R/W R/W R/W Description Reserved This is a read-only bit and cannot be modified. Sets the priority level of the corresponding interrupt source. 000: Priority level 0 (lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (highest) 5.3.4 IRQ Enable Register (IER) IER enables interrupt requests IRQ15, and IRQ11 to IRQ0. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 IRQ15E 0 R/W 7 IRQ7E 0 R/W 14 0 R/W 6 IRQ6E 0 R/W 13 0 R/W 5 IRQ5E 0 R/W 12 0 R/W 4 IRQ4E 0 R/W 11 IRQ11E 0 R/W 3 IRQ3E 0 R/W 10 IRQ10E 0 R/W 2 IRQ2E 0 R/W 9 IRQ9E 0 R/W 1 IRQ1E 0 R/W 8 IRQ8E 0 R/W 0 IRQ0E 0 R/W Bit 15 Bit Name IRQ15E Initial Value 0 R/W R/W Description IRQ15 Enable The IRQ15 interrupt request is enabled when this bit is 1. IRQ15 is internally connected to the 32KOVI interrupt in the TM32K. Reserved These bits are always read as 0. The write value should always be 0. 14 to 12 All 0 R/W Rev.1.00 Jun. 07, 2006 Page 100 of 1102 REJ09B0294-0100 Section 5 Interrupt Controller Bit 11 Bit Name IRQ11E Initial Value 0 R/W R/W Description IRQ11 Enable The IRQ11 interrupt request is enabled when this bit is 1. 10 IRQ10E 0 R/W IRQ10 Enable The IRQ10 interrupt request is enabled when this bit is 1. 9 8 7 6 5 4 3 2 1 0 IRQ9E IRQ8E IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W IRQ9 Enable The IRQ9 interrupt request is enabled when this bit is 1. IRQ8 Enable The IRQ8 interrupt request is enabled when this bit is 1. IRQ7 Enable The IRQ7 interrupt request is enabled when this bit is 1. IRQ6 Enable The IRQ6 interrupt request is enabled when this bit is 1. IRQ5 Enable The IRQ5 interrupt request is enabled when this bit is 1. IRQ4 Enable The IRQ4 interrupt request is enabled when this bit is 1. IRQ3 Enable The IRQ3 interrupt request is enabled when this bit is 1. IRQ2 Enable The IRQ2 interrupt request is enabled when this bit is 1. IRQ1 Enable The IRQ1 interrupt request is enabled when this bit is 1. IRQ0 Enable The IRQ0 interrupt request is enabled when this bit is 1. Rev.1.00 Jun. 07, 2006 Page 101 of 1102 REJ09B0294-0100 Section 5 Interrupt Controller 5.3.5 IRQ Sense Control Registers H and L (ISCRH, ISCRL) ISCRH and ISCRL select the source that generates an interrupt request from IRQ15, and IRQ11 to IRQ0 input. Upon changing the setting of ISCR, IRQnF (n = 0 to 11, and 15) in ISR is often set to 1 accidentally through an internal operation. In this case, an interrupt exception handling is executed if an IRQn interrupt request is enabled. In order to prevent such an accidental interrupt from occurring, the setting of ISCR should be changed while the IRQn interrupt is disabled, and then the IRQnF in ISR should be cleared to 0. * ISCRH Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 IRQ15SR 0 R/W 7 IRQ11SR 0 R/W 14 IRQ15SF 0 R/W 6 IRQ11SF 0 R/W 13 0 R/W 5 IRQ10SR 0 R/W 12 0 R/W 4 IRQ10SF 0 R/W 11 0 R/W 3 IRQ9SR 0 R/W 10 0 R/W 2 IRQ9SF 0 R/W 9 0 R/W 1 IRQ8SR 0 R/W 8 0 R/W 0 IRQ8SF 0 R/W * ISCRL Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 IRQ7SR 0 R/W 7 IRQ3SR 0 R/W 14 IRQ7SF 0 R/W 6 IRQ3SF 0 R/W 13 IRQ6SR 0 R/W 5 IRQ2SR 0 R/W 12 IRQ6SF 0 R/W 4 IRQ2SF 0 R/W 11 IRQ5SR 0 R/W 3 IRQ1SR 0 R/W 10 IRQ5SF 0 R/W 2 IRQ1SF 0 R/W 9 IRQ4SR 0 R/W 1 IRQ0SR 0 R/W 8 IRQ4SF 0 R/W 0 IRQ0SF 0 R/W Rev.1.00 Jun. 07, 2006 Page 102 of 1102 REJ09B0294-0100 Section 5 Interrupt Controller * ISCRH Bit 15 14 Bit Name IRQ15SR IRQ15SF Initial Value 0 0 R/W R/W R/W Description IRQ15 Sense Control Rise IRQ15 Sense Control Fall IRQ15 is used as the 32KOVI interrupt in the TM32K. IRQ15 is generated at falling edge of IRQ15. 00: Initial setting 01: Interrupt request generated at falling edge of IRQ15 10: Setting prohibited 11: Setting prohibited 13 to 8 All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. 7 6 IRQ11SR IRQ11SF 0 0 R/W R/W IRQ11 Sense Control Rise IRQ11 Sense Control Fall 00: Interrupt request generated by low level of IRQ11 01: Interrupt request generated at falling edge of IRQ11 10: Interrupt request generated at rising edge of IRQ11 11: Interrupt request generated at both falling and rising edges of IRQ11 5 4 IRQ10SR IRQ10SF 0 0 R/W R/W IRQ10 Sense Control Rise IRQ10 Sense Control Fall 00: Interrupt request generated by low level of IRQ10 01: Interrupt request generated at falling edge of IRQ10 10: Interrupt request generated at rising edge of IRQ10 11: Interrupt request generated at both falling and rising edges of IRQ10 3 2 IRQ9SR IRQ9SF 0 0 R/W R/W IRQ9 Sense Control Rise IRQ9 Sense Control Fall 00: Interrupt request generated by low level of IRQ9 01: Interrupt request generated at falling edge of IRQ9 10: Interrupt request generated at rising edge of IRQ9 11: Interrupt request generated at both falling and rising edges of IRQ9 Rev.1.00 Jun. 07, 2006 Page 103 of 1102 REJ09B0294-0100 Section 5 Interrupt Controller Bit 1 0 Bit Name IRQ8SR IRQ8SF Initial Value 0 0 R/W R/W R/W Description IRQ8 Sense Control Rise IRQ8 Sense Control Fall 00: Interrupt request generated by low level of IRQ8 01: Interrupt request generated at falling edge of IRQ8 10: Interrupt request generated at rising edge of IRQ8 11: Interrupt request generated at both falling and rising edges of IRQ8 * ISCRL Bit 15 14 Bit Name IRQ7SR IRQ7SF Initial Value 0 0 R/W R/W R/W Description IRQ7 Sense Control Rise IRQ7 Sense Control Fall 00: Interrupt request generated by low level of IRQ7 01: Interrupt request generated at falling edge of IRQ7 10: Interrupt request generated at rising edge of IRQ7 11: Interrupt request generated at both falling and rising edges of IRQ7 13 12 IRQ6SR IRQ6SF 0 0 R/W R/W IRQ6 Sense Control Rise IRQ6 Sense Control Fall 00: Interrupt request generated by low level of IRQ6 01: Interrupt request generated at falling edge of IRQ6 10: Interrupt request generated at rising edge of IRQ6 11: Interrupt request generated at both falling and rising edges of IRQ6 11 10 IRQ5SR IRQ5SF 0 0 R/W R/W IRQ5 Sense Control Rise IRQ5 Sense Control Fall 00: Interrupt request generated by low level of IRQ5 01: Interrupt request generated at falling edge of IRQ5 10: Interrupt request generated at rising edge of IRQ5 11: Interrupt request generated at both falling and rising edges of IRQ5 Rev.1.00 Jun. 07, 2006 Page 104 of 1102 REJ09B0294-0100 Section 5 Interrupt Controller Bit 9 8 Bit Name IRQ4SR IRQ4SF Initial Value 0 0 R/W R/W R/W Description IRQ4 Sense Control Rise IRQ4 Sense Control Fall 00: Interrupt request generated by low level of IRQ4 01: Interrupt request generated at falling edge of IRQ4 10: Interrupt request generated at rising edge of IRQ4 11: Interrupt request generated at both falling and rising edges of IRQ4 7 6 IRQ3SR IRQ3SF 0 0 R/W R/W IRQ3 Sense Control Rise IRQ3 Sense Control Fall 00: Interrupt request generated by low level of IRQ3 01: Interrupt request generated at falling edge of IRQ3 10: Interrupt request generated at rising edge of IRQ3 11: Interrupt request generated at both falling and rising edges of IRQ3 5 4 IRQ2SR IRQ2SF 0 0 R/W R/W IRQ2 Sense Control Rise IRQ2 Sense Control Fall 00: Interrupt request generated by low level of IRQ2 01: Interrupt request generated at falling edge of IRQ2 10: Interrupt request generated at rising edge of IRQ2 11: Interrupt request generated at both falling and rising edges of IRQ2 3 2 IRQ1SR IRQ1SF 0 0 R/W R/W IRQ1 Sense Control Rise IRQ1 Sense Control Fall 00: Interrupt request generated by low level of IRQ1 01: Interrupt request generated at falling edge of IRQ1 10: Interrupt request generated at rising edge of IRQ1 11: Interrupt request generated at both falling and rising edges of IRQ1 1 0 IRQ0SR IRQ0SF 0 0 R/W R/W IRQ0 Sense Control Rise IRQ0 Sense Control Fall 00: Interrupt request generated by low level of IRQ0 01: Interrupt request generated at falling edge of IRQ0 10: Interrupt request generated at rising edge of IRQ0 11: Interrupt request generated at both falling and rising edges of IRQ0 Rev.1.00 Jun. 07, 2006 Page 105 of 1102 REJ09B0294-0100 Section 5 Interrupt Controller 5.3.6 IRQ Status Register (ISR) ISR is an IRQ15, and IRQ11 to IRQ0 interrupt request register. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Note: * 15 IRQ15F 0 R/(W)* 7 IRQ7F 0 R/(W)* 14 0 R/W 6 IRQ6F 0 R/(W)* 13 0 R/W 5 IRQ5F 0 R/(W)* 12 0 R/W 4 IRQ4F 0 R/(W)* 11 IRQ11F 0 R/(W)* 3 IRQ3F 0 R/(W)* 10 IRQ10F 0 R/(W)* 2 IRQ2F 0 R/(W)* 9 IRQ9F 0 R/(W)* 1 IRQ1F 0 R/(W)* 8 IRQ8F 0 R/(W)* 0 IRQ0F 0 R/(W)* Only 0 can be written, to clear the flag. The bit manipulation instructions or memory operation instructions should be used to clear the flag. Bit 15 Bit Name IRQ15F Initial Value 0 R/W R/(W)* Description [Setting condition] * * * When the interrupt selected by ISCR occurs Writing 0 after reading IRQnF = 1 (n = 15) When IRQn interrupt exception handling is executed while falling-edge sensing is selected [Clearing conditions] 14 to 12 All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. Rev.1.00 Jun. 07, 2006 Page 106 of 1102 REJ09B0294-0100 Section 5 Interrupt Controller Bit 11 10 9 8 7 6 5 4 3 2 1 0 Note: * Bit Name IRQ11F IRQ10F IRQ9F IRQ8F IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Description [Setting condition] * * * * When the interrupt selected by ISCR occurs Writing 0 after reading IRQnF = 1 (n = 11 to 0) When interrupt exception handling is executed while low-level sensing is selected and IRQn input is high When IRQn interrupt exception handling is executed while falling-, rising-, or both-edge sensing is selected When the DTC is activated by an IRQn interrupt, and the DISEL bit in MRB of the DTC is cleared to 0 [Clearing conditions] * Only 0 can be written, to clear the flag. 5.3.7 Software Standby Release IRQ Enable Register (SSIER) SSIER selects the IRQ interrupt used to leave software standby mode. The IRQ interrupt used to leave software standby mode should not be set as the DTC activation source. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 SSI15 0 R/W 7 SSI7 0 R/W 14 0 R/W 6 SSI6 0 R/W 13 0 R/W 5 SSI5 0 R/W 12 0 R/W 4 SSI4 0 R/W 11 SSI11 0 R/W 3 SSI3 0 R/W 10 SSI10 0 R/W 2 SSI2 0 R/W 9 SSI9 0 R/W 1 SSI1 0 R/W 8 SSI8 0 R/W 0 SSI0 0 R/W Rev.1.00 Jun. 07, 2006 Page 107 of 1102 REJ09B0294-0100 Section 5 Interrupt Controller Bit 15 Bit Name SSI15 Initial Value 0 R/W R/W Description Software Standby Release IRQ Setting This bit selects the IRQn interrupt used to leave software standby mode (n = 15). 0: An IRQn request is not sampled in software standby mode 1: When an IRQn request occurs in software standby mode, this LSI leaves software standby mode after the oscillation settling time has elapsed 14 to 12 All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. 11 10 9 8 7 6 5 4 3 2 1 0 SSI11 SSI10 SSI9 SSI8 SSI7 SSI6 SSI5 SSI4 SSI3 SSI2 SSI1 SSI0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Software Standby Release IRQ Setting These bits select the IRQn interrupt used to leave software standby mode (n = 11 to 0). 0: An IRQn request is not sampled in software standby mode 1: When an IRQn request occurs in software standby mode, this LSI leaves software standby mode after the oscillation settling time has elapsed Rev.1.00 Jun. 07, 2006 Page 108 of 1102 REJ09B0294-0100 Section 5 Interrupt Controller 5.4 5.4.1 Interrupt Sources External Interrupts There are thirteen external interrupts: NMI and IRQ11 to IRQ0. These interrupts can be used to leave software standby mode. (1) NMI Interrupts Nonmaskable interrupt request (NMI) is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt control mode or the settings of the CPU interrupt mask bits. The NMIEG bit in INTCR selects whether an interrupt is requested at the rising or falling edge on the NMI pin. When an NMI interrupt is generated, the interrupt controller determines that an error has occurred, and performs the following procedure. * Sets the ERR bit of DTCCR in the DTC to 1. * Sets the ERRF bit of DMDR_0 in the DMAC to 1 * Clears the DTE bits of DMDRs for all channels in the DMAC to 0 to forcibly terminate transfer (2) IRQn Interrupts An IRQn interrupt is requested by a signal input on pins IRQ11 to IRQ0. IRQn (n = 11 to 0) have the following features: * Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, on pins IRQn. * Enabling or disabling of interrupt requests IRQn can be selected by IER. * The interrupt priority can be set by IPR. * The status of interrupt requests IRQn is indicated in ISR. ISR flags can be cleared to 0 by software. The bit manipulation instructions and memory operation instructions should be used to clear the flag. Rev.1.00 Jun. 07, 2006 Page 109 of 1102 REJ09B0294-0100 Section 5 Interrupt Controller Detection of IRQn interrupts is enabled through the P1ICR, P2ICR, and P5ICR register settings, and does not change regardless of the output setting. However, when a pin is used as an external interrupt input pin, the pin must not be used as an I/O pin for another function by clearing the corresponding DDR bit to 0. A block diagram of interrupts IRQn is shown in figure 5.2. IRQnE Corresponding bit in ICR IRQnSF, IRQnSR IRQnF Input buffer IRQn input Edge/level detection circuit IRQn interrupt request S R Q [Legend] n = 11 to 0 Clear signal Figure 5.2 Block Diagram of Interrupts IRQn When the IRQ sensing control in ISCR is set to a low level of signal IRQn, the level of IRQn should be held low until an interrupt handling starts. Then set the corresponding input signal IRQn to high in the interrupt handling routine and clear the IRQnF to 0. Interrupts may not be executed when the corresponding input signal IRQn is set to high before the interrupt handling begins. 5.4.2 Internal Interrupts The sources for internal interrupts from on-chip peripheral modules have the following features: * For each on-chip peripheral module there are flags that indicate the interrupt request status, and enable bits that enable or disable these interrupts. They can be controlled independently. When the enable bit is set to 1, an interrupt request is issued to the interrupt controller. * The interrupt priority can be set by means of IPR. * The DTC and DMAC can be activated by a TPU, SCI, or other interrupt request. * The priority levels of DTC and DMAC activation can be controlled by the DTC and DMAC priority control functions. Rev.1.00 Jun. 07, 2006 Page 110 of 1102 REJ09B0294-0100 Section 5 Interrupt Controller 5.5 Interrupt Exception Handling Vector Table Table 5.2 lists interrupt exception handling sources, vector address offsets, and interrupt priority. In the default priority order, a lower vector number corresponds to a higher priority. When interrupt control mode 2 is set, priority levels can be changed by setting the IPR contents. The priority for interrupt sources allocated to the same level in IPR follows the default priority, that is, they are fixed. Table 5.2 Interrupt Sources, Vector Address Offsets, and Interrupt Priority Vector Number Vector Address Offset* DTC Activation DMAC Activation Classification Interrupt Source IPR Priority External pin External pin NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 7 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 H'001C H'0100 H'0104 H'0108 H'010C H'0110 H'0114 H'0118 H'011C H'0120 H'0124 H'0128 H'012C H'0130 H'0134 H'0138 H'013C H'0140 H'0144 IPRA14 to IPRA12 IPRA10 to IPRA8 IPRA6 to IPRA4 IPRA2 to IPRA0 IPRB14 to IPRB12 IPRB10 to IPRB8 IPRB6 to IPRB4 IPRB2 to IPRB0 IPRC14 to IPRC12 IPRC10 to IPRC8 IPRC6 to IPRC4 IPRC2 to IPRC0 High O O O O O O O O O O O O Reserved for system use TM32K WDT 32KOVI (IRQ15) 79 Reserved for system use WOVI 80 81 IPRD2 to IPRD0 IPRE10 to IPRE8 Low Rev.1.00 Jun. 07, 2006 Page 111 of 1102 REJ09B0294-0100 Section 5 Interrupt Controller Vector Address Offset* Classification Interrupt Source Vector Number IPR Priority DTC Activation DMAC Activation Refresh controller Reserved for system use CMI Reserved for system use ADI Reserved for system use TGI0A TGI0B TGI0C TGI0D TCI0V 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 H'0148 H'014C H'0150 H'0154 H'0158 H'015C H'0160 H'0164 H'0168 H'016C H'0170 H'0174 H'0178 H'017C H'0180 H'0184 H'0188 H'018C H'0190 H'0194 H'0198 H'019C H'01A0 H'01A4 H'01A8 H'01AC H'01B0 H'01B4 IPRE2 to IPRE0 High O O O O O O A/D TPU_0 IPRF10 to IPRF8 IPRF6 to IPRF4 O O O O O TPU_1 TGI1A TGI1B TCI1V TCI1U IPRF2 to IPRF0 O O TPU_2 TGI2A TGI2B TCI2V TCI2U IPRG14 to IPRG12 O O TPU_3 TGI3A TGI3B TGI3C TGI3D TCI3V IPRG10 to IPRG8 O O O O TPU_4 TGI4A TGI4B TCI4V TCI4U IPRG6 to IPRG4 O O Low Rev.1.00 Jun. 07, 2006 Page 112 of 1102 REJ09B0294-0100 Section 5 Interrupt Controller Vector Address Offset* Classification Interrupt Source Vector Number IPR Priority DTC Activation DMAC Activation TPU_5 TGI5A TGI5B TCI5V TCI5U 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 H'01B8 H'01BC H'01C0 H'01C4 H'01C8 H'01CC H'01D0 H'01D4 H'01D8 H'01DC H'01E0 H'01E4 H'01E8 H'01EC H'01F0 H'01F4 H'01F8 H'01FC H'0200 H'0204 H'0208 H'020C H'0210 H'0214 H'0218 H'021C H'0220 H'0224 H'0228 H'022C IPRG2 to IPRG0 High O O O Reserved for system use CMI0A CMI0B OV0I TMR_0 IPRH14 to IPRH12 O O TMR_1 CMI1A CMI1B OV1I IPRH10 to IPRH8 O O TMR_2 CMI2A CMI2B OV2I IPRH6 to IPRH4 O O TMR_3 CMI3A CMI3B OV3I IPRH2 to IPRH0 O O DMAC DMTEND0 DMTEND1 DMTEND2 DMTEND3 IPRI14 to IPRI12 IPRI10 to IPRI8 IPRI6 to IPRI4 IPRI2 to IPRI0 O O O O Reserved for system use DMAC DMEEND0 DMEEND1 DMEEND2 DMEEND3 136 137 138 139 IPRK14 to IPRK12 O O O Low O Rev.1.00 Jun. 07, 2006 Page 113 of 1102 REJ09B0294-0100 Section 5 Interrupt Controller Classification Interrupt Source Vector Number Vector Address Offset* IPR Priority DTC Activation DMAC Activation Reserved for system use 140 141 142 143 H'0230 H'0234 H'0238 H'023C H'0240 H'0244 H'0248 H'024C H'0250 H'0254 H'0258 H'025C H'0260 H'0264 H'0268 H'026C H'0270 H'0274 H'0278 H'027C H'0280 H'0284 H'0288 H'028C H'0290 | H'035C High O O O O O O SCI_0 ERI0 RXI0 TXI0 TEI0 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 IPRK6 to IPRK4 O O SCI_1 ERI1 RXI1 TXI1 TEI1 IPRK2 to IPRK0 O O SCI_2 ERI2 RXI2 TXI2 TEI2 IPRL14 to IPRL12 O O Reserved for system use IPRL6 to IPRL4 O O Low | O O | SCI_4 ERI4 RXI4 TXI4 TEI4 160 161 162 163 164 | 215 Reserved for system use Rev.1.00 Jun. 07, 2006 Page 114 of 1102 REJ09B0294-0100 Section 5 Interrupt Controller Vector Address Offset* Classification Interrupt Source Vector Number IPR Priority DTC Activation DMAC Activation IIC2 IICI0 Reserved for system use IICI1 Reserved for system use 216 217 218 219 220 221 222 223 224 225 226 227 H'0360 H'0364 H'0368 H'036C H'0370 H'0374 H'0378 H'037C H'0380 H'0384 H'0388 H'038C H'0390 H'0394 H'0398 H'039C H'03A0 H'03A4 H'03A8 H'03AC H'03B0 H'03B4 H'03B8 H'03BC | H'03FC IPRQ6 to IPRQ4 High -- -- -- -- -- -- -- -- O O -- -- O O -- -- -- -- -- -- O O -- -- -- -- -- -- | -- SCI_5 RXI5 TXI5 ERI5 TEI5 IPRQ2 to IPRQ0 -- -- -- -- SCI_6 RXI6 TXI6 ERI6 TEI6 IPRR14 to IPRR12 -- -- -- -- TMR_4 TMR_5 TMR_6 TMR_7 USB CMIA4 or CMIB4 228 CMIA5 or CMIB5 229 CMIA6 or CMIB6 230 CMIA7 or CMIB7 231 USBINTN0 USBINTN1 USBINTN2 USBINTN3 232 233 234 235 236 237 238 239 | 255 IPRR10 to IPRR8 -- -- -- -- IPRR6 to IPRR4 -- -- -- -- -- Reserved for system use resume Reserved for system use IPRR2 to IPRR0 -- -- -- USB -- -- Low -- | -- Note: * Lower 16 bits of the start address in advanced, middle, and maximum modes. Rev.1.00 Jun. 07, 2006 Page 115 of 1102 REJ09B0294-0100 Section 5 Interrupt Controller 5.6 Interrupt Control Modes and Interrupt Operation The interrupt controller has two interrupt control modes: interrupt control mode 0 and interrupt control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is selected by INTCR. Table 5.3 shows the differences between interrupt control mode 0 and interrupt control mode 2. Table 5.3 Interrupt Control Mode 0 Interrupt Control Modes Priority Setting Register Default Interrupt Mask Bit I Description The priority levels of the interrupt sources are fixed default settings. The interrupts except for NMI is masked by the I bit. Eight priority levels can be set for interrupt sources except for NMI with IPR. 8-level interrupt mask control is performed by bits I2 to I0. 2 IPR I2 to I0 5.6.1 Interrupt Control Mode 0 In interrupt control mode 0, interrupt requests except for NMI are masked by the I bit in CCR of the CPU. Figure 5.3 shows a flowchart of the interrupt acceptance operation in this case. 1. If an interrupt request occurs when the corresponding interrupt enable bit is set to 1, the interrupt request is sent to the interrupt controller. 2. If the I bit in CCR is set to 1, NMI is accepted, and other interrupt requests are held pending. If the I bit is cleared to 0, an interrupt request is accepted. 3. For multiple interrupt requests, the interrupt controller selects the interrupt request with the highest priority, sends the request to the CPU, and holds other interrupt requests pending. 4. When the CPU accepts the interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. The PC and CCR contents are saved to the stack area during the interrupt exception handling. The PC contents saved on the stack is the address of the first instruction to be executed after returning from the interrupt handling routine. 6. Next, the I bit in CCR is set to 1. This masks all interrupts except NMI. Rev.1.00 Jun. 07, 2006 Page 116 of 1102 REJ09B0294-0100 Section 5 Interrupt Controller 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. Program execution state Interrupt generated? Yes Yes No NMI No I=0 Yes No Pending No IRQ0 Yes No IRQ1 Yes TEI4 Yes Save PC and CCR I1 Read vector address Branch to interrupt handling routine Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 Rev.1.00 Jun. 07, 2006 Page 117 of 1102 REJ09B0294-0100 Section 5 Interrupt Controller 5.6.2 Interrupt Control Mode 2 In interrupt control mode 2, interrupt requests except for NMI are masked by comparing the interrupt mask level (I2 to I0 bits) in EXR of the CPU and the IPR setting. There are eight levels in mask control. Figure 5.4 shows a flowchart of the interrupt acceptance operation in this case. 1. If an interrupt request occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. For multiple interrupt requests, the interrupt controller selects the interrupt request with the highest priority according to the IPR setting, and holds other interrupt requests pending. If multiple interrupt requests have the same priority, an interrupt request is selected according to the default setting shown in table 5.2. 3. Next, the priority of the selected interrupt request is compared with the interrupt mask level set in EXR. When the interrupt request does not have priority over the mask level set, it is held pending, and only an interrupt request with a priority over the interrupt mask level is accepted. 4. When the CPU accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. The PC, CCR, and EXR contents are saved to the stack area during interrupt exception handling. The PC saved on the stack is the address of the first instruction to be executed after returning from the interrupt handling routine. 6. The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority of the accepted interrupt. If the accepted interrupt is NMI, the interrupt mask level is set to H'7. 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. Rev.1.00 Jun. 07, 2006 Page 118 of 1102 REJ09B0294-0100 Section 5 Interrupt Controller Program execution state Interrupt generated? Yes Yes NMI No No No Level 7 interrupt? Yes Mask level 6 or below? Yes No Level 6 interrupt? No Yes Level 1 interrupt? Mask level 5 or below? Yes Mask level 0? Yes No Yes No No Save PC, CCR, and EXR Pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2 Rev.1.00 Jun. 07, 2006 Page 119 of 1102 REJ09B0294-0100 5.6.3 REJ09B0294-0100 Interrupt acceptance Instruction prefetch Internal operation Stack Vector fetch Internal operation Instruction prefetch in interrupt handling routine (1) (3) (5) (7) (9) (11) Section 5 Interrupt Controller Interrupt level determination Wait for end of instruction I Rev.1.00 Jun. 07, 2006 Page 120 of 1102 Interrupt request signal Internal address bus Interrupt Exception Handling Sequence Internal read signal Internal write signal Figure 5.5 shows the interrupt exception handling sequence. The example is for the case where interrupt control mode 0 is set in maximum mode, and the program area and stack area are in onchip memory. Figure 5.5 Interrupt Exception Handling (2) (4) (6) (8) (10) (12) (6) (8) (9) (10) (11) (12) Saved PC and saved CCR Vector address Start address of interrupt handling routine (vector address contents) Start address of Interrupt handling routine ((13) = (10)(12)) First instruction of interrupt handling routine Internal data bus (1) Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.) (2) (4) Instruction code (Not executed.) (3) Instruction prefetch address (Not executed.) (5) SP - 2 (7) SP - 4 Section 5 Interrupt Controller 5.6.4 Interrupt Response Times Table 5.4 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The symbols for execution states used in table 5.4 are explained in table 5.5. This LSI is capable of fast word transfer to on-chip memory, so allocating the program area in onchip ROM and the stack area in on-chip RAM enables high-speed processing. Table 5.4 Interrupt Response Times Normal Mode*5 Interrupt Control Mode 0 Interrupt Control Mode 2 Advanced Mode Interrupt Control Mode 0 3 1 to 19 + 2*SI SK to 2*SK*6 2*SK SK to 2*SK*6 2*SK Sh 3 Maximum Mode*5 Interrupt Control Mode 0 Interrupt Control Mode 2 Execution State Interrupt priority determination*1 Number of states until executing instruction ends*2 PC, CCR, EXR stacking Vector fetch Instruction fetch* Interrupt Control Mode 2 2*SK 2*SK 2*SI 4 Internal processing* 2 10 to 31 11 to 31 10 to 31 11 to 31 11 to 31 11 to 31 Total (using on-chip memory) Notes: 1. 2. 3. 4. 5. 6. Two states for an internal interrupt. In the case of the MULXS or DIVXS instruction Prefetch after interrupt acceptance or for an instruction in the interrupt handling routine. Internal operation after interrupt acceptance or after vector fetch Not available in this LSI. When setting the SP value to 4n, the interrupt response time is SK; when setting to 4n + 2, the interrupt response time is 2*SK. Rev.1.00 Jun. 07, 2006 Page 121 of 1102 REJ09B0294-0100 Section 5 Interrupt Controller Table 5.5 Number of Execution States in Interrupt Handling Routine Object of Access External Device 8-Bit Bus 16-Bit Bus 2-State Access 4 2 4 3-State Access 6 + 2m 3+m 6 + 2m Symbol Vector fetch Sh Instruction fetch SI Stack manipulation SK On-Chip Memory 1 1 1 2-State Access 8 4 8 3-State Access 12 + 4m 6 + 2m 12 + 4m [Legend] m: Number of wait cycles in an external device access. 5.6.5 DTC and DMAC Activation by Interrupt The DTC and DMAC can be activated by an interrupt. In this case, the following options are available: * Interrupt request to the CPU * Activation request to the DTC * Activation request to the DMAC * Combination of the above For details on interrupt requests that can be used to activate the DTC and DMAC, see table 5.2, section 7, DMA Controller (DMAC), and section 8, Data Transfer Controller (DTC). Figure 5.6 shows a block diagram of the DTC, DMAC, and interrupt controller. Rev.1.00 Jun. 07, 2006 Page 122 of 1102 REJ09B0294-0100 Section 5 Interrupt Controller Select signal DMRSR_0 to DMRSR_3 Control signal Interrupt request On-chip peripheral module Interrupt request clear signal DMAC select circuit DMAC activation request signal Clear signal DTCER Clear signal DMAC Select signal Interrupt request Clear signal DTC/CPU Interrupt request IRQ interrupt Interrupt request clear signal select circuit Priority determination Interrupt controller I, I2 to I0 DTC control circuit Clear signal CPU interrupt request vector number CPU DTC activation request vector number DTC Figure 5.6 Block Diagram of DTC, DMAC, and Interrupt Controller (1) Selection of Interrupt Sources The activation source for each DMAC channel is selected by DMRSR. The selected activation source is input to the DMAC through the select circuit. When transfer by an on-chip module interrupt is enabled (DTF1 = 1, DTF0 = 0, and DTE = 1 in DMDR) and the DTA bit in DMDR is set to 1, the interrupt source selected for the DMAC activation source is controlled by the DMAC and cannot be used as a DTC activation source or CPU interrupt source. Interrupt sources that are not controlled by the DMAC are set for DTC activation sources or CPU interrupt sources by the DTCE bit in DTCERA to DTCERH of the DTC. Specifying the DISEL bit in MRB of the DTC generates an interrupt request to the CPU by clearing the DTCE bit to 0 after the individual DTC data transfer. Note that when the DTC performs a predetermined number of data transfers and the transfer counter indicates 0, an interrupt request is made to the CPU by clearing the DTCE bit to 0 after the DTC data transfer. When the same interrupt source is set as both the DTC and DMAC activation source and CPU interrupt source, the DTC and DMAC must be given priority over the CPU. If the IPSETE bit in CPUPCR is set to 1, the priority is determined according to the IPR setting. Therefore, the CPUP setting or the IPR setting corresponding to the interrupt source must be set to lower than or equal to the DTCP and DMAP setting. If the CPU is given priority over the DTC or DMAC, the DTC or DMAC may not be activated, and the data transfer may not be performed. Rev.1.00 Jun. 07, 2006 Page 123 of 1102 REJ09B0294-0100 Section 5 Interrupt Controller (2) Priority Determination The DTC activation source is selected according to the default priority, and the selection is not affected by its mask level or priority level. For respective priority levels, see table 8.1, Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs. (3) Operation Order If the same interrupt is selected as both the DTC activation source and CPU interrupt source, the CPU interrupt exception handling is performed after the DTC data transfer. If the same interrupt is selected as the DTC or DMAC activation source or CPU interrupt source, respective operations are performed independently. Table 5.6 lists the selection of interrupt sources and interrupt source clear control by setting the DTA bit in DMDR of the DMAC, the DTCE bit in DTCERA to DTCERH of the DTC, and the DISEL bit in MRB of the DTC. Table 5.6 Interrupt Source Selection and Clear Control DTC Setting DTCE 0 1 DISEL * 0 1 1 * * Interrupt Source Selection/Clear Control DMAC O O O DTC X O X CPU X X DMAC Setting DTA 0 [Legend] : The corresponding interrupt is used. The interrupt source is cleared. (The interrupt source flag must be cleared in the CPU interrupt handling routine.) O: The corresponding interrupt is used. The interrupt source is not cleared. X: The corresponding interrupt is not available. *: Don't care. (4) Usage Note The interrupt sources of the SCI, and A/D converter are cleared according to the setting shown in table 5.6, when the DTC or DMAC reads/writes the prescribed register. To initiate multiple channels for the DTC with the same interrupt, the same priority (DTCP = DMAP) should be assigned. Rev.1.00 Jun. 07, 2006 Page 124 of 1102 REJ09B0294-0100 Section 5 Interrupt Controller 5.7 CPU Priority Control Function Over DTC and DMAC The interrupt controller has a function to control the priority among the DTC, DMAC, and the CPU by assigning different priority levels to the DTC, DMAC, and CPU. Since the priority level can automatically be assigned to the CPU on an interrupt occurrence, it is possible to execute the CPU interrupt exception handling prior to the DTC or DMAC transfer. The priority level of the CPU is assigned by bits CPUP2 to CPUP0 in CPUPCR. The priority level of the DTC is assigned by bits DTCP2 to DTCP0 in CPUPCR. The priority level of the DMAC is assigned by bits DMAP2 to DMAP0 in DMDR for each channel. The priority control function over the DTC and DMAC is enabled by setting the CPUPCE bit in CPUPCR to 1. When the CPUPCE bit is 1, the DTC and DMAC activation sources are controlled according to the respective priority levels. The DTC activation source is controlled according to the priority level of the CPU indicated by bits CPUP2 to CPUP0 and the priority level of the DTC indicated by bits DTCP2 to DTCP0. If the CPU has priority, the DTC activation source is held. The DTC is activated when the condition by which the activation source is held is cancelled (CPUPCE = 1 and value of bits CPUP2 to CPUP0 is greater than that of bits DTCP2 to DTCP0). The priority level of the DTC is assigned by the DTCP2 to DTCP0 bits regardless of the activation source. For the DMAC, the priority level can be specified for each channel. The DMAC activation source is controlled according to the priority level of each DMAC channel indicated by bits DMAP2 to DMAP0 and the priority level of the CPU. If the CPU has priority, the DMAC activation source is held. The DMAC is activated when the condition by which the activation source is held is cancelled (CPUPCE = 1 and value of bits CPUP2 to CPUP0 is greater than that of bits DMAP2 to DMAP0). If different priority levels are specified for channels, the channels of the higher priority levels continue transfer and the activation sources for the channels of lower priority levels than that of the CPU are held. There are two methods for assigning the priority level to the CPU by the IPSETE bit in CPUPCR. Setting the IPSETE bit to 1 enables a function to automatically assign the value of the interrupt mask bit of the CPU to the CPU priority level. Clearing the IPSETE bit to 0 disables the function to automatically assign the priority level. Therefore, the priority level is assigned directly by software rewriting bits CPUP2 to CPUP0. Even if the IPSETE bit is 1, the priority level of the CPU is software assignable by rewriting the interrupt mask bit of the CPU (I bit in CCR or I2 to I0 bits in EXR). Rev.1.00 Jun. 07, 2006 Page 125 of 1102 REJ09B0294-0100 Section 5 Interrupt Controller The priority level which is automatically assigned when the IPSETE bit is 1 differs according to the interrupt control mode. In interrupt control mode 0, the I bit in CCR of the CPU is reflected in bit CPUP2. Bits CPUP1 and CPUP0 are fixed 0. In interrupt control mode 2, the values of bits I2 to I0 in EXR of the CPU are reflected in bits CPUP2 to CPUP0. Table 5.7 shows the CPU priority control. Table 5.7 CPU Priority Control Control Status Interrupt Mask Bit I = any I=0 I=1 2 IPR setting I2 to I0 0 1 IPSETE in CPUPCR CPUP2 to CPUP0 0 1 B'111 to B'000 B'000 B'100 B'111 to B'000 I2 to I0 Enabled Disabled Updating of CPUP2 to CPUP0 Enabled Disabled Interrupt Control Interrupt Priority Mode 0 Default Rev.1.00 Jun. 07, 2006 Page 126 of 1102 REJ09B0294-0100 Section 5 Interrupt Controller Table 5.8 shows a setting example of the priority control function over the DTC and DMAC and the transfer request control state. A priority level can be independently set to each DMAC channel, but the table only shows one channel for example. Transfers through the DMAC channels can be separately controlled by assigning different priority levels for channels. Table 5.8 Example of Priority Control Function Setting and Control State DTCP2 to DTCP0 DMAP2 to DMAP0 Transfer Request Control State DTC DMAC Interrupt Control CPUPCE in CPUP2 to Mode CPUPCR CPUP0 0 0 1 Any B'000 B'100 B'100 B'100 B'000 Any B'000 B'000 B'000 B'111 B'111 Any B'000 B'011 B'011 B'011 B'011 B'011 B'011 B'011 B'110 Any B'000 B'000 B'011 B'101 B'101 Any B'000 B'101 B'101 B'101 B'101 B'101 B'101 B'101 B'101 Enabled Enabled Masked Masked Enabled Enabled Enabled Enabled Enabled Enabled Masked Masked Masked Masked Masked Enabled Enabled Enabled Masked Masked Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Masked Masked Enabled Enabled 2 0 1 Any B'000 B'000 B'011 B'100 B'101 B'110 B'111 B'101 B'101 Rev.1.00 Jun. 07, 2006 Page 127 of 1102 REJ09B0294-0100 Section 5 Interrupt Controller 5.8 5.8.1 Usage Notes Conflict between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to mask the interrupt, the masking becomes effective after execution of the instruction. When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there is an interrupt request with priority over that interrupt, interrupt exception handling will be executed for the interrupt with priority, and another interrupt will be ignored. The same also applies when an interrupt source flag is cleared to 0. Figure 5.7 shows an example in which the TCIEV bit in TIER of the TPU is cleared to 0. The above conflict will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. TIER_0 write cycle by CPU TCIV exception handling P Internal address bus TIER_0 address Internal write signal TCIEV TCFV TCIV interrupt signal Figure 5.7 Conflict between Interrupt Generation and Disabling Similarly, when an interrupt is requested immediately before the DTC enable bit is changed to activate the DTC, DTC activation and the interrupt exception handling by the CPU are both executed. When changing the DTC enable bit, make sure that an interrupt is not requested. Rev.1.00 Jun. 07, 2006 Page 128 of 1102 REJ09B0294-0100 Section 5 Interrupt Controller 5.8.2 Instructions that Disable Interrupts Instructions that disable interrupts immediately after execution are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.8.3 Times when Interrupts are Disabled There are times when interrupt acceptance is disabled by the interrupt controller. The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has updated the mask level with an LDC, ANDC, ORC, or XORC instruction, and for a period of writing to the registers of the interrupt controller. 5.8.4 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B and the EEPMOV.W instructions. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the transfer is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at the end of the individual transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used. L1: EEPMOV.W MOV.W BNE R4,R4 L1 5.8.5 Interrupts during Execution of MOVMD and MOVSD Instructions With the MOVMD or MOVSD instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at the end of the individual transfer cycle. The PC value saved on the stack in this case is the address of the MOVMD or MOVSD instruction. The transfer of the remaining data is resumed after returning from the interrupt handling routine. Rev.1.00 Jun. 07, 2006 Page 129 of 1102 REJ09B0294-0100 Section 5 Interrupt Controller 5.8.6 Interrupts of Peripheral Modules To clear an interrupt source flag by the CPU using an interrupt function of a peripheral module, the flag must be read from after clearing within the interrupt processing routine. This makes the request signal synchronized with the peripheral module clock. For details, refer to section 22.6.1, Notes on Clock Pulse Generator. Rev.1.00 Jun. 07, 2006 Page 130 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Section 6 Bus Controller (BSC) This LSI has an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus controller also has a bus arbitration function, and controls the operation of the internal bus masters; CPU, DMAC, and DTC. 6.1 Features * Manages external address space in area units Manages the external address space divided into eight areas Chip select signals (CS0 to CS7) can be output for each area Bus specifications can be set independently for each area 8-bit access or 16-bit access can be selected for each area Burst ROM, byte control SRAM, or address/data multiplexed I/O interface can be set An endian conversion function is provided to connect a device of little endian * Basic bus interface This interface can be connected to the SRAM and ROM 2-state access or 3-state access can be selected for each area Program wait cycles can be inserted for each area Wait cycles can be inserted by the WAIT pin. Extension cycles can be inserted while CSn is asserted for each area (n = 0 to 7) The negation timing of the read strobe signal (RD) can be modified * Byte control SRAM interface Byte control SRAM interface can be set for areas 0 to 7 The SRAM that has a byte control pin can be directly connected * Burst ROM interface Burst ROM interface can be set for areas 0 and 1 Burst ROM interface parameters can be set independently for areas 0 and 1 * Address/data multiplexed I/O interface Address/data multiplexed I/O interface can be set for areas 3 to 7 Rev.1.00 Jun. 07, 2006 Page 131 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) * DRAM interface DRAM interface is available as area 2 Row/column address-multiplexed output (8, 9, 10, or 11 bits) Two CAS signals control byte accesses for 16-bit data bus device CAS assertion period can be extended by a program wait and a pin wait Burst access can be performed in fast page mode Tp cycle for ensuring a RAS precharge time can be inserted CAS-before-RAS refresh (CBR refresh) and self refresh are selectable * Synchronous DRAM interface Synchronous DRAM interface is available as area 2 Row/column address-multiplexed output (8, 9, 10, or 11 bits) DQM signals control byte access for 16-bit data bus device Auto refresh and self refresh are selectable CAS latency can be selected from 2 to 4 * Idle cycle insertion Idle cycles can be inserted between external read accesses to different areas Idle cycles can be inserted before the external write access after an external read access Idle cycles can be inserted before the external read access after an external write access Idle cycles can be inserted before the external access after a DMAC single address transfer (write access) * Write buffer function External write cycles and internal accesses can be executed in parallel Write accesses to the on-chip peripheral module and on-chip memory accesses can be executed in parallel DMAC single address transfers and internal accesses can be executed in parallel * External bus release function * Bus arbitration function Includes a bus arbiter that arbitrates bus mastership among the CPU, DMAC, DTC, and external bus master * Multi-clock function The internal peripheral functions can be operated in synchronization with the peripheral module clock (P). Accesses to the external address space can be operated in synchronization with the external bus clock (B). * The bus start (BS) and read/write (RD/WR) signals can be output. Rev.1.00 Jun. 07, 2006 Page 132 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) A block diagram of the bus controller is shown in figure 6.1. CPU address bus DMAC address bus DTC address bus Address selector Area decoder CS7 to CS0 Internal bus control signals CPU bus acknowledge signal DTC bus acknowledge signal DMAC bus acknowledge signal CPU bus request signal DTC bus request signal DMAC bus request signal Internal bus control unit External bus control unit Internal bus arbiter External bus arbiter Refresh timer External bus control signals WAIT BREQ BACK BREQO Control registers Internal data bus ABWCR ASTCR WTCRA WTCRB RDNCR CSACR IDLCR BCR1 BCR2 ENDIANCR SRAMCR: SRAM mode control register BROMCR: Burst ROM interface control register MPXCR: Address/data multiplexed I/O control register DRAMCR: DRAM control register DRACCR: DRAM access control register Synchronous DRAM control register SDCR: REFCR: Refresh control register RTCNT: Refresh timer counter RTCOR: Refresh time constant register SRAMCR BROMCR MPXCR DRAMCR DRACCR SDCR REFCR RTCNT RTCOR [Legend] Bus width control register ABWCR: Access state control register ASTCR: Wait control register A WTCRA: Wait control register B WTCRB: Read strobe timing control register RDNCR: CS assertion period control register CSACR: Idle control register IDLCR: Bus control register 1 BCR1: Bus control register 2 BCR2: ENDIANCR:Endian control register Figure 6.1 Block Diagram of Bus Controller Rev.1.00 Jun. 07, 2006 Page 133 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.2 Register Descriptions The bus controller has the following registers. * Bus width control register (ABWCR) * Access state control register (ASTCR) * Wait control register A (WTCRA) * Wait control register B (WTCRB) * Read strobe timing control register (RDNCR) * CS assertion period control register (CSACR) * Idle control register (IDLCR) * Bus control register 1 (BCR1) * Bus control register 2 (BCR2) * Endian control register (ENDIANCR) * SRAM mode control register (SRAMCR) * Burst ROM interface control register (BROMCR) * Address/data multiplexed I/O control register (MPXCR) * DRAM control register (DRAMCR) * DRAM access control register (DRACCR) * Synchronous DRAM control register (SDCR) * Refresh control register (REFCR) * Refresh timer counter (RTCNT) * Refresh time constant register (RTCOR) Rev.1.00 Jun. 07, 2006 Page 134 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.2.1 Bus Width Control Register (ABWCR) ABWCR specifies the data bus width for each area in the external address space. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 ABWH7 1 R/W 7 ABWL7 1 R/W 14 ABWH6 1 R/W 6 ABWL6 1 R/W 13 ABWH5 1 R/W 5 ABWL5 1 R/W 12 ABWH4 1 R/W 4 ABWL4 1 R/W 11 ABWH3 1 R/W 3 ABWL3 1 R/W 10 ABWH2 1 R/W 2 ABWL2 1 R/W 9 ABWH1 1 R/W 1 ABWL1 1 R/W 8 ABWH0 1/0 R/W 0 ABWL0 1 R/W Note: * Initial value at 16-bit bus initiation is H'FEFF, and that at 8-bit bus initiation is H'FFFF. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name ABWH7 ABWH6 ABWH5 ABWH4 ABWH3 ABWH2 ABWH1 ABWL0 ABWL7 ABWL6 ABWL5 ABWL4 ABWL3 ABWL2 ABWL1 ABWL0 Initial 1 Value* 1 1 1 1 1 1 1 1/0 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Area 7 to 0 Bus Width Control These bits select whether the corresponding area is to be designated as 8-bit access space or 16-bit access space. ABWHn ABWLn (n = 7 to 0) x 0: Setting prohibited 0 1: Area n is designated as 16-bit access space 1 1: Area n is designated as 8-bit access 2 space* [Legend] x: Don't care Notes: 1. Initial value at 16-bit bus initiation is H'FEFF, and that at 8-bit bus initiation is H'FFFF. 2. An address space specified as byte control SRAM interface must not be specified as 8bit access space. Rev.1.00 Jun. 07, 2006 Page 135 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.2.2 Access State Control Register (ASTCR) ASTCR designates each area in the external address space as either 2-state access space or 3-state access space and enables/disables wait cycle insertion. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 AST7 1 R/W 7 0 R 14 AST6 1 R/W 6 0 R 13 AST5 1 R/W 5 0 R 12 AST4 1 R/W 4 0 R 11 AST3 1 R/W 3 0 R 10 AST2 1 R/W 2 0 R 9 AST1 1 R/W 1 0 R 8 AST0 1 R/W 0 0 R Bit 15 14 13 12 11 10 9 8 Bit Name AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0 Initial Value 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Area 7 to 0 Access State Control These bits select whether the corresponding area is to be designated as 2-state access space or 3-state access space. Wait cycle insertion is enabled or disabled at the same time. 0: Area n is designated as 2-state access space Wait cycle insertion in area n access is disabled 1: Area n is designated as 3-state access space Wait cycle insertion in area n access is enabled (n = 7 to 0) Reserved These are read-only bits and cannot be modified. 7 to 0 All 0 R Rev.1.00 Jun. 07, 2006 Page 136 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.2.3 Wait Control Registers A and B (WTCRA, WTCRB) WTCRA and WTCRB select the number of program wait cycles for each area in the external address space. * WTCRA Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W * WTCRB Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 0 R 7 0 R 14 W32 1 R/W 6 W12 1 R/W 13 W31 1 R/W 5 W11 1 R/W 12 W30 1 R/W 4 W10 1 R/W 11 0 R 3 0 R 10 W22 1 R/W 2 W02 1 R/W 9 W21 1 R/W 1 W01 1 R/W 8 W20 1 R/W 0 W00 1 R/W 15 0 R 7 0 R 14 W72 1 R/W 6 W52 1 R/W 13 W71 1 R/W 5 W51 1 R/W 12 W70 1 R/W 4 W50 1 R/W 11 0 R 3 0 R 10 W62 1 R/W 2 W42 1 R/W 9 W61 1 R/W 1 W41 1 R/W 8 W60 1 R/W 0 W40 1 R/W Rev.1.00 Jun. 07, 2006 Page 137 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) * WTCRA Bit 15 14 13 12 Bit Name W72 W71 W70 Initial Value 0 1 1 1 R/W R R/W R/W R/W Description Reserved This is a read-only bit and cannot be modified. Area 7 Wait Control 2 to 0 These bits select the number of program wait cycles when accessing area 7 while bit AST7 in ASTCR is 1. 000: Program wait cycle not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted 11 10 9 8 W62 W61 W60 0 1 1 1 R R/W R/W R/W Reserved This is a read-only bit and cannot be modified. Area 6 Wait Control 2 to 0 These bits select the number of program wait cycles when accessing area 6 while bit AST6 in ASTCR is 1. 000: Program wait cycle not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted 7 0 R Reserved This is a read-only bit and cannot be modified. Rev.1.00 Jun. 07, 2006 Page 138 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Bit 6 5 4 Bit Name W52 W51 W50 Initial Value 1 1 1 R/W R/W R/W R/W Description Area 5 Wait Control 2 to 0 These bits select the number of program wait cycles when accessing area 5 while bit AST5 in ASTCR is 1. 000: Program cycle wait not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted 3 2 1 0 W42 W41 W40 0 1 1 1 R R/W R/W R/W Reserved This is a read-only bit and cannot be modified. Area 4 Wait Control 2 to 0 These bits select the number of program wait cycles when accessing area 4 while bit AST4 in ASTCR is 1. 000: Program wait cycle not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted * WTCRB Bit 15 Bit Name Initial Value 0 R/W R Description Reserved This is a read-only bit and cannot be modified. Rev.1.00 Jun. 07, 2006 Page 139 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Bit 14 13 12 Bit Name W32 W31 W30 Initial Value 1 1 1 R/W R/W R/W R/W Description Area 3 Wait Control 2 to 0 These bits select the number of program wait cycles when accessing area 3 while bit AST3 in ASTCR is 1. 000: Program wait cycle not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted 11 10 9 8 W22 W21 W20 0 1 1 1 R R/W R/W R/W Reserved This is a read-only bit and cannot be modified. Area 2 Wait Control 2 to 0 These bits select the number of program wait cycles when accessing area 2 while bit AST2 in ASTCR is 1. When SDRAM is connected, the CAS latency is specified. At this time, W22 is ignored. The CAS latency can be specified even if the wait cycle insertion is disabled by ASTCR. Selection of number of program wait cycles: 000: Program wait cycle not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted Setting of CAS latency (W22 is ignored.): 00: Setting prohibited 01: SDRAM with a CAS latency of 2 is connected. 10: SDRAM with a CAS latency of 3 is connected. 11: SDRAM with a CAS latency of 4 is connected. Rev.1.00 Jun. 07, 2006 Page 140 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Bit 7 6 5 4 Bit Name W12 W11 W10 Initial Value 0 1 1 1 R/W R R/W R/W R/W Description Reserved This is a read-only bit and cannot be modified. Area 1 Wait Control 2 to 0 These bits select the number of program wait cycles when accessing area 1 while bit AST1 in ASTCR is 1. 000: Program wait cycle not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted 3 2 1 0 W02 W01 W00 0 1 1 1 R R/W R/W R/W Reserved This is a read-only bit and cannot be modified. Area 0 Wait Control 2 to 0 These bits select the number of program wait cycles when accessing area 0 while bit AST0 in ASTCR is 1. 000: Program wait cycle not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted Rev.1.00 Jun. 07, 2006 Page 141 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.2.4 Read Strobe Timing Control Register (RDNCR) RDNCR selects the negation timing of the read strobe signal (RD) when reading the external address spaces specified as a basic bus interface or the address/data multiplexed I/O interface. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 RDN7 0 R/W 7 0 R 14 RDN6 0 R/W 6 0 R 13 RDN5 0 R/W 5 0 R 12 RDN4 0 R/W 4 0 R 11 RDN3 0 R/W 3 0 R 10 RDN2 0 R/W 2 0 R 9 RDN1 0 R/W 1 0 R 8 RDN0 0 R/W 0 0 R Bit 15 14 13 12 11 10 9 8 Bit Name RDN7 RDN6 RDN5 RDN4 RDN3 RDN2 RDN1 RDN0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Read Strobe Timing Control RDN7 to RDN0 set the negation timing of the read strobe in a corresponding area read access. As shown in figure 6.2, the read strobe for an area for which the RDNn bit is set to 1 is negated one halfcycle earlier than that for an area for which the RDNn bit is cleared to 0. The read data setup and hold time are also given one half-cycle earlier. 0: In an area n read access, the RD signal is negated at the end of the read cycle 1: In an area n read access, the RD signal is negated one half-cycle before the end of the read cycle (n = 7 to 0) 7 to 0 All 0 R Reserved These are read-only bits and cannot be modified. Notes: 1. In an external address space which is specified as byte control SRAM interface, the RDNCR setting is ignored and the same operation when RDNn = 1 is performed. 2. In an external address space which is specified as burst ROM interface, the RDNCR setting is ignored during CPU read accesses and the same operation when RDNn = 0 is performed. Rev.1.00 Jun. 07, 2006 Page 142 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Bus cycle T1 B T2 T3 RD RDNn = 0 Data RD RDNn = 1 Data (n = 7 to 0) Figure 6.2 Read Strobe Negation Timing (Example of 3-State Access Space) 6.2.5 CS Assertion Period Control Registers (CSACR) CSACR selects whether or not the assertion periods of the chip select signals (CSn) and address signals for the basic bus, byte-control SRAM, burst ROM, and address/data multiplexed I/O interface are to be extended. Extending the assertion period of the CSn and address signals allows the setup time and hold time of read strobe (RD) and write strobe (LHWR/LLWR) to be assured and to make the write data setup time and hold time for the write strobe become flexible. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 CSXH7 0 R/W 7 CSXT7 0 R/W 14 CSXH6 0 R/W 6 CSXT6 0 R/W 13 CSXH5 0 R/W 5 CSXT5 0 R/W 12 CSXH4 0 R/W 4 CSXT4 0 R/W 11 CSXH3 0 R/W 3 CSXT3 0 R/W 10 CSXH2 0 R/W 2 CSXT2 0 R/W 9 CSXH1 0 R/W 1 CSXT1 0 R/W 8 CSXH0 0 R/W 0 CSXT0 0 R/W Rev.1.00 Jun. 07, 2006 Page 143 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Bit 15 14 13 12 11 10 9 8 Bit Name CSXH7 CSXH6 CSXH5 CSXH4 CSXH3 CSXH2 CSXH1 CSXH0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description CS and Address Signal Assertion Period Control 1 These bits specify whether or not the Th cycle is to be inserted (see figure 6.3). When an area for which bit CSXHn is set to 1 is accessed, one Th cycle, in which the CSn and address signals are asserted, is inserted before the normal access cycle. 0: In access to area n, the CSn and address assertion period (Th) is not extended 1: In access to area n, the CSn and address assertion period (Th) is extended (n = 7 to 0) CS and Address Signal Assertion Period Control 2 These bits specify whether or not the Tt cycle is to be inserted (see figure 6.3). When an area for which bit CSXTn is set to 1 is accessed, one Tt cycle, in which the CSn and address signals are retained, is inserted after the normal access cycle. 0: In access to area n, the CSn and address assertion period (Tt) is not extended 1: In access to area n, the CSn and address assertion period (Tt) is extended (n = 7 to 0) 7 6 5 4 3 2 1 0 CSXT7 CSXT6 CSXT5 CSXT4 CSXT3 CSXT2 CSXT1 CSXT0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Note: * In burst ROM interface, the CSXTn settings are ignored during CPU read accesses. Rev.1.00 Jun. 07, 2006 Page 144 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Bus cycle Th B T1 T2 T3 Tt Address CSn AS BS RD/WR RD Read Data bus Read data LHWR, LLWR Write Data bus Write data Figure 6.3 CS and Address Assertion Period Extension (Example of Basic Bus Interface, 3-State Access Space, and RDNn = 0) Rev.1.00 Jun. 07, 2006 Page 145 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.2.6 Idle Control Register (IDLCR) IDLCR specifies the idle cycle insertion conditions and the number of idle cycles. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 IDLS3 1 R/W 7 IDLSEL7 0 R/W 14 IDLS2 1 R/W 6 IDLSEL6 0 R/W 13 IDLS1 1 R/W 5 IDLSEL5 0 R/W 12 IDLS0 1 R/W 4 IDLSEL4 0 R/W 11 IDLCB1 1 R/W 3 IDLSEL3 0 R/W 10 IDLCB0 1 R/W 2 IDLSEL2 0 R/W 9 IDLCA1 1 R/W 1 IDLSEL1 0 R/W 8 IDLCA0 1 R/W 0 IDLSEL0 0 R/W Bit 15 Bit Name IDLS3 Initial Value 1 R/W R/W Description Idle Cycle Insertion 3 Inserts an idle cycle between the bus cycles when the DMAC single address transfer (write cycle) is followed by external access. 0: No idle cycle is inserted 1: An idle cycle is inserted 14 IDLS2 1 R/W Idle Cycle Insertion 2 Inserts an idle cycle between the bus cycles when the external write cycle is followed by external read cycle. 0: No idle cycle is inserted 1: An idle cycle is inserted 13 IDLS1 1 R/W Idle Cycle Insertion 1 Inserts an idle cycle between the bus cycles when the external read cycles of different areas continue. 0: No idle cycle is inserted 1: An idle cycle is inserted Rev.1.00 Jun. 07, 2006 Page 146 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Bit 12 Bit Name IDLS0 Initial Value 1 R/W R/W Description Idle Cycle Insertion 0 Inserts an idle cycle between the bus cycles when the external read cycle is followed by external write cycle. 0: No idle cycle is inserted 1: An idle cycle is inserted 11 10 IDLCB1 IDLCB0 1 1 R/W R/W Idle Cycle State Number Select B Specifies the number of idle cycles to be inserted for the idle condition specified by IDLS1 and IDLS0. 00: No idle cycle is inserted 01: 2 idle cycles are inserted 00: 3 idle cycles are inserted 01: 4 idle cycles are inserted 9 8 IDLCA1 IDLCA0 1 1 R/W R/W Idle Cycle State Number Select A Specifies the number of idle cycles to be inserted for the idle condition specified by IDLS3 to IDLS0. 00: 1 idle cycle is inserted 01: 2 idle cycles are inserted 10: 3 idle cycles are inserted 11: 4 idle cycles are inserted 7 6 5 4 3 2 1 0 IDLSEL7 IDLSEL6 IDLSEL5 IDLSEL4 IDLSEL3 IDLSEL2 IDLSEL1 IDLSEL0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Idle Cycle Number Select Specifies the number of idle cycles to be inserted for each area for the idle insertion condition specified by IDLS1 and IDLS0. 0: Number of idle cycles to be inserted for area n is specified by IDLCA1 and IDLCA0. 1: Number of idle cycles to be inserted for area n is specified by IDLCB1 and IDLCB0. (n = 7 to 0) Rev.1.00 Jun. 07, 2006 Page 147 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.2.7 Bus Control Register 1 (BCR1) BCR1 is used for selection of the external bus released state protocol, enabling/disabling of the write data buffer function, and enabling/disabling of the WAIT pin input. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 BRLE 0 R/W 7 DKC 0 R/W 14 BREQOE 0 R/W 6 0 R/W 13 0 R 5 0 R 12 0 R 4 0 R 11 0 R/W 3 0 R 10 0 R/W 2 0 R 9 WDBE 0 R/W 1 0 R 8 WAITE 0 R/W 0 0 R Bit 15 Bit Name BRLE Initial Value 0 R/W R/W Description External Bus Release Enable Enables/disables external bus release. 0: External bus release disabled BREQ, BACK, and BREQO pins can be used as I/O ports 1: External bus release enabled* For details, see section 9, I/O Ports. BREQO Pin Enable Controls outputting the bus request signal (BREQO) to the external bus master in the external bus released state when an internal bus master performs an external address space access. 0: BREQO output disabled BREQO pin can be used as I/O port 1: BREQO output enabled 14 BREQOE 0 R/W Rev.1.00 Jun. 07, 2006 Page 148 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Bit 13, 12 11, 10 Bit Name Initial Value All 0 All 0 R/W R R/W Description Reserved These are read-only bits and cannot be modified. Reserved These bits are always read as 0. The write value should always be 0. 9 WDBE 0 R/W Write Data Buffer Enable The write data buffer function can be used for an external write cycle and a DMAC single address transfer cycle. The changed setting may not affect an external access immediately after the change. 0: Write data buffer function not used 1: Write data buffer function used 8 WAITE 0 R/W WAIT Pin Enable Selects enabling/disabling of wait input by the WAIT pin. 0: Wait input by WAIT pin disabled WAIT pin can be used as I/O port 1: Wait input by WAIT pin enabled For details, see section 9, I/O Ports. 7 DKC 0 R/W DACK Control Selects the timing of DMAC transfer acknowledge signal assertion. 0: DACK signal is asserted at the B falling edge 1: DACK signal is asserted at the B rising edge 6 0 R/W Reserved This bit is always read as 0. The write value should always be 0. 5 to 0 All 0 R Reserved These are read-only bits and cannot be modified. Note: When external bus release is enabled or input by the WAIT pin is enabled, make sure to set the ICR bit to 1. For details, see section 9, I/O Ports. Rev.1.00 Jun. 07, 2006 Page 149 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.2.8 Bus Control Register 2 (BCR2) BCR2 is used for bus arbitration control of the CPU, DMAC, and DTC, and enabling/disabling of the write data buffer function to the peripheral modules. Bit Bit Name Initial Value R/W 7 0 R 6 0 R 5 0 R/W 4 IBCCS 0 R/W 3 0 R 2 0 R 1 1 R/W 0 PWDBE 0 R/W Bit 7, 6 5 Bit Name Initial Value All 0 0 R/W R R/W Description Reserved These are read-only bits and cannot be modified. Reserved This bit is always read as 0. The write value should always be 0. 4 IBCCS 0 R/W Internal Bus Cycle Control Select Selects the internal bus arbiter function. 0: Releases the bus mastership according to the priority 1: Executes the bus cycles alternatively when a CPU bus mastership request conflicts with a DMAC or DTC bus mastership request 3, 2 1 All 0 1 R R/W Reserved These are read-only bits and cannot be modified. Reserved This bit is always read as 1. The write value should always be 1. 0 PWDBE 0 R/W Peripheral Module Write Data Buffer Enable Specifies whether or not to use the write data buffer function for the peripheral module write cycles. 0: Write data buffer function not used 1: Write data buffer function used Rev.1.00 Jun. 07, 2006 Page 150 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.2.9 Endian Control Register (ENDIANCR) ENDIANCR selects the endian format for each area of the external address space. Though the data format of this LSI is big endian, data can be transferred in the little endian format during external address space access. Note that the data format for the areas used as a program area or a stack area should be big endian. Bit Bit Name Initial Value R/W 7 LE7 0 R/W 6 LE6 0 R/W 5 LE5 0 R/W 4 LE4 0 R/W 3 LE3 0 R/W 2 LE2 0 R/W 1 0 R 0 0 R Bit 7 6 5 4 3 2 1, 0 Bit Name LE7 LE6 LE5 LE4 LE3 LE2 Initial Value 0 0 0 0 0 0 All 0 R/W R/W R/W R/W R/W R/W R/W R Description Little Endian Select Selects the endian for the corresponding area. 0: Data format of area n is specified as big endian 1: Data format of area n is specified as little endian (n = 7 to 2) Reserved These are read-only bits and cannot be modified. Rev.1.00 Jun. 07, 2006 Page 151 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.2.10 SRAM Mode Control Register (SRAMCR) SRAMCR specifies the bus interface of each area in the external address space as a basic bus interface or a byte control SRAM interface. In areas specified as 8-bit access space by ABWCR, the SRAMCR setting is ignored and the byte control SRAM interface cannot be specified. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 BCSEL7 0 R/W 7 0 R 14 BCSEL6 0 R/W 6 0 R 13 BCSEL5 0 R/W 5 0 R 12 BCSEL4 0 R/W 4 0 R 11 BCSEL3 0 R/W 3 0 R 10 BCSEL2 0 R/W 2 0 R 9 BCSEL1 0 R/W 1 0 R 8 BCSEL0 0 R/W 0 0 R Bit 15 14 13 12 11 10 9 8 7 to 0 Bit Name BCSEL7 BCSEL6 BCSEL5 BCSEL4 BCSEL3 BCSEL2 BCSEL1 BCSEL0 Initial Value 0 0 0 0 0 0 0 0 All 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R Description Byte Control SRAM Interface Select Selects the bus interface for the corresponding area. When setting a bit to 1, the bus interface select bits in BROMCR and MPXCR must be cleared to 0. 0: Area n is basic bus interface 1: Area n is byte control SRAM interface (n = 7 to 0) Reserved These are read-only bits and cannot be modified. Rev.1.00 Jun. 07, 2006 Page 152 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.2.11 Burst ROM Interface Control Register (BROMCR) BROMCR specifies the burst ROM interface. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 BSRM0 0 R/W 7 BSRM1 0 R/W 14 BSTS02 0 R/W 6 BSTS12 0 R/W 13 BSTS01 0 R/W 5 BSTS11 0 R/W 12 BSTS00 0 R/W 4 BSTS10 0 R/W 11 0 R 3 0 R 10 0 R 2 0 R 9 BSWD01 0 R/W 1 BSWD11 0 R/W 8 BSWD00 0 R/W 0 BSWD10 0 R/W Bit 15 Bit Name BSRM0 Initial Value 0 R/W R/W Description Area 0 Burst ROM Interface Select Specifies the area 0 bus interface. To set this bit to 1, clear bit BCSEL0 in SRAMCR to 0. 0: Basic bus interface or byte-control SRAM interface 1: Burst ROM interface 14 13 12 BSTS02 BSTS01 BSTS00 0 0 0 R/W R/W R/W Area 0 Burst Cycle Select Specifies the number of burst cycles of area 0 000: 1 cycle 001: 2 cycles 010: 3 cycles 011: 4 cycles 100: 5 cycles 101: 6 cycles 110: 7 cycles 111: 8 cycles 11, 10 All 0 R Reserved These are read-only bits and cannot be modified. Rev.1.00 Jun. 07, 2006 Page 153 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Bit 9 8 Bit Name BSWD01 BSWD00 Initial Value 0 0 R/W R/W R/W Description Area 0 Burst Word Number Select Selects the number of words in burst access to the area 0 burst ROM interface 00: Up to 4 words (8 bytes) 01: Up to 8 words (16 bytes) 10: Up to 16 words (32 bytes) 11: Up to 32 words (64 bytes) 7 BSRM1 0 R/W Area 1 Burst ROM Interface Select Specifies the area 1 bus interface as a basic interface or a burst ROM interface. To set this bit to 1, clear bit BCSEL1 in SRAMCR to 0. 0: Basic bus interface or byte-control SRAM interface 1: Burst ROM interface 6 5 4 BSTS12 BSTS11 BSTS10 0 0 0 R/W R/W R/W Area 1 Burst Cycle Select Specifies the number of cycles of area 1 burst cycle 000: 1 cycle 001: 2 cycles 010: 3 cycles 011: 4 cycles 100: 5 cycles 101: 6 cycles 110: 7 cycles 111: 8 cycles 3, 2 1 0 BSWD11 BSWD10 All 0 0 0 R R/W R/W Reserved These are read-only bits and cannot be modified. Area 1 Burst Word Number Select Selects the number of words in burst access to the area 1 burst ROM interface 00: Up to 4 words (8 bytes) 01: Up to 8 words (16 bytes) 10: Up to 16 words (32 bytes) 11: Up to 32 words (64 bytes) Rev.1.00 Jun. 07, 2006 Page 154 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.2.12 Address/Data Multiplexed I/O Control Register (MPXCR) MPXCR specifies the address/data multiplexed I/O interface. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 MPXE7 0 R/W 7 0 R 14 MPXE6 0 R/W 6 0 R 13 MPXE5 0 R/W 5 0 R 12 MPXE4 0 R/W 4 0 R 11 MPXE3 0 R/W 3 0 R 10 0 R 2 0 R 9 0 R 1 0 R 8 0 R 0 ADDEX 0 R/W Bit 15 14 13 12 11 Bit Name MPXE7 MPXE6 MPXE5 MPXE4 MPXE3 Initial Value 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Description Address/Data Multiplexed I/O Interface Select Specifies the bus interface for the corresponding area. To set this bit to 1, clear the BCSELn bit in SRAMCR to 0. 0: Area n is specified as a basic interface or a byte control SRAM interface. 1: Area n is specified as an address/data multiplexed I/O interface (n = 7 to 3) 10 to 1 0 ADDEX All 0 0 R R/W Reserved These are read-only bits and cannot be modified. Address Output Cycle Extension Specifies whether a wait cycle is inserted for the address output cycle of address/data multiplexed I/O interface. 0: No wait cycle is inserted for the address output cycle 1: One wait cycle is inserted for the address output cycle Rev.1.00 Jun. 07, 2006 Page 155 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.2.13 DRAM Control Register (DRAMCR) DRAMCR specifies the DRAM/SDRAM interface. Rewrite this register while the DRAM/SDRAM is not accessed. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 DRAME 0 R/W 7 BE 0 R/W 14 DTYPE 0 R/W 6 RCDM 0 R/W 13 0 R 5 DDS 0 R/W 12 0 R 4 0 R/W 11 OEE 0 R/W 3 0 R 10 RAST 0 R/W 2 0 R/W 9 0 R 1 MXC1 0 R/W 8 CAST 0 R/W 0 MXC0 0 R/W Bit 15 Bit Name DRAME Initial Value 0 R/W R/W Description Area 2 DRAM Interface Select Selects whether or not area 2 is specified as the DRAM/SDRAM interface. When this bit is set to 1, select the type of DRAM to be used in area 2 with the DTYPE bit. When this bit is set to 1, the BCSEL2 bit in SRAMCR should be set to 0. 0: Basic bus interface or byte-control SRAM interface 1: DRAM/SDRAM interface 14 DTYPE 0 R/W DRAM Select Selects the type of DRAM to be used in area 2. 0: DRAM is used in area 2 1: SDRAM is used in area 2 13, 12 11 OEE All 0 0 R R/W Reserved The initial value should not be changed. OE Output Enable The OE signal is output when DRAM with the EDO page mode is connected, whereas the CKE signal is output when SDRAM is connected. 0: OE/CKE signal output disabled (the OE/CKE pin can be used as an I/O port) 1: OE/CKE signal enabled Rev.1.00 Jun. 07, 2006 Page 156 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Bit 10 Bit Name RAST Initial Value 0 R/W R/W Description RAS Assertion Timing Select Selects whether the RAS signal is asserted at the rising edge or falling edge of the B signal in the Tr cycle during a DRAM access. The relationship between this bit and RAS assertion timing is shown in figure 6.4. When SDRAM is used, the setting of this bit does not affect operation. 0: RAS signal is asserted at the falling edge of the Bf signal in the Tr cycle 1: RAS signal is asserted at the rising edge of the Bf signal in the Tr cycle 9 8 CAST 0 0 R R/W Reserved The initial value should not be changed. Column Address Output Cycle Count Select Selects whether the number of column address output cycles is two or three during a DRAM access. When SDRAM is used, the setting of this bit does not affect operation. 0: Column address is output for two cycles 1: Column address is output for three cycles 7 BE 0 R/W Burst Access Enable Enables or disables a burst access to the DRAM/SDRAM. The DRAM/SDRAM is accessed in high-speed page mode. When DRAM with the EDO page mode is used, connect the OE signal of this LSI to the OE signal of DRAM. 0: DRAM/SDRAM is accessed with full access 1: DRAM/SDRAM is accessed in high-speed page mode Rev.1.00 Jun. 07, 2006 Page 157 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Bit 6 Bit Name RCDM Initial Value 0 R/W R/W Description RAS Down Mode Selects the RAS signal state while a DRAM access is halted when a basic bus interface area or an on-chip I/O register is accessed: keep the RAS signal low (RAS down mode) and high (RAS up mode). This bit is effective when BE = 1. Clearing this bit to 0 with RCDM = 1 in RAS down mode cancels the RAS down mode and the RAS signal goes high. If the RAS down mode is selected for the SDRAM interface, the READ/WRIT command is issued without issuance of the ACTV command when the same row address is accessed consecutively. 0: RAS up mode when the DRAM/SDRAM is accessed 1: RAS down mode when the DRAM/SDRAM is accessed 5 DDS 0 R/W DMAC Single Address Transfer Option Selects whether a DMAC single address transfer through the DRAM/SDRAM interface is enabled only in full access mode or is also enabled in fast-page access mode. When clearing the BE bit to 0 to disable a burst access to the DRAM/SDRAM interface, a DMAC single address transfer is performed in full access mode regardless of this bit. This bit does not affect an external access by other bus masters or a DMAC dual address transfer. Setting this bit to 1 changes the DACK output timing. 0: DMAC single address transfer through the DRAM/SDRAM is enabled only in full access mode 1: DMAC single address transfer through the DRAM/SDRAM is also enabled in fast-page access mode Rev.1.00 Jun. 07, 2006 Page 158 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Bit 4 3 2 1 0 Bit Name MCX1 MCX0 Initial Value 0 0 0 0 0 R/W R/W R R/W R/W R/W Description Reserved The initial value should not be changed. Multiplexed Address Bit Select Select the number of bits by which a row address multiplexed with a column address is shifted to the lower side. At the same time, these bits select row address bits compared during a burst access to the DRAM/SDRAM interface. 00: Shifted by 8 bits A23 to A8 are compared for 8-bit access space A23 to A9 are compared for 16-bit access space 01: Shifted by 9 bits A23 to A9 are compared for 8-bit access space A23 to A10 are compared for 16-bit access space 10: Shifted by 10 bits A23 to A10 are compared for 8-bit access space A23 to A11 are compared for 16-bit access space 11: Shifted by 11 bits A23 to A11 are compared for 8-bit access space A23 to A12 are compared for 16-bit access space Rev.1.00 Jun. 07, 2006 Page 159 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Bus cycle Tp Tr Tc1 Tc2 B Address RAS (When RAST = 0) RAS (When RAST = 1) LUCAS, LLCAS Row address Column address Figure 6.4 RAS Assertion Timing (Column Address Output for 2 cycles in Full Access Mode) 6.2.14 DRAM Access Control Register (DRACCR) DRACCR specifies the settings for the DRAM/SDRAM interface. Rewrite this register while the DRAM/SDRAM is not accessed. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 0 R 7 0 R 14 0 R 6 0 R 13 TPC1 0 R/W 5 0 R 12 TPC0 0 R/W 4 0 R 11 0 R 3 0 R 10 0 R 2 0 R 9 RCD1 0 R/W 1 0 R 8 RCD0 0 R/W 0 0 R Rev.1.00 Jun. 07, 2006 Page 160 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Bit 15, 14 13 12 Bit Name TPC1 TPC0 Initial Value All 0 0 0 R/W R R/W R/W Description Reserved The initial value should not be changed. Precharge Cycle Control Select the number of RAS precharge cycles on a normal access and a refresh cycle. 00: One cycle 01: Two cycles 10: Three cycles 11: Four cycles 11, 10 9 8 RCD1 RCD0 All 0 0 0 R R/W R/W Reserved The initial value should not be changed. RAS-CAS Wait Control Select the number of wait cycles inserted between RAS and CAS cycles. 00: No wait cycle inserted 01: One wait cycle inserted 10: Two wait cycles inserted 11: Three wait cycles inserted 7 to 0 All 0 R Reserved The initial value should not be changed. Rev.1.00 Jun. 07, 2006 Page 161 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.2.15 Synchronous DRAM Control Register (SDCR) SDCR specifies the settings for the SDRAM interface (when the DTYPE bit in DRAMCE is set to 1). Rewrite this register while the SDRAM is not accessed. When the SDRAM interface is not used, the initial value must not be changed. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 MRSE 0 R/W 7 CKSPE 0 R/W 14 0 R 6 0 R 13 0 R 5 0 R 12 0 R 4 0 R 11 0 R/W 3 0 R 10 0 R/W 2 0 R 9 0 R 1 0 R 8 0 R/W 0 TRWL 0 R/W Bit 15 Bit Name MRSE Initial Value 0 R/W R/W Description Mode Register Set Enable Enables the setting in the SDRAM mode register. See section 6.11.14, Setting SDRAM Mode Register. 0: Disables to set the SDRAM mode register 1: Enables to set the SDRAM mode register 14 to 12 All 0 R Reserved These bits are always read as 0. The initial value should not be changed. 11, 10 9 8 7 CKSPE 0 0 0 0 R/W R R/W R/W Reserved The initial value should not be changed. Reserved The initial value should not be changed. Clock Suspend Enable Enables the clock suspend mode in which read data output cycles are extended. Setting this bit to 1 extends cycles in which read data is output from SDRAM. 0: Disables the clock suspend mode 1: Enables the clock suspend mode Rev.1.00 Jun. 07, 2006 Page 162 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Bit 6 to 1 0 Bit Name TRWL Initial Value All 0 0 R/W R R/W Description Reserved The initial value should not be changed. Write-Precharge Delay Control Specifies the time until the precharge command is issued after the write command is issued to the SDRAM. Setting this bit to 1 inserts one wait cycle after the write command is issued. 0: No wait cycle inserted 1: One wait cycle inserted 6.2.16 Refresh Control Register (REFCR) REFCR specifies the refresh type for the DRAM/SDRAM interface. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 CMF 0 R/(W)* 7 RFSHE 0 R/W 14 CMIE 0 R/W 6 RLW2 0 R/W 13 RCW1 0 R/W 5 RLW1 0 R/W 12 RCW0 0 R/W 4 RLW0 0 R/W 11 0 R 3 SLFRF 0 R/W 10 RTCK2 0 R/W 2 TPCS2 0 R/W 9 RTCK1 0 R/W 1 TPCS1 0 R/W 8 RTCK0 0 R/W 0 TPCS0 0 R/W Note: * Only 0 can be written to this bit, to clear the flag. Rev.1.00 Jun. 07, 2006 Page 163 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Bit 15 Bit Name CMF Initial Value 0 R/W Description R/(W)* Compare Match Flag Indicates that the refresh timer counter (RTCNT) and refresh timer constant register (RTCOR) match. [Clearing conditions] * * * When 0 is written to this bit after this bit is read as 1 with RFSHE = 0 When CBR refresh is performed with RFSHE = 1 When RTCNT matches RTCOR [Setting condition] 14 CMIE 0 R/W Compare Match Interrupt Enable Enables or disables an interrupt request (CMIF) when the CMF flag is set to 1. This bit is effective when refresh control is not performed (RFSHE = 0). When refresh control is performed (RFSHE = 1), this bit is always cleared to 0. This bit cannot be modified. 13 to 12 RCW1 RCW0 0 0 R/W R/W CAS-RAS Wait Control Select the number of wait cycles inserted between the CAS asserted cycle and CAS asserted cycle during DRAM refresh. When the SDRAM space is selected, these bits do not affect operations although they can be read from or written to. 00: No wait cycle inserted 01: One wait cycle inserted 10: Two wait cycles inserted 11: Three wait cycles inserted 11 0 R Reserved The initial value should not be changed. Rev.1.00 Jun. 07, 2006 Page 164 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Bit 10 9 8 Bit Name RTCK2 RTCK1 RTCK0 Initial Value 0 0 0 R/W R/W R/W R/W Description Refresh Counter Clock Select Select the clock used to count up the refresh counter from the seven internal clocks generated by dividing the on-chip peripheral module clock (P). When the clock is selected, the refresh counter starts to count up. 000: Counting halted 001: Counts on P/2 001: Counts on P/8 001: Counts on P/32 001: Counts on P/128 001: Counts on P/512 001: Counts on P/2048 001: Counts on P/4096 7 RFSHE 0 R/W Refresh Control Enables or disables refresh control. When refresh control is disabled, the refresh timer can be used as the interval timer. In single-chip activation mode, the setting of this bit should be made after setting the EXPE bit in SYSCR to 1. For SYSCR, see section 3, MCU Operating Modes. 0: Refresh control enabled 1: Refresh control disabled 6 5 4 RLW2 RLW1 RLW0 0 0 0 R/W R/W R/W Refresh Cycle Wait Control Select the number of wait cycles during a CAS before RAS refresh cycle for the DRAM interface and an autorefresh cycle for the SDRAM interface. 000: No wait cycle inserted 001: One wait cycle inserted 010: Two wait cycles inserted 010: Three wait cycles inserted 010: Four wait cycles inserted 010: Five wait cycles inserted 010: Six wait cycles inserted 010: Seven wait cycles inserted Rev.1.00 Jun. 07, 2006 Page 165 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Bit 3 Bit Name SLFRF Initial Value 0 R/W R/W Description Self-Refresh Enable Selects the self-refresh mode for the DRAM/SDRAM interface when a transition to the software standby mode is made with this bit set to 1. To perform a refresh cycle by setting the RFSHE bit is set to 1, this bit is effective. To perform a self-refresh cycle when the SDRAM interface is selected, enable the CKE output by setting the OEE bit in DRAMCR. 0: Disables self-refresh 1: Enables self-refresh 2 1 0 TPS2 TPS1 TPS0 0 0 0 R/W R/W R/W Precharge Cycle Control during Self-Refresh Selects the number of precharge cycles immediately after a self-refresh cycle. The number of actual number of precharge cycles is the sum of the numbers indicated by these bits and bits TPC1 and TPC0. 000: No wait cycle inserted 001: One wait cycle inserted 010: Two wait cycles inserted 010: Three wait cycles inserted 010: Four wait cycles inserted 010: Five wait cycles inserted 010: Six wait cycles inserted 010: Seven wait cycles inserted Note: Only 0 can be written to this bit, to clear the flag. Rev.1.00 Jun. 07, 2006 Page 166 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.2.17 Refresh Timer Counter (RTCNT) RTCNT counts up on the internal clock selected by bits RTCS2 to RTCK0 in REFCR. When the RTCNT value matches the RTCOR value (compare match), the CMF flag in REFCR is set to 1 and RTCNT is initialized to H'00. At this time, when the RFSHE bit in REFCR is set to 1, a refresh cycle is generated. When the RFSHE bit is cleared to 0 and the CMIE bit in REFCR is set to 1, a compare match interrupt (CMI) is generated. Bit Bit Name Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 6 5 4 3 2 1 0 6.2.18 Refresh Time Constant Register (RTCOR) RTCOR specifies intervals at which a compare match for RTCOR and RTCNT is generated. The RTCOR value is always compared with the RTCNT value. When they match, the CMF flag in REFCR is set to 1 and RTCNT is initialized to H'00. Bit Bit Name Initial Value R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 7 6 5 4 3 2 1 0 Rev.1.00 Jun. 07, 2006 Page 167 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.3 Bus Configuration Figure 6.5 shows the internal bus configuration of this LSI. The internal bus of this LSI consists of the following three types. * Internal system bus A bus that connects the CPU, DTC, DMAC, on-chip RAM, on-chip ROM, internal peripheral bus, and external access bus. * Internal peripheral bus A bus that accesses registers in the bus controller, interrupt controller, and DMAC, and registers of peripheral modules such as SCI and timer. * External access cycle A bus that accesses external devices via the external bus interface. I synchronization CPU DTC On-chip RAM On-chip ROM Internal system bus Write data buffer Bus controller, interrupt controller, power-down controller DMAC Write data buffer External access bus Internal peripheral bus P synchronization Peripheral functions B synchronization External bus interface Figure 6.5 Internal Bus Configuration Rev.1.00 Jun. 07, 2006 Page 168 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.4 Multi-Clock Function and Number of Access Cycles The internal functions of this LSI operate synchronously with the system clock (I), the peripheral module clock (P), or the external bus clock (B). Table 6.1 shows the synchronization clock and their corresponding functions. Table 6.1 Synchronization Clocks and Their Corresponding Functions Function Name MCU operating mode Interrupt controller Bus controller CPU DTC DMAC Internal memory Clock pulse generator Power down control I/O ports TPU PPG TMR WDT SCI A/D D/A IIC2 USB External bus interface Synchronization Clock I P B The frequency of each synchronization clock (I, P, and B) is specified by the system clock control register (SCKCR) independently. For further details, see section 22, Clock Pulse Generator. There will be cases when P and B are equal to I and when P and B are different from I according to the SCKCR specifications. In any case, access cycles for internal peripheral functions and external space is performed synchronously with P and B, respectively. Rev.1.00 Jun. 07, 2006 Page 169 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) For example, in an external address space access where the frequency rate of I and B is n : 1, the operation is performed in synchronization with B. In this case, external 2-state access space is 2n cycles and external 3-state access space is 3n cycles (no wait cycles is inserted) if the number of access cycles is counted based on I. If the frequencies of I, P and B are different, the start of bus cycle may not synchronize with P or B according to the bus cycle initiation timing. In this case, clock synchronization cycle (Tsy) is inserted at the beginning of each bus cycle. For example, if an external address space access occurs when the frequency rate of I and B is n : 1, 0 to n-1 cycles of Tsy may be inserted. If an internal peripheral module access occurs when the frequency rate of I and P is m : 1, 0 to m-1 cycles of Tsy may be inserted. Figure 6.6 shows the external 2-state access timing when the frequency rate of I and B is 4 : 1. Figure 6.7 shows the external 3-state access timing when the frequency rate of I and B is 2 : 1. Rev.1.00 Jun. 07, 2006 Page 170 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Divided clock synchronization cycle Tsy I T1 T2 B Address CSn AS RD Read D15 to D8 D7 to D0 LHWR LLWR Write D15 to D8 D7 to D0 BS RD/WR Figure 6.6 System Clock: External Bus Clock = 4:1, External 2-State Access Rev.1.00 Jun. 07, 2006 Page 171 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Divided clock synchronization cycle Tsy I T1 T2 T3 B Address CSn AS RD Read D15 to D8 D7 to D0 LHWR LLWR Write D15 to D8 D7 to D0 BS RD/WR Figure 6.7 System Clock: External Bus Clock = 2:1, External 3-State Access Rev.1.00 Jun. 07, 2006 Page 172 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.5 6.5.1 External Bus Input/Output Pins Table 6.2 shows the pin configuration of the bus controller and table 6.3 shows the pin functions on each interface. Table 6.2 Name Bus cycle start Address strobe/ address hold Pin Configuration Symbol BS AS/AH I/O Output Output Function Signal indicating that the bus cycle has started * Strobe signal indicating that the basic bus, byte control SRAM, or burst ROM space is accessed and address output on address bus is enabled * RD Signal to hold the address during access to the address/data multiplexed I/O interface Read strobe Output Strobe signal indicating that the basic bus, byte control SRAM, burst ROM, or address/data multiplexed I/O space is being read * * Signal indicating the input or output direction Write enable signal of the SRAM during access to the byte control SRAM space Read/write RD/WR Output Low-high write/ lower-upper byte select LHWR/LUB Output * Strobe signal indicating that the basic bus, burst ROM, or address/data multiplexed I/O space is written to, and the upper byte (D15 to D8) of data bus is enabled * Strobe signal indicating that the byte control SRAM space is accessed, and the upper byte (D15 to D8) of data bus is enabled Low-low write/ lower-lower byte select LLWR/LLB Output * Strobe signal indicating that the basic bus, burst ROM, or address/data multiplexed I/O space is written to, and the lower byte (D7 to D0) of data bus is enabled * Strobe signal indicating that the byte control SRAM space is accessed, and the lower byte (D7 to D0) of data bus is enabled Rev.1.00 Jun. 07, 2006 Page 173 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Name Chip select 0 Chip select 1 Chip select 2 Chip select 3 Chip select 4 Chip select 5 Chip select 6 Chip select 7 Row address strobe Symbol CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS7 RAS I/O Output Output Output Output Output Output Output Output Output Function Strobe signal indicating that area 0 is selected Strobe signal indicating that area 1 is selected Strobe signal indicating that area 2 is selected Strobe signal indicating that area 3 is selected Strobe signal indicating that area 4 is selected Strobe signal indicating that area 5 is selected Strobe signal indicating that area 6 is selected Strobe signal indicating that area 7 is selected * * Column address strobe Write enable CAS WE Output Output Row address strobe signal when area 2 is specified as DRAM space Row address strobe signal when area 2 is specified as SDRAM space Column address strobe signal when area 2 is specified as SDRAM space * * Write enable signal for DRAM Write enable signal when area 2 is specified as SDRAM space Lower-upper-column address strobe signal for 32bit DRAM Upper-column address strobe signal for 16-bit DRAM Lower-upper-data mask enable signal for 32-bit SDRAM Upper-data mask enable signal for 16-bit SDRAM Lower-lower-column address strobe signal for 32bit DRAM Lower-column address strobe signal for 16-bit DRAM Column address strobe signal for 8-bit DRAM Lower-lower-data mask enable signal for 32-bit SDRAM Lower-data mask enable signal for 16-bit SDRAM Data mask enable signal for 8-bit SDRAM Lower-upper-column address strobe/lower-upper-data mask enable LUCAS/ DQMLU Output * * * * Lower-lower-column address strobe/lower-lower-data mask enable LLCAS/ DQMLL Output * * * * * * Rev.1.00 Jun. 07, 2006 Page 174 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Name Output enable/clock enable Symbol OE/CKE I/O Output Function * * SDRAM Wait Bus request Bus request acknowledge Bus request output SD WAIT BREQ BACK BREQO Output Input Input Output Output Output enable signal for DRAM Clock enable signal for SDRAM SDRAM dedicated clock Wait request signal when accessing external address space Request signal for release of bus to external bus master Acknowledge signal indicating that bus has been released to external bus master External bus request signal used when internal bus master accesses external address space in the external-bus released state Data acknowledge signal for DMAC_3 single address transfer Data acknowledge signal for DMAC_2 single address transfer Data acknowledge signal for DMAC_1 single address transfer Data acknowledge signal for DMAC_0 single address transfer External bus clock Data transfer acknowledge 3 (DMAC_3) Data transfer acknowledge 2 (DMAC_2 Data transfer acknowledge 1 (DMAC_1) Data transfer acknowledge 0 (DMAC_0) External bus clock DACK3 DACK2 DACK1 DACK0 B Output Output Output Output Output Rev.1.00 Jun. 07, 2006 Page 175 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Table 6.3 Pin Functions in Each Interface Byte Control SRAM 16 O O O O O O O O O O O O O O O O Address/Data Initial State Single- Basic Bus 16 O O O O O O O O O O O O O O O O 8 O O O O O O O O O O O O O O O Burst ROM 16 O O O O O O O O O O 8 O O O O O O O O O Multiplexed I/O Pin Name B CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS7 BS RD/WR AS AH RD LHWR/LUB LLWR/LLB WAIT 16 8 Chip 16 O O O O O O O O O O O O O 8 O O O O O O O O O O O O Remarks Output Output Output Output Output Output Output Output Output Output Output Output Controlled by WAITE [Legend] O: Used as a bus control signal : Not used as a bus control signal (used as a port input when initialized) Rev.1.00 Jun. 07, 2006 Page 176 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.5.2 Area Division The bus controller divides the 16-Mbyte address space into eight areas, and performs bus control for the external address space in area units. Chip select signals (CS0 to CS7) can be output for each area. Figure 6.8 shows an area division of the 16-Mbyte address space. For details on address map, see section 3, MCU Operating Modes. H'000000 Area 0 (2 Mbytes) H'1FFFFF H'200000 Area 1 (2 Mbytes) H'3FFFFF H'400000 Area 2 (8 Mbytes) H'BFFFFF H'C00000 Area 3 (2 Mbytes) H'DFFFFF H'E00000 Area 4 (1 Mbyte) H'EFFFFF H'F00000 Area 5 (1 Mbyte - 8 kbytes) H'FFDFFF H'FFE000 Area 6 H'FFFEFF (8 kbytes - 256 bytes) H'FFFF00 Area 7 H'FFFFFF (256 bytes) 16-Mbyte space Figure 6.8 Address Space Area Division Rev.1.00 Jun. 07, 2006 Page 177 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.5.3 Chip Select Signals This LSI can output chip select signals (CS0 to CS7) for areas 0 to 7. The signal outputs low when the corresponding external address space area is accessed. Figure 6.9 shows an example of CSn (n = 0 to 7) signal output timing. Enabling or disabling of CSn signal output is set by the port function control register (PFCR). For details, see section 9.3, Port Function Controller. In on-chip ROM disabled extended mode, pin CS0 is placed in the output state after a reset. Pins CS1 to CS7 are placed in the input state after a reset and so the corresponding PFCR bits should be set to 1 when outputting signals CS1 to CS7. In on-chip ROM enabled extended mode, pins CS0 to CS7 are all placed in the input state after a reset and so the corresponding PFCR bits should be set to 1 when outputting signals CS0 to CS7. The PFCR can specify multiple CS outputs for a pin. If multiple CSn outputs are specified for a single pin by the PFCR, CS to be output are generated by mixing all the CS signals. In this case, the settings for the external bus interface areas in which the CSn signals are output to a single pin should be the same. Figure 6.10 shows the signal output timing when the CS signals to be output to areas 5 and 6 are output to the same pin. Bus cycle T1 B Address bus CSn External address of area n T2 T3 Figure 6.9 CSn Signal Output Timing (n = 0 to 7) Rev.1.00 Jun. 07, 2006 Page 178 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Area 5 access B Area 6 access CS5 CS6 Output waveform Address bus Area 5 access Area 6 access Figure 6.10 Timing When CS Signal is Output to the Same Pin 6.5.4 External Bus Interface The type of the external bus interfaces, bus width, endian format, number of access cycles, and strobe assert/negate timings can be set for each area in the external address space. The bus width and the number of access cycles for both on-chip memory and internal I/O registers are fixed, and are not affected by the external bus settings. (1) Type of External Bus Interface Four types of external bus interfaces are provided and can be selected in area units. Table 6.4 shows each interface name, description, area name to be set for each interface. Table 6.5 shows the areas that can be specified for each interface. The initial state of each area is a basic bus interface. Table 6.4 Interface Basic interface Byte control SRAM interface Burst ROM interface Address/data multiplexed I/O interface Interface Names and Area Names Description Directly connected to ROM and RAM Directly connected to byte SRAM with byte control pin Directly connected to the ROM that allows page access Directly connected to the peripheral LSI that requires address and data multiplexing Area Name Basic bus space Byte control SRAM space Burst ROM space Address/data multiplexed I/O space Rev.1.00 Jun. 07, 2006 Page 179 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Table 6.5 Areas Specifiable for Each Interface Related Registers SRAMCR Areas 0 O O BROMCR MPXCR O 1 O O O 2 O O 3 O O O 4 O O O 5 O O O 6 O O O 7 O O O Interface Basic interface Byte control SRAM interface Burst ROM interface Address/data multiplexed I/O interface (2) Bus Width A bus width of 8 or 16 bits can be selected with ABWCR. An area for which an 8-bit bus is selected functions as an 8-bit access space and an area for which a 16-bit bus is selected functions as a 16-bit access space. In addition, the bus width of address/data multiplexed I/O space is 8 bits or 16 bits, and the bus width for the byte control SRAM space is 16 bits. The initial state of the bus width is specified by the operating mode. If all areas are designated as 8-bit access space, 8-bit bus mode is set; if any area is designated as 16-bit access space, 16-bit bus mode is set. (3) Endian Format Though the endian format of this LSI is big endian, data can be converted into little endian format when reading or writing to the external address space. Areas 7 to 2 can be specified as either big endian or little endian format by the LE7 to LE2 bits in ENDIANCR. The initial state of each area is the big endian format. Note that the data format for the areas used as a program area or a stack area should be big endian. Rev.1.00 Jun. 07, 2006 Page 180 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) (4) (a) Number of Access Cycles Basic Bus Interface The number of access cycles in the basic bus interface can be specified as two or three cycles by the ASTCR. An area specified as 2-state access is specified as 2-state access space; an area specified as 3-state access is specified as 3-state access space. For the 2-state access space, a wait cycle insertion is disabled. For the 3-state access space, a program wait (0 to 7 cycles) specified by WTCRA and WTCRB or an external wait by WAIT can be inserted. Number of access cycles in the basic bus interface = number of basic cycles (2, 3) + number of program wait cycles (0 to 7) + number of CS extension cycles (0, 1, 2) [+ number of external wait cycles by the WAIT pin] Assertion period of the chip select signal can be extended by CSACR. (b) Byte Control SRAM Interface The number of access cycles in the byte control SRAM interface is the same as that in the basic bus interface. Number of access cycles in byte control SRAM interface = number of basic cycles (2, 3) + number of program wait cycles (0 to 7) + number of CS extension cycles (0, 1, 2) [+ number of external wait cycles by the WAIT pin] (c) Burst ROM Interface The number of access cycles at full access in the burst ROM interface is the same as that in the basic bus interface. The number of access cycles in the burst access can be specified as one to eight cycles by the BSTS bit in BROMCR. Number of access cycles in the burst ROM interface = number of basic cycles (2, 3) + number of program wait cycles (0 to 7) + number of CS extension cycles (0, 1) [+number of external wait cycles by the WAIT pin] + number of burst access cycles (1 to 8) x number of burst accesses (0 to 63) Rev.1.00 Jun. 07, 2006 Page 181 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) (d) Address/data multiplexed I/O interface The number of access cycles in data cycle of the address/data multiplexed I/O interface is the same as that in the basic bus interface. The number of access cycles in address cycle can be specified as two or three cycles by the ADDEX bit in MPXCR. Number of access cycles in the address/data multiplexed I/O interface = number of address output cycles (2, 3) + number of data output cycles (2, 3) + number of program wait cycles (0 to 7) + number of CS extension cycles (0, 1, 2) [+number of external wait cycles by the WAIT pin] (e) DRAM Interface In the DRAM interface, the numbers of precharge cycles, row address output cycles, and column address output cycles can be specified. The number of precharge cycles can be specified as one to four cycles by bits TPC1 and TPC0 in DRACCR. The number of row address output cycles can be specified as one to four cycles by bits RCD1 and RCD0 in DRACCR. The number of column address output cycles can be specified as two or three cycles by the CAST bit in DRAMCR. For the column address output cycle, program wait (0 to 7 cycles) specified by WTCRB or external wait by WAIT can be inserted. Number of access cycles in the DRAM interface = number of precharge cycles (1 to 4) + number of row address output cycles (1 to 4) + number of column address output cycles (2 or 3) + number of program wait cycles (0 to 7) [+number of external wait cycles by the WAIT pin] (f) SDRAM Interface In the SDRAM interface, the numbers of precharge cycles, row address output cycles, and column address output cycles, as well as clock suspend and write-precharge delay, can be specified by DRACCR and WTCRB. The number of precharge cycles can be specified as one to four cycles by bits TPC1 and TPC0 in DRACCR. The number of row address output cycles can be specified as one to four cycles by bits RCD1 and RCD0 in DRACCR. The number of column address output cycles during read access can be specified as two to four cycles by bits W21 and W20 in WTCRB. The cycles for clock suspend and write-precharge delay can be inserted by bits CKSPE and TRWL in SDCR. Rev.1.00 Jun. 07, 2006 Page 182 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Number of access cycles in the SDRAM interface = number of precharge cycles (1 to 4) + number of row address output cycles (1 to 4) + number of column address output cycles (read: 2 to 4, write: 2) + number of clock suspend cycles (only read: 0 or 1) + number of write precharge delay cycles (only write: 0 or 1) Table 6.6 lists the number of access cycles for each interface. Table 6.6 Basic bus interface Number of Access Cycles = = Th [0,1] Th [0,1] Th [0,1] Th [0,1] Th [0,1] Th [0,1] +Th [0,1] +Th [0,1] +Tr [1] +T1 [1] +T1 [1] +T1 [1] +T1 [1] +T1 [1] +T1 [1] +T1 [1] +T1 [1] +Trw [0 to 3] +T2 [1] +Tpw +T2 [0 to 7] [1] +T2 [1] +Tpw +T2 [0 to 7] [1] +T2 [1] +Tpw +T2 [0 to 7] [1] +T2 [1] +Tpw +T2 [0 to 7] [1] +Tpw +TC1 [0 to 7] [1] +Tpw TC1 [0 to 7] [1] +TRcw +TRc1 [0 to 7] [1] Software + standby mode [1+s] +Tc1 [1] +Tc1 [1] +Tc1 [1] Tc1 [1] Tc1 [1] +Tc1 +Trw [1] [0 to 3] Tc1 [1] +Tc1 +Trw [1] [0 to 3] Tc1 [1] +TRcw +TRc1 [0 to 7] [1] Software + standby mode [1+s] +Trw [0 to 3] +Trw [0 to 3] +Trw [0 to 3] +Tt [0,1] +Tt [0,1] +Tt [0,1] +Tt [0,1] +Tb [(1 to 8) x m] +Tb [(1 to 8) x m] +Tt [0,1] +Tt [0,1] +Tc3 [0,1] +Tc3 [0,1] [2 to 4] [3 to 12+n] [2 to 4] [3 to 12+n] [(2 to 3)+(1 to 8) x m] [(2 to 11+n)+(1 to 8) x m] [4 to 7] [5 to 15+n] [4 to 18+n] [2 to 10+n] [4 to 17] +TRc3 [1] +TRc4 [1] +TRp [0 to 7] +Tc2 [1] +Tc2 [1] +Tc2 [1] [1] +Tc2 [1] +Tc2 [1] +Tc2 [1] +Tc2 [1] +Tc2 [1] +Tc2 [1] [5 to 18+s] +Trwl [0,1] [4 to 11] [5 to 14] +Trwl [0,1] [4 to 11] [3 to 6] [2 to 3] +Trwl [0,1] [5 to 44] [3 to 36] +Tcb [0 to 31] +Tcb [0 to 31] [4 to 41] [2 to 33] [4 to 14] +TRc3 [1] +TRp [0 to 7] [5 to 15+s] +Ttw [n] +T3 [1] Byte-control SRAM interface = = +Ttw [n] +T3 [1] Burst ROM interface = = +Ttw [n] +T3 [1] Address/data multiplexed I/O interface DRAM interface Full access Fast page Refresh Self-refresh =Tma [2,3] =Tma [2,3] =Tp [1 to 4] = =TRp [1 to 4] =TRp [1 to 4] = = = = = = = SDRAM interface Setting mode register Full access (read) Full access (write) Page access (read) Page access (write) Cluster transfer (read) +TRrw [0 to 3] +TRrw [0 to 3] Tp [1 to 4] Tp [1 to 4] Tp [1 to 4] +TRr [1] +TRr [1] +Tr [1] +Tr [1] +Tr [1] +Ttw [n] +Ttw [n] +Ttw [n] +TRc2 [1] +T3 [1] +Tc2 [1] +Tc2 [1] +Tcl [1 to 3] +Tsp [0,1] +Tcl [1 to 3] +Tsp [0,1] Tp [1 to 4] +Tr [1] +Tcb +Tcl [0 to 31] [1 to 3] +Tcb +Tcl [0 to 31] [1 to 3] Cluster transfer (write) = = Tp [1 to 4] +Tr [1] Refresh Self-refresh = = TRp [1 to 4] TRp [1 to 4] +TRr [1] +TRr [1] +TRc2 [1] +TRc2 [1] [Legend] Number enclosed by bracket: Number of access cycles n: Pin wait (0 to ) m: Number of burst accesses (0 to 63) s: Time for a transition to or from software standby mode Rev.1.00 Jun. 07, 2006 Page 183 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) (5) Strobe Assert/Negate Timings The assert and negate timings of the strobe signals can be modified as well as number of access cycles. * Read strobe (RD) in the basic bus interface * Chip select assertion period extension cycles in the basic bus interface * Data transfer acknowledge (DACK3 to DACK0) output for DMAC single address transfers 6.5.5 (1) Area and External Bus Interface Area 0 Area 0 includes on-chip ROM. All of area 0 is used as external address space in on-chip ROM disabled extended mode, and the space excluding on-chip ROM is external address space in onchip ROM enabled extended mode. When area 0 external address space is accessed, the CS0 signal can be output. Either of the basic bus interface, byte control SRAM interface, or burst ROM interface can be selected for area 0 by bit BSRM0 in BROMCR and bit BCSEL0 in SRAMCR. Table 6.7 shows the external interface of area 0. Table 6.7 Area 0 External Interface Register Setting Interface Basic bus interface Byte control SRAM interface Burst ROM interface Setting prohibited BSRM0 of BROMCR 0 0 1 1 BCSEL0 of SRAMCR 0 1 0 1 Rev.1.00 Jun. 07, 2006 Page 184 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) (2) Area 1 n externally extended mode, all of area 1 is external address space. In on-chip ROM enabled extended mode, the space excluding on-chip ROM is external address space. When area 1 external address space is accessed, the CS1 signal can be output. Either of the basic bus interface, byte control SRAM, or burst ROM interface can be selected for area 1 by bit BSRM1 in BROMCR and bit BCSEL1 in SRAMCR. Table 6.8 shows the external interface of area 1. Table 6.8 Area 1 External Interface Register Setting Interface Basic bus interface Byte control SRAM interface Burst ROM interface Setting prohibited BSRM1 of BROMCR 0 0 1 1 BCSEL1 of SRAMCR 0 1 0 1 (3) Area 2 In externally extended mode, all of area 2 is external address space. When area 2 external address space is accessed, the CS2 signal can be output. Either the basic bus interface, byte-control SRAM interface, DRAM interface, or SDRAM interface can be selected for area 2 by the DRAME and DTYPE bits in DRAMCR and bit BCSEL2 in SRAMCR. Table 6.9 shows the external interface of area 2. Table 6.9 Area 2 External Interface DRAME in DRAMCR 0 0 1 1 1 Register Setting DTYPE in DRAMCR Don't care Don't care 0 1 Don't care BCSEL2 in SRAMCR 0 1 0 0 1 Interface Basic bus interface Byte-control SRAM interface DRAM interface SDRAM interface Setting prohibited Rev.1.00 Jun. 07, 2006 Page 185 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) (4) Area 3 In externally extended mode, all of area 3 is external address space. When area 3 external address space is accessed, the CS3 signal can be output. Either of the basic bus interface, byte control SRAM interface, or address/data multiplexed I/O interface can be selected for area 3 by bit MPXE3 in MPXCR and bit BCSEL3 in SRAMCR. Table 6.10 shows the external interface of area 3. Table 6.10 Area 3 External Interface Register Setting Interface Basic bus interface Byte control SRAM interface Address/data multiplexed I/O interface Setting prohibited MPXE3 of MPXCR 0 0 1 1 BCSEL3 of SRAMCR 0 1 0 1 (5) Area 4 In externally extended mode, all of area 4 is external address space. When area 4 external address space is accessed, the CS4 signal can be output. Either of the basic bus interface, byte control SRAM interface, or address/data multiplexed I/O interface can be selected for area 4 by bit MPXE4 in MPXCR and bit BCSEL4 in SRAMCR. Table 6.11 shows the external interface of area 4. Table 6.11 Area 4 External Interface Register Setting Interface Basic bus interface Byte control SRAM interface Address/data multiplexed I/O interface Setting prohibited MPXE4 of MPXCR 0 0 1 1 BCSEL4 of SRAMCR 0 1 0 1 Rev.1.00 Jun. 07, 2006 Page 186 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) (6) Area 5 Area 5 includes the on-chip RAM and access prohibited spaces. In external extended mode, area 5, other than the on-chip RAM and access prohibited spaces, is external address space. Note that the on-chip RAM is enabled when the RAME bit in SYSCR are set to 1. If the RAME bit in SYSCR is cleared to 0, the on-chip RAM is disabled and the corresponding addresses are an external address space. For details, see section 3, MCU Operating Modes. When area 5 external address space is accessed, the CS5 signal can be output. Either of the basic bus interface, byte control SRAM interface, or address/data multiplexed I/O interface can be selected for area 5 by the MPXE5 bit in MPXCR and the BCSEL5 bit in SRAMCR. Table 6.12 shows the external interface of area 5. Table 6.12 Area 5 External Interface Register Setting Interface Basic bus interface Byte control SRAM interface Address/data multiplexed I/O interface Setting prohibited MPXE5 of MPXCR 0 0 1 1 BCSEL5 of SRAMCR 0 1 0 1 Rev.1.00 Jun. 07, 2006 Page 187 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) (7) Area 6 Area 6 includes internal I/O registers. In external extended mode, area 6 other than on-chip I/O register area is external address space. When area 6 external address space is accessed, the CS6 signal can be output. Either of the basic bus interface, byte control SRAM interface, or address/data multiplexed I/O interface can be selected for area 6 by the MPXE6 bit in MPXCR and the BCSEL6 bit in SRAMCR. Table 6.13 shows the external interface of area 6. Table 6.13 Area 6 External Interface Register Setting Interface Basic bus interface Byte control SRAM interface Address/data multiplexed I/O interface Setting prohibited MPXE6 of MPXCR 0 0 1 1 BCSEL6 of SRAMCR 0 1 0 1 (8) Area 7 Area 7 includes internal I/O registers. In external extended mode, area 7 other than internal I/O register area is external address space. When area 7 external address space is accessed, the CS7 signal can be output. Either of the basic bus interface, byte control SRAM interface, or address/data multiplexed I/O interface can be selected for area 7 by the MPXE7 bit in MPXCR and the BCSEL7 bit in SRAMCR. Table 6.14 shows the external interface of area 7. Table 6.14 Area 7 External Interface Register Setting Interface Basic bus interface Byte control SRAM interface Address/data multiplexed I/O interface Setting prohibited MPXE7 of MPXCR 0 0 1 1 BCSEL7 of SRAMCR 0 1 0 1 Rev.1.00 Jun. 07, 2006 Page 188 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.5.6 Endian and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and controls whether the upper byte data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space), the data size, and endian format when accessing external address space. (1) 8-Bit Access Space With the 8-bit access space, the lower byte data bus (D7 to D0) is always used for access. The amount of data that can be accessed at one time is one byte: a word access is performed as two byte accesses, and a longword access, as four byte accesses. Figures 6.11 and 6.12 illustrate data alignment control for the 8-bit access space. Figure 6.11 shows the data alignment when the data endian format is specified as big endian. Figure 6.12 shows the data alignment when the data endian format is specified as little endian. Strobe signal LHWR/LUB RD LLWR/LLB Data Size Byte Word Access Address n Access Count 1 Bus Cycle 1st 1st Data Size Byte Byte Byte Byte Byte Byte Byte D15 Data bus D8 D7 7 15 7 31 23 15 7 D0 0 8 0 24 16 8 0 n n 2 2nd 1st 2nd 3rd 4th Longword 4 Figure 6.11 Access Sizes and Data Alignment Control for 8-Bit Access Space (Big Endian) Rev.1.00 Jun. 07, 2006 Page 189 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Strobe signal LHWR/LUB RD LLWR/LLB Data Size Byte Word Access Address n n n Access Count 1 2 Bus Cycle 1st 1st 2nd Data Size Byte Byte Byte Byte Byte Byte Byte D15 Data bus D8 D7 7 7 15 7 15 23 31 D0 0 0 8 0 8 16 24 Longword 4 1st 2nd 3rd 4th Figure 6.12 Access Sizes and Data Alignment Control for 8-Bit Access Space (Little Endian) (2) 16-Bit Access Space With the 16-bit access space, the upper byte data bus (D15 to D8) and lower byte data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word. Figures 6.13 and 6.14 illustrate data alignment control for the 16-bit access space. Figure 6.13 shows the data alignment when the data endian format is specified as big endian. Figure 6.14 shows the data alignment when the data endian format is specified as little endian. In big endian, byte access for an even address is performed by using the upper byte data bus and byte access for an odd address is performed by using the lower byte data bus. In little endian, byte access for an even address is performed by using the lower byte data bus, and byte access for an odd address is performed by using the third byte data bus. Rev.1.00 Jun. 07, 2006 Page 190 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Strobe signal LHWR/LUB LLWR/LLB RD Access Size Byte Word Access Address Even (2n) Odd (2n+1) Even (2n) Odd (2n+1) Access Count 1 1 1 2 Bus Cycle 1st 1st 1st 1st 2nd Data Size Byte Byte Word Byte Byte Word Word Byte Word Byte D15 7 Data bus D8 D7 0 7 D0 0 0 8 15 87 15 7 31 15 0 24 23 87 31 16 0 24 8 Longword Even (2n) Odd (2n+1) 2 1st 2nd 3 1st 2nd 3rd 23 7 16 15 0 Figure 6.13 Access Sizes and Data Alignment Control for 16-Bit Access Space (Big Endian) Strobe signal LHWR/LUB LLWR/LLB RD Access Size Byte Word Access Address Even (2n) Odd (2n+1) Even (2n) Odd (2n+1) Access Count 1 1 1 2 Bus Cycle 1st 1st 1st 1st 2nd Data Size Byte Byte Word Byte Byte Word Word Byte Word Byte D15 Data bus D8 D7 7 D0 0 7 15 7 0 87 0 15 8 0 16 0 Longword Even (2n) Odd (2n+1) 2 1st 2nd 15 31 7 23 87 24 23 0 16 15 31 3 1st 2nd 3rd 8 24 Figure 6.14 Access Sizes and Data Alignment Control for 16-Bit Access Space (Little Endian) Rev.1.00 Jun. 07, 2006 Page 191 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.6 Basic Bus Interface The basic bus interface can be connected directly to the ROM and SRAM. The bus specifications can be specified by the ABWCR, ASTCR, WTCRA, WTCRB, RDNCR, CSACR, and ENDIANCR. 6.6.1 Data Bus Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and controls whether the upper byte data bus (D15 to D8) or lower byte data bus (D7 to D0) is used according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space), the data size, and endian format when accessing external address space,. For details, see section 6.5.6, Endian and Data Alignment. 6.6.2 I/O Pins Used for Basic Bus Interface Table 6.15 shows the pins used for basic bus interface. Table 6.15 I/O Pins for Basic Bus Interface Name Bus cycle start Address strobe Read strobe Read/write Low-high write Low-low write Chip select 0 to 7 Wait Note: * Symbol BS AS* RD RD/WR LHWR LLWR I/O Output Output Output Output Output Output Function Signal indicating that the bus cycle has started Strobe signal indicating that an address output on the address bus is valid during access Strobe signal indicating the read access Signal indicating the data bus input or output direction Strobe signal indicating that the upper byte (D15 to D8) is valid during write access Strobe signal indicating that the lower byte (D7 to D0) is valid during write access Strobe signal indicating that the area is selected Wait request signal used when an external address space is accessed CS0 to CS7 Output WAIT Input When the address/data multiplexed I/O is selected, this pin only functions as the AH output and does not function as the AS output. Rev.1.00 Jun. 07, 2006 Page 192 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.6.3 Basic Timing This section describes the basic timing when the data is specified as big endian. (1) 16-Bit 2-State Access Space Figures 6.15 to 6.17 show the bus timing of 16-bit 2-state access space. When accessing 16-bit access space, the upper byte data bus (D15 to D8) is used for even addresses access, and the lower byte data bus (D7 to D0) is used for odd addresses. No wait cycles can be inserted. Bus cycle T1 B Address T2 CSn AS RD Read D15 to D8 D7 to D0 LHWR LLWR Valid Invalid High level Valid Write D15 to D8 D7 to D0 BS RD/WR DACK Notes: 1. n = 0 to 7 2. When RDNn = 0 3. When DKC = 0 High-Z Figure 6.15 16-Bit 2-State Access Space Bus Timing (Byte Access for Even Address) Rev.1.00 Jun. 07, 2006 Page 193 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Bus cycle T1 B Address CSn AS RD Read D15 to D8 D7 to D0 Invalid T2 Valid LHWR LLWR D15 to D8 D7 to D0 High level Write High-Z Valid BS RD/WR DACK Notes: 1. n = 0 to 7 2. When RDNn = 0 3. When DKC = 0 Figure 6.16 16-Bit 2-State Access Space Bus Timing (Byte Access for Odd Address) Rev.1.00 Jun. 07, 2006 Page 194 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Bus cycle T1 B T2 Address CSn AS RD Read D15 to D8 D7 to D0 Valid Valid LHWR LLWR Write D15 to D8 D7 to D0 Valid Valid BS RD/WR DACK Notes: 1. n = 0 to 7 2. When RDNn = 0 3. When DKC = 0 Figure 6.17 16-Bit 2-State Access Space Bus Timing (Word Access for Even Address) Rev.1.00 Jun. 07, 2006 Page 195 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) (2) 16-Bit 3-State Access Space Figures 6.18 to 6.20 show the bus timing of 16-bit 3-state access space. When accessing 16-bit access space, the upper byte data bus (D15 to D8) is used for even addresses, and the lower byte data bus (D7 to D0) is used for odd addresses. Wait cycles can be inserted. Bus cycle T1 B Address CSn AS RD Read D15 to D8 D7 to D0 LHWR LLWR Write D15 to D8 D7 to D0 High-Z BS RD/WR DACK Notes: 1. n = 0 to 7 2. When RDNn = 0 3. When DKC = 0 High level Valid Valid Invalid T2 T3 Figure 6.18 16-Bit 3-State Access Space Bus Timing (Byte Access for Even Address) Rev.1.00 Jun. 07, 2006 Page 196 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Bus cycle T1 B T2 T3 Address CSn AS RD Read D15 to D8 D7 to D0 LHWR High level Write LLWR Invalid Valid D15 to D8 D7 to D0 High-Z Valid BS RD/WR DACK Notes: 1. n = 0 to 7 2. When RDNn = 0 3. When DKC = 0 Figure 6.19 16-Bit 3-State Access Space Bus Timing (Word Access for Odd Address) Rev.1.00 Jun. 07, 2006 Page 197 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Bus cycle T1 B T2 T3 Address CSn AS RD Read D15 to D8 D7 to D0 LHWR LLWR Write D15 to D8 D7 to D0 Valid Valid Valid Valid BS RD/WR DACK Notes: 1. n = 0 to 7 2. When RDNn = 0 3. When DKC = 0 Figure 6.20 16-Bit 3-State Access Space Bus Timing (Word Access for Even Address) Rev.1.00 Jun. 07, 2006 Page 198 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.6.4 Wait Control This LSI can extend the bus cycle by inserting wait cycles (Tw) when the external address space is accessed. There are two ways of inserting wait cycles: program wait (Tpw) insertion and pin wait (Ttw) insertion using the WAIT pin. (1) Program Wait Insertion From 0 to 7 wait cycles can be inserted automatically between the T2 state and T3 state for 3-state access space, according to the settings in WTCRA and WTCRB. (2) Pin Wait Insertion For 3-state access space, when the WAITE bit in BCR1 is set to 1 and the corresponding ICR bit is set to 1, wait input by means of the WAIT pin is enabled. When the external address space is accessed in this state, a program wait (Tpw) is first inserted according to the WTCRA and WTCRB settings. If the WAIT pin is low at the falling edge of B in the last T2 or Tpw cycle, another Ttw cycle is inserted until the WAIT pin is brought high. The pin wait insertion is effective when the Tw cycles are inserted to seven cycles or more, or when the number of Tw cycles to be inserted is changed according to the external devices. The WAITE bit is common to all areas. For details on ICR, see section 9, I/O Ports. Rev.1.00 Jun. 07, 2006 Page 199 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Figure 6.21 shows an example of wait cycle insertion timing. After a reset, the 3-state access is specified, the program wait is inserted for seven cycles, and the WAIT input is disabled. Wait by program Wait by WAIT pin wait Tpw Ttw Ttw T1 B T2 T3 WAIT Address CSn AS RD Read Data bus Read data LHWR, LLWR Write Data bus Write data BS RD/WR Notes: 1. Upward arrows indicate the timing of WAIT pin sampling. 2. n = 0 to 7 3. When RDNn = 0 Figure 6.21 Example of Wait Cycle Insertion Timing Rev.1.00 Jun. 07, 2006 Page 200 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.6.5 Read Strobe (RD) Timing The read strobe timing can be modified in area units by setting bits RDN7 to RDN0 in RDNCR to 1. Note that the RD timing with respect to the DACK rising edge will change if the read strobe timing is modified by setting RDNn to 1 when the DMAC is used in the single address mode. Figure 6.22 shows an example of timing when the read strobe timing is changed in the basic bus 3state access space. Bus cycle T1 T2 T3 B Address bus CSn AS RD RDNn = 0 Data bus RD RDNn = 1 Data bus BS RD/WR DACK Notes: 1. n = 0 to 7 2. When DKC = 0 Figure 6.22 Example of Read Strobe Timing Rev.1.00 Jun. 07, 2006 Page 201 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.6.6 Extension of Chip Select (CS) Assertion Period Some external I/O devices require a setup time and hold time between address and CS signals and strobe signals such as RD, LHWR, and LLWR. Settings can be made in CSACR to insert cycles in which only the CS, AS, and address signals are asserted before and after a basic bus space access cycle. Extension of the CS assertion period can be set in area units. With the CS assertion extension period in write access, the data setup and hold times are less stringent since the write data is output to the data bus. Figure 6.23 shows an example of the timing when the CS assertion period is extended in basic bus 3-state access space. Both extension cycle Th inserted before the basic bus cycle and extension cycle Tt inserted after the basic bus cycle, or only one of these, can be specified for individual areas. Insertion or noninsertion can be specified for the Th cycle with the upper eight bits (CSXH7 to CSXH0) in CSACR, and for the Tt cycle with the lower eight bits (CSXT7 to CSXT0). Rev.1.00 Jun. 07, 2006 Page 202 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Bus cycle Th B T1 T2 T3 Tt Address CSn AS RD Read Data bus LHWR, LLWR Write Data bus Write data Read data BS RD/WR DACK Notes: 1. n = 0 to 7 2. When DKC = 0 Figure 6.23 Example of Timing when Chip Select Assertion Period is Extended Rev.1.00 Jun. 07, 2006 Page 203 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.6.7 DACK Signal Output Timing For DMAC single address transfers, the DACK signal assert timing can be modified by using the DKC bit in BCR1. Figure 6.24 shows the DACK signal output timing. Setting the DKC bit to 1 asserts the DACK signal a half cycle earlier. Bus cycle T1 T2 B Address bus CSn AS RD Read Data bus Read data LHWR, LLWR Write Data bus BS RD/WR Write data DKC = 0 DACK DKC = 1 Notes: 1. n = 7 to 0 2. RDNn = 0 Figure 6.24 DACK Signal Output Timing Rev.1.00 Jun. 07, 2006 Page 204 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.7 Byte Control SRAM Interface The byte control SRAM interface is a memory interface for outputting a byte select strobe during a read or a write bus cycle. This interface has 16-bit data input/output pins and can be connected to the SRAM that has the upper byte select and the lower byte select strobes such as UB and LB. The operation of the byte control SRAM interface is the same as the basic bus interface except that: the byte select strobes (LUB and LLB) are output from the write strobe output pins (LHWR and LLWR), respectively; the read strobe (RD) negation timing is a half cycle earlier than that in the case where RDNn = 0 in the basic bus interface regardless of the RDNCR settings; and the RD/WR signal is used as write enable. 6.7.1 Byte Control SRAM Space Setting Byte control SRAM interface can be specified for areas 0 to 7. Each area can be specified as byte control SRAM interface by setting bits BCSELn (n = 0 to 7) in SRAMCR. For the area specified as burst ROM interface or address/data multiplexed I/O interface, the SRAMCR setting is invalid and byte control SRAM interface cannot be used. 6.7.2 Data Bus The bus width of the byte control SRAM space can be specified as 16-bit byte control SRAM space according to bits ABWHn and ABWLn (n = 0 to 7) in ABWCR. The area specified as 8-bit access space cannot be specified as the byte control SRAM space. For the 16-bit byte control SRAM space, data bus (D15 to D0) is valid. Access size and data alignment are the same as the basic bus interface. For details, see section 6.5.6, Endian and Data Alignment. Rev.1.00 Jun. 07, 2006 Page 205 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.7.3 I/O Pins Used for Byte Control SRAM Interface Table 6.16 shows the pins used for the byte control SRAM interface. In the byte control SRAM interface, write strobe signals (LHWR and LLWR) are output from the byte select strobes. The RD/WR signal is used as a write enable signal. Table 6.16 I/O Pins for Byte Control SRAM Interface Pin AS/AH When Byte Control SRAM is Specified AS Name Address strobe I/O Output Function Strobe signal indicating that the address output on the address bus is valid when a basic bus interface space or byte control SRAM space is accessed Strobe signal indicating that area n is selected Output enable for the SRAM when the byte control SRAM space is accessed Write enable signal for the SRAM when the byte control SRAM space is accessed Upper byte select when the 16-bit byte control SRAM space is accessed Lower byte select when the 16-bit byte control SRAM space is accessed Wait request signal used when an external address space is accessed Address output pin Data input/output pin CSn RD RD/WR LHWR/LUB LLWR/LLB WAIT A23 to A0 D15 to D0 CSn RD RD/WR LUB LLB WAIT A23 to A0 D15 to D0 Chip select Read strobe Read/write Lower-upper byte select Lower-lower byte select Wait Address pin Data pin Output Output Output Output Output Input Output Input/ output Rev.1.00 Jun. 07, 2006 Page 206 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.7.4 (1) Basic Timing 2-State Access Space Figure 6.25 shows the bus timing when the byte control SRAM space is specified as a 2-state access space. Data buses used for 16-bit access space is the same as those in basic bus interface. No wait cycles can be inserted. Bus cycle T1 B Address T2 CSn AS LUB LLB RD/WR RD D15 to D8 D7 to D0 Valid Valid Read RD/WR Write RD D15 to D8 D7 to D0 BS DACK Note: n = 0 to 7 High level Valid Valid Figure 6.25 16-Bit 2-State Access Space Bus Timing Rev.1.00 Jun. 07, 2006 Page 207 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) (2) 3-State Access Space Figure 6.26 shows the bus timing when the byte control SRAM space is specified as a 3-state access space. Data buses used for 16-bit access space is the same as those in the basic bus interface. Wait cycles can be inserted. Bus cycle T2 T1 B Address CSn AS LUB LLB RD/WR RD Read D15 to D8 D7 to D0 T3 Valid Valid RD/WR RD D15 to D8 D7 to D0 High level Valid Valid Write BS DACK Note: n = 0 to 7 Figure 6.26 16-Bit 3-State Access Space Bus Timing Rev.1.00 Jun. 07, 2006 Page 208 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.7.5 Wait Control The bus cycle can be extended for the byte control SRAM interface by inserting wait cycles (Tw) in the same way as the basic bus interface. (1) Program Wait Insertion From 0 to 7 wait cycles can be inserted automatically between T2 cycle and T3 cycle for the 3state access space in area units, according to the settings in WTCRA and WTCRB. (2) Pin Wait Insertion For 3-state access space, when the WAITE bit in BCR1 is set to 1, the corresponding DDR bit is cleared to 0, and the ICR bit is set to 1, wait input by means of the WAIT pin is enabled. For details on DDR and ICR, refer to section 9, I/O Ports. Figure 6.27 shows an example of wait cycle insertion timing. Rev.1.00 Jun. 07, 2006 Page 209 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Wait by program wait T1 B T2 Tpw Wait by WAIT pin Ttw Ttw T3 WAIT Address CSn AS LUB, LLB RD/WR Read RD Data bus RD/WR RD Data bus Read data Write High level Write data BS DACK Notes: 1. Upward arrows indicate the timing of WAIT pin sampling. 2. n = 0 to 7 Figure 6.27 Example of Wait Cycle Insertion Timing Rev.1.00 Jun. 07, 2006 Page 210 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.7.6 Read Strobe (RD) When the byte control SRAM space is specified, the RDNCR setting for the corresponding space is invalid. The read strobe negation timing is the same timing as when RDNn = 1 in the basic bus interface. Note that the RD timing with respect to the DACK rising edge becomes different. 6.7.7 Extension of Chip Select (CS) Assertion Period In the byte control SRAM interface, the extension cycles can be inserted before and after the bus cycle in the same way as the basic bus interface. For details, refer to section 6.6.6, Extension of Chip Select (CS) Assertion Period. 6.7.8 DACK Signal Output Timing For DMAC single address transfers, the DACK signal assert timing can be modified by using the DKC bit in BCR1. Figure 6.28 shows the DACK signal output timing. Setting the DKC bit to 1 asserts the DACK signal a half cycle earlier. Rev.1.00 Jun. 07, 2006 Page 211 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Bus cycle T1 B Address CSn AS LUB LLB T2 RD/WR RD Read D15 to D8 D7 to D0 RD/WR RD Write D15 to D8 D7 to D0 BS DKC = 0 DACK DKC = 1 Valid Valid Valid Valid High level Figure 6.28 DACK Signal Output Timing Rev.1.00 Jun. 07, 2006 Page 212 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.8 Burst ROM Interface In this LSI, external address space areas 0 and 1 can be designated as burst ROM space, and burst ROM interfacing performed. The burst ROM interface enables ROM with page access capability to be accessed at high speed. Areas 1 and 0 can be designated as burst ROM space by means of bits BSRM1 and BSRM0 in BROMCR. Consecutive burst accesses of up to 32 words can be performed, according to the setting of bits BSWDn1 and BSWDn0 (n = 0, 1) in BROMCR. From one to eight cycles can be selected for burst access. Settings can be made independently for area 0 and area 1. In the burst ROM interface, the burst access covers only CPU read accesses. Other accesses are performed with the similar method to the basic bus interface. 6.8.1 Burst ROM Space Setting Burst ROM interface can be specified for areas 0 and 1. Areas 0 and 1 can be specified as burst ROM space by setting bits BSRMn (n = 0, 1) in BROMCR. 6.8.2 Data Bus The bus width of the burst ROM space can be specified as 8-bit or 16-bit burst ROM interface space according to the ABWHn and ABWLn bits (n = 0, 1) in ABWCR. For the 8-bit bus width, data bus (D7 to D0) is valid. For the 16-bit bus width, data bus (D15 to D0) is valid. Access size and data alignment are the same as the basic bus interface. For details, see section 6.5.6, Endian and Data Alignment. Rev.1.00 Jun. 07, 2006 Page 213 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.8.3 I/O Pins Used for Burst ROM Interface Table 6.17 shows the pins used for the burst ROM interface. Table 6.17 I/O Pins Used for Burst ROM Interface Name Bus cycle start Address strobe Read strobe Read/write Low-high write Low-low write Symbol BS AS RD RD/WR LHWR LLWR I/O Output Output Output Output Output Output Output Input Function Signal indicating that the bus cycle has started. Strobe signal indicating that an address output on the address bus is valid during access Strobe signal indicating the read access Signal indicating the data bus input or output direction Strobe signal indicating that the upper byte (D15 to D8) is valid during write access Strobe signal indicating that the lower byte (D7 to D0) is valid during write access Strobe signal indicating that the area is selected Wait request signal used when an external address space is accessed Chip select 0 and 1 CS0, CS1 Wait WAIT Rev.1.00 Jun. 07, 2006 Page 214 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.8.4 Basic Timing The number of access cycles in the initial cycle (full access) on the burst ROM interface is determined by the basic bus interface settings in ABWCR, ASTCR, WTCRA, WTCRB, and bits CSXHn in CSACR (n = 0 to 7). When area 0 or area 1 designated as burst ROM space is read by the CPU, the settings in RDNCR and bits CSXTn in CSACR (n = 0 to 7) are ignored. From one to eight cycles can be selected for the burst cycle, according to the settings of bits BSTS02 to BSTS00 and BSTS12 to BSTS10 in BROMCR. Wait cycles cannot be inserted. In addition, 4-word, 8-word, 16-word, or 32-word consecutive burst access can be performed according to the settings of BSTS01, BSTS00, BSTS11, and BSTS10 bits in BROMCR. The basic access timing for burst ROM space is shown in figures 6.29 and 6.30. Full access T1 B Upper address bus Lower address bus CSn T2 T3 T1 Burst access T2 T1 T2 AS RD Data bus BS RD/WR Note: n = 1, 0 Figure 6.29 Example of Burst ROM Access Timing (ASTn = 1, Two Burst Cycles) Rev.1.00 Jun. 07, 2006 Page 215 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Full access T1 T2 T1 Burst access T1 B Upper address bus Lower address bus CSn AS RD Data bus BS RD/WR Note: n = 1, 0 Figure 6.30 Example of Burst ROM Access Timing (ASTn = 0, One Burst Cycle) Rev.1.00 Jun. 07, 2006 Page 216 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.8.5 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion by the WAIT pin can be used in the initial cycle (full access) on the burst ROM interface. See section 6.6.4, Wait Control. Wait cycles cannot be inserted in a burst cycle. 6.8.6 Read Strobe (RD) Timing When the burst ROM space is read by the CPU, the RDNCR setting for the corresponding space is invalid. The read strobe negation timing is the same timing as when RDNn = 0 in the basic bus interface. 6.8.7 Extension of Chip Select (CS) Assertion Period In the burst ROM interface, the extension cycles can be inserted in the same way as the basic bus interface. For the burst ROM space, the burst access can be enabled only in read access by the CPU. In this case, the setting of the corresponding CSXTn bit in CSACR is ignored and an extension cycle can be inserted only before the full access cycle. Note that no extension cycle can be inserted before or after the burst access cycles. In accesses other than read accesses by the CPU, the burst ROM space is equivalent to the basic bus interface space. Accordingly, extension cycles can be inserted before and after the burst access cycles. Rev.1.00 Jun. 07, 2006 Page 217 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.9 Address/Data Multiplexed I/O Interface If areas 3 to 7 of external address space are specified as address/data multiplexed I/O space in this LSI, the address/data multiplexed I/O interface can be performed. In the address/data multiplexed I/O interface, peripheral LSIs that require the multiplexed address/data can be connected directly to this LSI. 6.9.1 Address/Data Multiplexed I/O Space Setting Address/data multiplexed I/O interface can be specified for areas 3 to 7. Each area can be specified as the address/data multiplexed I/O space by setting bits MPXEn (n = 3 to 7) in MPXCR. 6.9.2 Address/Data Multiplex In the address/data multiplexed I/O space, data bus is multiplexed with address bus. Table 6.18 shows the relationship between the bus width and address output. Table 6.18 Address/Data Multiplex Data Pins Bus Width 8 bits Cycle Address Data 16 bits Address Data PI7 A15 PI6 A14 PI5 A13 PI4 A12 PI3 A11 PI2 A10 PI1 A9 D9 PI0 A8 D8 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 A7 D7 A7 D7 A6 D6 A6 D6 A5 D5 A5 D5 A4 D4 A4 D4 A3 D3 A3 D3 A2 D2 A2 D2 A1 D1 A1 D1 A0 D0 A0 D0 D15 D14 D13 D12 D11 D10 6.9.3 Data Bus The bus width of the address/data multiplexed I/O space can be specified for either 8-bit access space or 16-bit access space by the ABWHn and ABWLn bits (n = 3 to 7) in ABWCR. For the 8-bit access space, D7 to D0 are valid for both address and data. For 16-bit access space, D15 to D0 are valid for both address and data. If the address/data multiplexed I/O space is accessed, the corresponding address will be output to the address bus. For details on access size and data alignment, see section 6.5.6, Endian and Data Alignment. Rev.1.00 Jun. 07, 2006 Page 218 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.9.4 I/O Pins Used for Address/Data Multiplexed I/O Interface Table 6.19 shows the pins used for the address/data multiplexed I/O Interface. Table 6.19 I/O Pins for Address/Data Multiplexed I/O Interface When Byte Control SRAM is Specified CSn AH* RD LHWR Pin CSn AS/AH RD LHWR/LUB Name Chip select Address hold Read strobe I/O Output Output Output Function Chip select (n = 3 to 7) when area n is specified as the address/data multiplexed I/O space Signal to hold an address when the address/data multiplexed I/O space is specified Signal indicating that the address/data multiplexed I/O space is being read Strobe signal indicating that the upper byte (D15 to D8) is valid when the address/data multiplexed I/O space is written Strobe signal indicating that the lower byte (D7 to D0) is valid when the address/data multiplexed I/O space is written Address and data multiplexed pins for the address/data multiplexed I/O space. Only D7 to D0 are valid when the 8-bit space is specified. D15 to D0 are valid when the 16-bit space is specified. Low-high write Output LLWR/LLB LLWR Low-low write Output D15 to D0 D15 to D0 Address/data Input/ output A23 to A0 WAIT BS RD/WR A23 to A0 WAIT BS RD/WR Address Wait Output Input Address output pin Wait request signal used when the external address space is accessed Signal to indicate the bus cycle start Signal indicating the data bus input or output direction Bus cycle start Output Read/write Output Note: * The AH output is multiplexed with the AS output. At the timing that an area is specified as address/data multiplexed I/O, this pin starts to function as the AH output meaning that this pin cannot be used as the AS output. At this time, when other areas set to the basic bus interface is accessed, this pin does not function as the AS output. Until an area is specified as address/data multiplexed I/O, be aware that this pin functions as the AS output. Rev.1.00 Jun. 07, 2006 Page 219 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.9.5 Basic Timing The bus cycle in the address/data multiplexed I/O interface consists of an address cycle and a data cycle. The data cycle is based on the basic bus interface timing specified by the ABWCR, ASTCR, WTCRA, WTCRB, RDNCR, and CSACR. Figures 6.31 and 6.32 show the basic access timings. Address cycle Tma1 Tma2 T1 Data cycle T2 B Address bus CSn AH RD Read D7 to D0 Address Read data LLWR Write D7 to D0 Address Write data BS RD/WR DACK Note: n = 3 to 7 Figure 6.31 8-Bit Access Space Access Timing (ABWHn = 1, ABWLn = 1) Rev.1.00 Jun. 07, 2006 Page 220 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Bus cycle Address cycle Tma1 Tma2 T1 Data cycle T2 B Address bus CSn AH RD Read D15 to D0 Address Read data LHWR LLWR Write D15 to D0 Address Write data BS RD/WR DACK Note: n = 3 to 7 Figure 6.32 16-Bit Access Space Access Timing (ABWHn = 0, ABWLn = 1) Rev.1.00 Jun. 07, 2006 Page 221 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.9.6 Address Cycle Control An extension cycle (Tmaw) can be inserted between Tma1 and Tma2 cycles to extend the AH signal output period by setting the ADDEX bit in MPXCR. By inserting the Tmaw cycle, the address setup for AH and the AH minimum pulse width can be assured. Figure 6.33 shows the access timing when the address cycle is three cycles. Address cycle Tma1 B Tmaw Tma2 T1 Data cycle T2 Address bus CSn AH RD Read D15 to D0 LHWR Address Read data Write LLWR D15 to D0 Address Write data BS RD/WR DACK Note: n = 3 to 7 Figure 6.33 Access Timing of 3 Address Cycles (ADDEX = 1) Rev.1.00 Jun. 07, 2006 Page 222 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.9.7 Wait Control In the data cycle of the address/data multiplexed I/O interface, program wait insertion and pin wait insertion by the WAIT pin are enabled in the same way as in the basic bus interface. For details, refer to section 6.6.4, Wait Control. Wait control settings do not affect the address cycles. 6.9.8 Read Strobe (RD) Timing In the address/data multiplexed I/O interface, the read strobe timing of data cycles can be modified in the same way as in basic bus interface. For details, refer to section 6.6.5, Read Strobe (RD) Timing. Figure 6.34 shows an example when the read strobe timing is modified. Rev.1.00 Jun. 07, 2006 Page 223 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Address cycle Tma1 Tma2 T1 Data cycle T2 B Address bus CSn AH RD RDNn = 0 D15 to D0 Address Read data RD RDNn = 1 D15 to D0 Address Read data BS RD/WR DACK Note: n = 3 to 7 Figure 6.34 Read Strobe Timing Rev.1.00 Jun. 07, 2006 Page 224 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.9.9 Extension of Chip Select (CS) Assertion Period In the address/data multiplexed interface, the extension cycles can be inserted before and after the bus cycle. For details, see section 6.6.6, Extension of Chip Select (CS) Assertion Period. Figure 6.35 shows an example of the chip select (CS) assertion period extension timing. Bus cycle Address cycle Tma1 B Tma2 Th T1 Data cycle T2 Tt Address bus CSn AH RD Read D15 to D0 Address Read data LHWR LLWR Write D15 to D0 Address Write data BS RD/WR DACK Note: n = 3 to 7 Figure 6.35 Chip Select (CS) Assertion Period Extension Timing in Data Cycle Rev.1.00 Jun. 07, 2006 Page 225 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) When consecutively reading from the same area connected to a peripheral LSI whose data hold time is long, data outputs from the peripheral LSI and this LSI may conflict. Inserting the chip select assertion period extension cycle after the access cycle can avoid the data conflict. Figure 6.36 shows an example of the operation. In the figure, both bus cycles A and B are read access cycles to the address/data multiplexed I/O space. An example of the data conflict is shown in (a), and an example of avoiding the data conflict by the CS assertion period extension cycle in (b). Bus cycle A Bus cycle B B Address bus CS AH RD Data bus Data conflict Data hold time is long. (a) Without CS assertion period extension cycle (CSXTn = 0) Bus cycle A Bus cycle B B Address bus CS AH RD Data bus (b) With CS assertion period extension cycle (CSXTn = 1) Figure 6.36 Consecutive Read Accesses to Same Area (Address/Data Multiplexed I/O Space) Rev.1.00 Jun. 07, 2006 Page 226 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.9.10 DACK Signal Output Timing For DMAC single address transfers, the DACK signal assert timing can be modified by using the DKC bit in BCR1. Figure 6.37 shows the DACK signal output timing. Setting the DKC bit to 1 asserts the DACK signal a half cycle earlier. Address cycle Data cycle Tma1 B Tma2 T1 T2 Address bus CSn AH RD RDNn = 0 D15 to D0 RD RDNn = 1 D15 to D0 Address Read data Address Read data BS RD/WR DKC = 0 DACK DKC = 1 Note: n = 3 to 7 Figure 6.37 DACK Signal Output Timing Rev.1.00 Jun. 07, 2006 Page 227 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.10 DRAM Interface In this LSI, area 2 in the external space can be used as the DRAM interface space. Up to 8 Mbytes of DRAM is directly connected via the DRAM interface. 6.10.1 Setting DRAM Space Area 2 can be specified as the DRAM space by the DRAME and DTYPE bits in DRAMCR. Table 6.20 lists the relationship among the DRAME and DTYPE bits and area 2 interfaces. The bus settings of the DRAM space such as bus width and wait cycle number depend on area 2 settings. Table 6.20 Relationship Among DRAME and DTYPE and Area 2 Interfaces DRAME 0 1 1 [Legend] x: Don't care DTYPE x 0 1 Area 2 Interface Basic bus space (initial state)/byte-control SRAM space DRAM space SDRAM space 6.10.2 Address Multiplexing A Row address and a column address are multiplexed in the DRAM space. Select the number of row address bits to be shifted with bits MXC1 and MXC0 in DRAMCR. Table 6.21 lists the relationship among bits MXC1 and MXC0 and shifted bit number. Table 6.21 Relationship Among MXC1 and MXC0 and Shifted Bit Count DRAMCR Shit Bit MXC1 MXC0 Count 0 0 8 bits Data Bus Width 8/16 bits External Address Pin Address Row address A27 to A18 A23 to A18 A17 A16 A15 A14 A13 A12 A11 A10 A17 A9 A8 A7 A6 A5 A4 A3 A2 A1 A9 A1 A0 A8 A0 A9 A0 - A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 Column address A23 to A18 0 1 9 bits 8/16 bits Row address A23 to A18 A17 A16 A15 A14 A13 A12 A11 A10 A17 - A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 Column address A23 to A18 1 0 10 bits 8/16 bits Row address A23 to A18 A17 A16 A15 A14 A13 A12 A11 A10 A17 - A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Column address A23 to A18 1 1 11 bits 8/16 bits Row address A23 to A18 A17 A16 A15 A14 A13 A12 A11 A10 A17 - A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Column address A23 to A18 A17 A16 A15 A14 A13 A12 A11 A10 Rev.1.00 Jun. 07, 2006 Page 228 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.10.3 Data Bus The data bus width of the DRAM space can be selected from 8 and 16 bits by bits ABWH2 and ABWL2 in ABWCR. DRAM with 16-bit words can be connected directly to 16-bit bus width space. D7 to D0 are valid in 8-bit DRAM space, and D15 to D0 are valid in 16-bit DRAM space. The data endian format can be selected by bit LE2 in ENDIANCR. For details on the access size and alignment, see section 6.5.6, Endian and Data Alignment. 6.10.4 I/O Pins Used for DRAM Interface Table 6.22 shows the pins used for the DRAM interface. Table 6.22 I/O Pins for DRAM Interface Pin WE RAS LUCAS/ DQMLU DRAM Selected WE RAS LUCAS Name Write enable Row address strobe I/O Output Output Function Write enable signal for accessing the DRAM interface Row address strobe when the DRAM space is specified as area 2 * Lower-upper column address strobe when the 32-bit DRAM space is accessed Upper column address strobe when the 16-bit DRAM space is accessed Lower-lower column address strobe when the 32-bit DRAM space is accessed Lower column address strobe when the 16-bit DRAM space is accessed Output Lower-upper column address strobe * LLCAS/ DQMLL LLCAS Lower-lower Output column address strobe * * OE WAIT A17 to A0 D15 to D0 OE WAIT A17 to A0 D15 to D0 Output enable Wait Address pin Data pin Output Input Output Input/ output Output enable signal when the DRAM space is accessed Wait request signal used when an external address space is accessed Multiplexed address/data output pin Data input/output pin Rev.1.00 Jun. 07, 2006 Page 229 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.10.5 Basic Timing Figure 6.38 shows a basic access timing of the DRAM space. A basic bus cycle consists of four clock cycles: one precharge cycle (Tp), one row address output cycle (Tr), and two column address output cycles (Tc1 and Tc2). The RD signal is output to DRAM as an OE signal on a DRAM access. When DRAM with the EDO page mode function is in use, connect the OE signal to the OE pin of the DRAM. Tp B Tr Tc1 Tc2 Address bus Row address Column address RAS LUCAS LLCAS WE Read OE (RD) Data bus WE Write OE (RD) Data bus High High BS RD/WR Figure 6.38 DRAM Basic Access Timing (RAS = 0 and CAST = 0) Rev.1.00 Jun. 07, 2006 Page 230 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.10.6 Controlling Column Address Output Cycle The number of column address output cycles can be changed from two to three clock cycles by setting the CAST bit in DRAMCR. Set the bit according to the DRAM to be used and the frequency of this LSI so that the CAS pulse width can be optimal. Figure 6.39 shows a timing example when the number of column address output cycles is set to three clock cycles. Tp B Tr Tc1 Tc2 Tc3 Address bus RAS LUCAS LLCAS WE Read OE (RD) Data bus WE Write OE (RD) Data bus Row address Column address High High BS RD/WR Figure 6.39 Access Timing Example of Column Address Output Cycles for 3 Clock Cycles (RAST = 0) Rev.1.00 Jun. 07, 2006 Page 231 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.10.7 Controlling Row Address Output Cycle The RAS signal is driven low at the start of the Tr cycle by setting the RAST bit to 1. The row address hold time to the falling edge of the RAS signal and the DRAM read access time are changed. Set the bit according to the DRAM to be used and the frequency of this LSI so that required performance can be obtained. Figure 6.40 shows a timing example when the RAS signal is driven low at the start of the Tr cycle. Tp B Address bus Row address Column address Tr Tc1 Tc2 RAS LUCAS LLCAS High WE Read OE (RD) Data bus WE Write OE (RD) Data bus BS RD/WR High Figure 6.40 Access Timing Example of RAS Signal Driven Low at Start of Tr Cycle (CAST = 0) Rev.1.00 Jun. 07, 2006 Page 232 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) To ensure the row address hold time or read access time, one to three of Trw cycles in which the row address output is retained can be inserted between the Tr and Tc1 cycles. The RAS signal is driven low in the Tr cycle and the column address is output in the Tc1 cycle. Set the bit according to the DRAM to be used and the frequency of this LSI so that the row address hold time to the rising edge of the RAS signal is ensured. Figure 6.41 shows an access timing example when one Trw cycle is specified. Tp B Tr Trw Tc1 Tc2 Address bus Row address Column address RAS LUCAS LLCAS WE Read OE (RD) Data bus High WE Write OE (RD) Data bus BS RD/WR High Figure 6.41 Access Timing Example when One Trw Cycle is Specified Rev.1.00 Jun. 07, 2006 Page 233 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.10.8 Controlling Precharge Cycle The number of precharge cycles (Tp) can be selected from one to four clock cycles by bits TPC1 and TPC0 in DRACCR. Set the bit according to the DRAM to be used and the frequency of this LSI so that the number of precharge cycle can be optimal. Figure 6.42 shows an access timing example when two Tp cycles are specified. The setting of bits TPC1 and TPC0 affect the Tp cycle of a refresh cycle. Tp1 B Tp2 Tr Tc1 Tc2 Address bus Row address Column address RAS LUCAS LLCAS WE Read OE (RD) Data bus High WE Write OE (RD) Data bus BS RD/WR High Figure 6.42 Access Timing Example of Two Precharge Cycles (RAST = 0 and CAST = 0) Rev.1.00 Jun. 07, 2006 Page 234 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.10.9 Wait Control There are two methods of inserting wait cycles during a DRAM access cycle: program wait insertion and pin wait insertion using the WAIT pin. Wait cycles are inserted to extend the CAS assertion period during a DRAM read cycle and to ensure the write data setup time to the falling edge of the CAS signal during a DRAM write cycle. (1) Program Wait Insertion When bit AST2 in ASTCR is set to 1, zero to seven of wait cycles can automatically be inserted between the Tc1 and Tc2 cycles. The number of wait cycles is selected by bits W22 to W20 in WTCRB. (2) Pin Wait Insertion When the WAITE bit in BCR1 is set to 1, and the AST2 bit in ASTCR is set to 1, setting the ICR bit for the corresponding pin to 1 enables wait input by the WAIT pin. When the DRAM space is accessed in this state, a program wait (Tpw) is first inserted. If the WAIT pin is low at the rising edge of B in the last Tc1 or Tpw cycle, another Ttw cycle is inserted until the WAIT pin is driven high. For details on ICR, see section 9, I/O Ports. Figure 6.43 shows an example of wait cycle insertion timing for 2-cycle column address output. Figure 6.44 shows an example of wait cycle insertion timing for 3-cycle column address output. Rev.1.00 Jun. 07, 2006 Page 235 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Tp B Tr Tc1 Wait by program Wait by wait WAIT pin Tpw Ttw Tc2 WAIT Address bus RAS Row address Column address LUCAS, LLCAS WE Read OE (RD) High Data bus LUCAS, LLCAS WE Write OE (RD) High Data bus BS RD/WR Note: Upward arrows indicate the timing of WAIT pin sampling. Figure 6.43 Example of Wait Cycle Insertion Timing for 2-Cycle Column Address Output Rev.1.00 Jun. 07, 2006 Page 236 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Tp B Tr Tc1 Wait by program Wait by wait WAIT pin Tpw Ttw Tc2 Tc3 WAIT Address bus RAS Row address Column address LUCAS, LLCAS WE Read OE (RD) High Data bus LUCAS, LLCAS WE Write OE (RD) High Data bus BS RD/WR Note: Upward arrows indicate the timing of WAIT pin sampling. Figure 6.44 Example of Wait Cycle Insertion Timing for 3-Cycle Column Address Output Rev.1.00 Jun. 07, 2006 Page 237 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.10.10 Controlling Byte and Word Accesses When 16-bit bus DRAM is used, two CAS signals can be used to control byte and word accesses. Figures 6.45 and 6.46 show control timing examples with use of two CAS signals (in big endian format). Figure 6.47 shows an example of connection for control with two CAS signals. Tp B Address bus RAS Tr Tc1 Tc2 Row address Column address LUCAS LLCAS WE OE (RD) D15 to D8 D7 to D0 BS High RD/WR Figure 6.45 Timing Example of Byte Control with Use of Two CAS Signals (Write Access with Lowest Bit of Address = B'0, RAST = 0, CAST = 0) Rev.1.00 Jun. 07, 2006 Page 238 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Tp B Tr Tc1 Tc2 Address bus RAS LUCAS LLCAS Row address Column address WE OE (RD) D15 to D8 D7 to D0 High BS RD/WR Figure 6.46 Timing Example of Word Control with Use of Two CAS Signals (Read Access with Lowest Bit of Address = B'0, RAST = 0, CAST = 0) Rev.1.00 Jun. 07, 2006 Page 239 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) This LSI (Address shifted by 11 bits) RAS LUCAS LLCAS WE RD (OE) A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 D15 to D0 Two CAS signals used 64-Mbit DRAM (4 Mwords x 16 bits) 11-bit column address RAS UCAS LCAS WE OE A10 A9 Row address input: A10 to A0 A8 Column address input: A10 to A0 A7 A6 A5 A4 A3 A2 A1 A0 D15 to D0 Figure 6.47 Example of Connection for Control with Two CAS Signals 6.10.11 Burst Access Operation Besides an accessing method in which this LSI outputs a row address every time it accesses the DRAM (called full access or normal access), some DRAMs have a fast-page mode function in which fast speed access can be achieved by modifying only a column address with the same row address output (burst access) when consecutive accesses are made to the same row address. (1) Burst Access (Fast-Page Mode) Operation Timing Figures 6.48 and 6.49 show operation timing of the fast-page mode. When access cycles to the DRAM space are continued and the row addresses of the consecutive two cycles are the same, output cycles of the CAS and column address signals follow. The row address bits to be compared are decided by bits MXC1 and MXC0 in DRAMCR. Wait cycles can be inserted during a burst access. The method and timing of the wait insertion are the same as that of full access mode. For details, see section 6.10.9, Wait Control. Rev.1.00 Jun. 07, 2006 Page 240 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Tp B Tr Tc1 Tc2 Tc1 Tc2 Address bus RAS LUCAS LLCAS WE Read OE (RD) Data bus Row address Column address Column address WE Write OE (RD) Data bus BS RD/WR Figure 6.48 Operation Timing of Fast-Page Mode (RAST = 0, CAST = 0) Rev.1.00 Jun. 07, 2006 Page 241 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Tp B Tr Tc1 Tc2 Tc3 Tc1 Tc2 Tc3 Address bus RAS LUCAS LLCAS WE Read OE (RD) Data bus WE Write OE (RD) Data bus BS RD/WR Row address Column address Column address High High Figure 6.49 Operation Timing of Fast-Page Mode (RAST = 0, CAST = 1) Rev.1.00 Jun. 07, 2006 Page 242 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) (2) RAS Down Mode and RAS Up Mode Even if the fast-page mode is selected, the DRAM space is not consecutively accessed and other spaces may be accessed. The RAS signal can be held low during other space accesses. The fastpage mode access can be resumed (burst access) when the same row address in the DRAM space is accessed. (a) RAS Down Mode Set the RCDM and BE bits in DRAMCR to 1 to make a transition to the RAS down mode. The RCDM bit is enabled only when the BE bit is set to 1. The fast-page mode access (burst access) is resumed when the row addresses of the current cycle and previous cycle are the same. While other spaces are accessed when the DRAM space access is halted, the RAS signal must be low. Figure 6.50 shows a timing example of RAS down mode. The RAS signal goes high under the following conditions. * When a refresh cycle is performed during RAS down mode * When a self-refresh is performed * When a transition to software standby mode is made * When the external bus requested by the BREQ signal is released * When either the RCDM or BE bit is cleared to 0 If a transition to the all-module clock-stop mode is made during RAS down mode, clocks are stopped with the RAS signal driven low. To make a transition with the RAS signal driven high, clear the RCDM bit to 0 before execution of the SLEEP instruction. Clear the RCDM bit to 0 for write access to SCKCR to set the clock frequencies. For SCKCR, see section 22, Clock Pulse Generator. Rev.1.00 Jun. 07, 2006 Page 243 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) DRAM space read Tp B Tr Tc1 Tc2 Basic bus space read DRAM space read Tc1 Tc2 Tc1 Tc2 Address bus RAS LUCAS LLCAS Row address Column address External address Column address WE OE RD Data bus High BS RD/WR Figure 6.50 Timing Example of RAS Down Mode (RAST = 0, CAST = 0) Rev.1.00 Jun. 07, 2006 Page 244 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) (b) RAS Up Mode Set the BE bit in DRAMCR to 1 and clear the RCDM bit in DRAMCR to 0 to set the RAS up mode. Whenever a DRAM space access is halted and other spaces are accessed, the RAS signal is driven high. Only when the DRAM space continues to be accessed, the fast-page mode access (burst access) is performed. Figure 6.51 shows a timing example of RAS up mode. DRAM space read Tp B Address bus RAS LUCAS LLCAS WE RD Row address Column address Column address External address Tr Tc1 Tc2 DRAM space read Basic bus space read Tc1 Tc2 T1 T2 High OE Data bus BS RD/WR Figure 6.51 Timing Example of RAS Up Mode (RAST = 0, CAST = 0) Rev.1.00 Jun. 07, 2006 Page 245 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.10.12 Refresh Control This LSI includes a DRAM refresh control function. The refresh method is the CAS before RAS (CBR) refresh. Self-refresh cycles can be performed in software standby mode. The refresh control function is enabled when area 2 is specified as the DRAM space by the DRAME and DTYPE bits in DRAMCR. (1) CAS before RAS (CBR) Refresh Mode Set the RFSHE bit in REFCR to 1 to select the CBR refresh mode. A CBR refresh cycle is performed when the value set in RTCOR matches the RTCNT value (compare match). RTCNT is an up-counter operated on the input clock specified by bits RTCK2 to RTCK0 in REFCR. RTCNT is initialized upon the compare match and restarts to count up with H'00. Accordingly, a CBR refresh cycle is repeated at intervals specified by bits RTCK2 to RTCK0 in RTCOR. Set the bits so that the required refresh intervals of the DRAM must be satisfied. Since setting bits RTCK2 to RTCK0 starts RTCNT to count up, set RTCNT and RTCOR before setting bits RTCK2 to RTCK0. When changing RTCNT and RTCOR, the counting operation should be halted. When changing bits RTCK2 to RTCK0, change them only after disabling external bus release, and if the write data buffer function is in use, disabling the write data buffer function and reading the external space. The external space cannot be accessed in CBR refresh mode. Figure 6.52 shows RTCNT operation, figure 6.53 shows compare match timing, and figure 6.54 shows CBR refresh timing. Table 6.23 lists the pin states during a CBR refresh cycle. RTCNT RTCOR H'00 Refresh request Figure 6.52 RTCNT Operation Rev.1.00 Jun. 07, 2006 Page 246 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) P RTCNT N H'00 RTCOR N Refresh request and CMF bit set signal Figure 6.53 Compare Match Timing TRp B TRr TRc1 TRc2 RAS LUCAS LLCAS BS RD/WR High High Figure 6.54 CBR Refresh Timing Rev.1.00 Jun. 07, 2006 Page 247 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Table 6.23 Pin States during DRAM Refresh Cycle Pin A17 to A0 D15 to D0 RAS LUCAS, LLCAS WE AS RD BS RD/WR State Hold the value of the previous bus cycle Hi-Z Used for refresh control Used for refresh control High High High High High The RAS signal can be delayed for one to three clock cycles by setting bits RCW1 and RCW0 in REFCR. The pulse width of the RAS signal is changed by bits RLW2 to RLW0 in REFCR. The settings of bits RCW1, RCW0, and RLW2 to RLW0 are effective only for a refresh cycle. The precharge time set by bit TPC1 and TPC0 is effective for a refresh cycle. Figure 5.55 shows a timing for setting bits RCW1 and RCW0 TRp B TRrw TRr TRc1 TRc2 RAS LUCAS LLCAS BS RD/WR High High Figure 6.55 CBR Refresh Timing (RCW1 = 0, RCW0 = 1, RLW2 = 0, RLW1 = 0, RLW0 = 0) Rev.1.00 Jun. 07, 2006 Page 248 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) (2) Self-Refresh Mode Some DRAMs have a self-refresh mode (battery backup mode). The self-refresh mode is a kind of standby mode and refresh timing and refresh address are controlled internally. The self-refresh mode is selected by setting the RFSHE and SLFRF bits in REFCR to 1. The CAS and RAS signals are output as shown in figure 6.56 by executing the SLEEP instruction. Then, DRAM enters self-refresh mode. When a CBR refresh is requested on a transition to the standby mode, the CBR refresh is first performed and then the self-refresh mode is entered. When the self-refresh mode is used, do not clear the OPE bit in SBYCR to 0. For details, see section 23.2.1, Standby Control Register (SBYCR). Software standby TRp B RAS LUCAS LLCAS TRr TRc3 TRc4 WE BS RD/WR High High High Figure 6.56 Self-Refresh Timing Rev.1.00 Jun. 07, 2006 Page 249 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Some DRAMs having the self-refresh mode needs longer precharge time of the RAS signal immediately after the self-refresh mode than that in normal operation. From one to seven of precharge cycles immediately after a self-refresh cycle can be inserted. Precharging is also performed according to bits TPC1 and TPC0 in DRACCR. Set the precharge time so that the precharge time immediately after a self-refresh cycle is optimal. Figure 6.57 shows a timing example when one precharge cycle is added. Software standby TRc3 B Address bus RAS LUCAS LLCAS High TRc4 TRp1 Tp DRAM space write Tr Tc1 Tc2 RD OE WE Data bus BS RD/WR High High Figure 6.57 Timing Example when 1 Precharge Cycle Added Rev.1.00 Jun. 07, 2006 Page 250 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) (3) Refresh and All-Module Clock Stop Mode This LSI is entered in all-module clock stop mode by the following operation: Stop the clocks of all on-chip peripheral modules by setting the ACSE bit in MSTPCR to 1 (MSTPCRA, MSTPCRB = H'FFFFFFFF) or run only the 8-bit timer (MSTPCRA, MSTPCRB = H'F[C to F]FFFFFF), then execute the SLEEP instruction to enter the sleep mode. In all-module clock stop mode, clocks for the bus controller and I/O ports are stopped. Since the clock for the bus controller is stopped, a CBR refresh cycle cannot be performed. When external DRAM is used and the contents of the DRAM in sleep mode should be held, clear the ACSE bit in MSTPCE to 0. For details, see section 23.2.2, Module Stop Control Registers A and B (MSTPCR and MSTPCRB). 6.10.13 DRAM Interface and Single Address Transfer by DMAC When fast-page mode (BE = 1) is set for the DRAM space, either fast-page access or full access can be selected, by the setting of bit DDS in DRAMCR, for the single address transfer by the DMAC where the DRAM space is specified as the transfer source or destination. At the same time, the output timing of the DACK and BS signals is changed. When BE = 0, full access to the DRAM space is performed by single address transfer regardless of the setting of bit DDS. However, the output timing of the DACK and BS signals can be changed by the setting of bit DDS. The assertion timing of the DACK signal can be changed by bit DKC in BCR1. Rev.1.00 Jun. 07, 2006 Page 251 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) (1) When DDS = 1 A fast-page access is performed regardless of the bus master, only according to the address. The DACK signal is asserted at the start of the Tc1 cycle. Figure 6.58 shows the output timing example of the DACK signal. Tp B Address bus RAS LUCAS LLCAS WE Read OE (RD) Data bus WE Write OE (RD) Data bus When DKC = 0 DACK When DKC = 1 BS RD/WR High High Row address Column address Tr Tc1 Tc2 Figure 6.58 Output Timing Example of DACK when DDS = 1 (RAST = 0, CAST = 0) Rev.1.00 Jun. 07, 2006 Page 252 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) (2) When DDS = 0 Single address transfer by the DMAC takes place as a full access (normal access). The DACK signal is asserted within the Tr cycle and the BS signal is also asserted during the Tr cycle. When the DRAM space is accessed with other than the single address transfer by the DMAC, a fast-page access is available. Figure 6.59 shows an output timing example of the DACK signal when DDS = 0. Tp B Address bus RAS LUCAS LLCAS WE Read OE (RD) Data bus WE Write OE (RD) Data bus High High Row address Column address Tr Tc1 Tc2 Tc3 When DKC = 0 DACK When DKC = 1 BS RD/WR Figure 6.59 Output Timing Example of DACK when DDS = 0 (RAST = 0, CAST = 1) Rev.1.00 Jun. 07, 2006 Page 253 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.11 Synchronous DRAM Interface In this LSI, area 2 in the external space can be used as the SDRAM interface space. Up to 8 Mbytes (64 Mbits) of DRAM is directly connected via the SDRAM interface. The CAS latency with 2 to 4 is supported. 6.11.1 Setting SDRAM space Area 2 can be specified as the SDRAM space by the DRAME and DTYPE bits in DRAMCR. Table 6.24 lists the relationship among the DRAME and DTYPE bits and area 2 interfaces. In the SDRAM space, pins PB2, PB3, and PB4 are used as the RAS, CAS, and WE signals. The PB1 pin is used as the CS2 signal by the PFCR setting, and the PB5 pin is used as the CKE signal by setting the OEE bit in DRAMCR to 1. The bus settings of the SDRAM space depend on area 2 settings. The pin wait and program wait for the SDRAM space are not available. For PFCR, see section 9, I/O Ports. An SDRAM command is designated by the combination of the RAS, CAS, and WE signals and the precharge-sel command (Precharge-sel) output on the upper column address. This LSI supports the following commands: the NOP, auto-refresh (REF), self-refresh (SELF), allbank-precharge (PALL), bank active (ACTV), read (READ), write (WRIT), and mode register setting (MRS). Commands controlling a bank are not supported. Table 6.24 Relationship among DRAME and DTYPE and Area 2 Interfaces DRAME 0 1 1 [Legend] X: Don't care DTYPE X 0 1 Area 2 Interface Basic bus space (initial state)/byte-control SRAM space DRAM space SDRAM space Rev.1.00 Jun. 07, 2006 Page 254 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.11.2 Address Multiplexing A Row address and a column address are multiplexed in the SDRAM space. Select the number of row address bits to be shifted with bits MXC1 and MXC0 in DRAMCR. The precharge set command (Precharge-sel) is output on the upper column address. Table 6.25 lists the relationship among bits MXC1 and MXC0 and shifted bit number. Table 6.25 Relationship Among MXC1 and MXC0 and Shifted Bit Count DRAMCR Shift Bit Data Bus Address MXC1 MXC0 Count Width 0 0 8 bits 8 bits Row address External Address Pin A23 to A18 A17 A16 A15 A14 A13 A12 A11 A10 A23 to A18 A9 A8 A7 A6 A5 A4 A3 A2 A1 A9 A1 A9 A1 A0 A8 A0 A8 A0 A9 A0 A9 A0 - - A23 A22 A21 A20 A19 P/A18* A17 A16 A15 A14 A13 A12 A11 A10 A23 A22 A21 A20 A19 P A9 A8 A7 A6 A5 A4 A3 A2 Column address A23 to A18 16 bits Row address A23 to A18 A23 A22 A21 A20 P/A19* A18 A17 A16 A15 A14 A13 A12 A11 A10 A23 A22 A21 A20 P A10 A9 A8 A7 A6 A5 A4 A3 A2 Column address A23 to A18 0 1 9 bits 8 bits Row address A23 to A18 A17 - A23 A22 A21 A20 P/A19* A18 A17 A16 A15 A14 A13 A12 A11 A10 A23 A22 A21 A20 P A9 A8 A7 A6 A5 A4 A3 A2 A1 Column address A23 to A18 A17 16 bits Row address A23 to A18 A17 A23 A22 A21 P/A20* A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A23 A22 A21 P A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 Column address A23 to A18 A17 1 0 10 bits 8 bits Row address A23 to A18 - - A23 A22 A21 P/A20* A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A23 A22 A21 P A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Column address A23 to A18 16 bits Row address A23 to A18 A23 A22 P/A21* A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A23 A22 P A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Column address A23 to A18 1 1 11 bits 8 bits Row address A23 to A18 A17 - A23 A22 P/A21* A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A23 A10 P A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Column address A23 to A18 A17 16 bits Row address A23 to A18 A17 A23 P/A22* A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A11 P A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Column address A23 to A18 A17 Note: * When issuing the PALL command, precharge-sel = 1 is output and when issuing the ACTIV command, a corresponding address is output. 6.11.3 Data Bus Either 8 or 16 bits can be selected as the data bus width of the SDRAM space by bits ABWH2 and ABWL2 in ABWCR. SDRAM with 16-bit words can be connected directly to 16-bit bus width space. D7 to D0 are valid in 8-bit SDRAM space and D15 to D0 are valid in 16-bit SDRAM space. The data endian format can be selected by bit LE2 in ENDIANCR. For details on the access size and alignment, see section 6.5.6, Endian and Data Alignment. Rev.1.00 Jun. 07, 2006 Page 255 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.11.4 I/O Pins Used for DRAM Interface Table 6.26 shows the pins used for the SDRAM interface. Since a CS pin functions as an input after a reset, set the bit in PFCR to 1 to output the CS signal. For details, see section 9, I/O Ports. To enable the SDRAM interface, select the appropriate MCU operating mode. For details, see section 3, MCU Operating Modes. Table 6.26 I/O Pins for SDRAM Interface Pin RAS CAS WE OE/CKE LLCAS/ DQMLU LLCAS/ DQMLL DRAM Selected RAS CAS WE CKE DQMLU DQMLL Name Row address strobe Column address strobe Write enable Clock enable Lower-upper data mask enable Lower-lower data mask enable I/O Output Output Output Output Output Output Function Row address strobe when the SDRAM space is specified as area 2 Column address strobe when the SDRAM space is specified as area 2 Write enable signal for accessing the SDRAM interface Clock enable signal when the SDRAM space is specified as area 2. Upper data mask enable when the 16bit SDRAM space is accessed * * A17 to A0 D15 to D0 (PA7) PB7 CS2 A17 to A0 D15 to D0 SD CS Address pin Data pin Clock Chip select Output Input/ output Output Output Lower data mask enable when the 16-bit SDRAM space is accessed Data mask enable when the 8-bit SDRAM is accessed Multiplexed row/column-address output pin Data input/output pin SDRAM clock Strobe signal indicating that SDRAM is selected Rev.1.00 Jun. 07, 2006 Page 256 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.11.5 Basic Timing Figures 6.60 and 6.61 show a basic access timing of the SDRAM space. A basic read cycle consists of five clock cycles: one precharge cycle (Tp), one row address output cycle (Tr), and three column address output cycles (Tc1, Tcl, and Tc2). A basic write cycle consists of four clock cycles: one precharge cycle (Tp), one row address output cycle (Tr), and two column address output cycles (Tc1 and Tc2). When the SDRAM space is selected, the WAITE bit in BCR, the RAST and CAST bits in DRAMCR, bits RCW1 and RCW0 in REFCR are ignored. Tp SD Address bus Precharge-sel CS RAS CAS WE CKE DQMLU DQMLL D15 to D8 D7 to D0 BS RD/WR PALL ACTV READ NOP Row address Row address Column address Tr Tc1 Tcl Tc2 Figure 6.60 SDRAM Basic Read Access Timing (CAS Latency = 2) Rev.1.00 Jun. 07, 2006 Page 257 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Tp SD Address bus Precharge-sel CS RAS CAS WE CKE DQMLU DQMLL D15 to D8 D7 to D0 BS RD/WR PALL Tr Tc1 Tc2 Row address Row address Column address High ACTV NOP WRIT Figure 6.61 SDRAM Basic Write Access Timing Rev.1.00 Jun. 07, 2006 Page 258 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.11.6 CAS Latency Control The CAS latency is controlled by bits W21 and W20 in WTCRB. Table 6.27 lists the setting and CAS latency. CAS latency control cycles (Tcl) are inserted in a read cycle according to the W21 and W20 settings. WTCRB can be specified regardless of bit AST2 in ASTCR. Figure 6.62 shows a timing example when SDRAM with a CAS latency of 3 is in use. Bits W21 and W20 is initialized to B'11. Table 6.27 CAS Latency Setting W21 0 W20 0 1 1 0 1 Description Setting prohibited SDRAM with CAS latency of 2 is in use SDRAM with CAS latency of 3 is in use SDRAM with CAS latency of 4 is in use Number of CAS Latency Cycles 1 2 3 Rev.1.00 Jun. 07, 2006 Page 259 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Tp SD Address bus Precharge-sel CS RAS CAS WE CKE DQMLU DQMLL D15 to D8 D7 to D0 BS RD/WR PALL Tr Tc1 Tcl1 Tcl2 Tc2 Row address Row address Column address High ACTV READ NOP Figure 6.62 Timing Example of CAS Latency (CAS Latency = 3) Rev.1.00 Jun. 07, 2006 Page 260 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.11.7 Controlling Row Address Output Cycle When the time between the ACTV command and the subsequent READ or WRIT command does not meet a given specification, the Trw cycle in which the NOP command is output can be inserted for one to three cycles between the Tr cycle in which the ACTV command is output and the Tc1 cycle in which the column address is output. Set the bit according to the SDRAM to be used and the frequency of this LSI so that the number of wait cycles can be optimal. Figures 6.63 and 6.64 show a timing example when the one Trw cycle is inserted. Tp SD Address bus Precharge-sel CS RAS CAS WE CKE DQMLU DQMLL D15 to D8 D7 to D0 BS RD/WR PALL ACTV NOP READ NOP High Row address Row address Tr Trw Tc1 Tcl Tc2 Column address Figure 6.63 Read Timing Example of Row Address Output Retained for 1 Clock Cycle (RCD1 = 0, RCD0 = 1, CAS Latency = 2) Rev.1.00 Jun. 07, 2006 Page 261 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Tp SD Address bus Precharge-sel CS RAS CAS WE CKE DQMUU DQMLL Tr Trw Tc1 Tc2 Row address Row address Column address High D15 to D8 D7 to D0 BS RD/WR PALL ACTV NOP NOP WRIT Figure 6.64 Write Timing Example of Row Address Output Retained for 1 Clock Cycle (RCD1 = 0, RCD0 = 1) Rev.1.00 Jun. 07, 2006 Page 262 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.11.8 Controlling Precharge Cycle When the time between the PALL or PRE command and the subsequent ACTV or REF command does not meet a given specification, the Tp cycles can be extended by one to four cycles by bits TPC1 and TPC0 in DRACCR. Set the bit according to the SDRAM to be used and the frequency of this LSI so that the number of Tp cycles can be optimal. Figures 6.65 and 6.66 show a timing example when the two Tp cycles are inserted. Bits TPC1 and TPC0 are effective for the Tp cycle in a refresh cycle. Tp1 SD Address bus Precharge-sel CS RAS CAS WE CKE DQMLU DQMLL D15 to D8 D7 to D0 BS RD/WR PALL NOP ACTV READ NOP High Row address Row address Tp2 Tr Tc1 Tcl Tc2 Column address Figure 6.65 Read Timing Example of Two Precharge Cycles (TPC1 = 0, TPC0 = 1, CAS Latency = 2) Rev.1.00 Jun. 07, 2006 Page 263 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Tp1 SD Address bus Precharge-sel CS RAS CAS WE CKE DQMLU DQMLL D15 to D8 D7 to D0 BS RD/WR PALL Tp2 Tr Tc1 Tc2 Row address Row address Column address High NOP ACTV NOP WRIT Figure 6.66 Write Timing Example of Two Precharge Cycles (TPC1 = 0, TPC0 = 1) Rev.1.00 Jun. 07, 2006 Page 264 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.11.9 Controlling Clock Suspend Insertion When the SDRAM space is read, the read data settling cycle can be inserted for one cycle using the clock suspend mode. To enter the clock suspend mode, set the CKSPE bit in SDCR and the OEE bit in DRAMCR to 1and enable the CKE pin. Figure 6.67 shows a read timing example when CKSPE = 1. Tp SD Address bus Precharge-sel CS RAS CAS WE CKE Row address Row address Tr Tc1 Tcl Tsp Tc2 Tc1 Tcl Tsp Tc2 Column address 1 Column address 2 DQMLU DQMLL D15 to D8 D7 to D0 BS RD/WR PALL ACTV READ NOP READ NOP Figure 6.67 Read Timing Example when CKSPE = 1 (CAS Latency = 2) Rev.1.00 Jun. 07, 2006 Page 265 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.11.10 Controlling Write-Precharge Delay In an SDRAM write cycle, a certain time is required until the write operation is completed inside of the SDRAM. When the time between the WRIT command and the subsequent PALL command does not meet a given specification, the Trwl cycle can be inserted for one cycle by the TRWL bit in SDCR. Whether or not to insert the Trwl cycle depends on the SDRAM to be used and the frequency of this LSI. Figure 6.68 shows a timing example when one Trwl cycle is inserted. Tp SD Address bus Precharge-sel CS RAS CAS WE CKE DQMLU DQMLL D15 to D8 D7 to D0 BS RD/WR PALL ACTV NOP WRIT NOP High Row address Row address Tr Tc1 Tc2 Trwl Column address Figure 6.68 Write Timing Example when Write-Precharge Delay Cycle Insertion (TRWL = 1) Rev.1.00 Jun. 07, 2006 Page 266 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.11.11 Controlling Byte and Word Accesses When 16-bit bus SDRAM is used, byte and word accesses are performed through the control of DQMLU and DQMLL. Figures 6.69 and 6.70 show control timing examples of the DQM signals in the big endian format. Figure 6.71 shows a connection example when the DQM signals are used for the byte and word control. Tp SD Address bus Precharge-sel CS RAS CAS WE CKE DQMLU DQMLL D15 to D8 D7 to D0 BS RD/WR PALL ACTV READ NOP Hi-Z High High Row address Row address Tr Tc1 Tcl Tc2 Column address Figure 6.69 Control Timing Example of Byte Control by DQM in 16-Bit Access Space (Read Access with Lowest Bit of Address = B'0) Rev.1.00 Jun. 07, 2006 Page 267 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Tp SD Address bus Precharge-sel CS RAS CAS WE CKE DQMLU DQMLL D15 to D8 D7 to D0 BS RD/WR PALL Tr Tc1 Tcl Tc2 Row address Row address Column address High ACTV READ NOP Figure 6.70 Control Timing Example of Word Control by DQM in 16-Bit Access Space (Read Access with Lowest Bit of Address = B'0, CAS Latency = 2) Rev.1.00 Jun. 07, 2006 Page 268 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) This LSI (Address shifted by 8 bis) RAS CAS WE DQMLU DQMLL SD OE/CKE CS 64-Mbit synchronous DRAM (1 Mwords x 16 bits x 4 banks) 10-bit column address RAS CAS WE DQMU DQML CLK CKE CS Row address: Column address: Bank select address: A11 to A0 A9 to A0 A11/A10 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 D15 to D0 A11 (BA1) A10 (BA0) A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 DQ15 to DQ0 Figure 6.71 Connection Example of DQM Byte/Word Control 6.11.12 Fast-Page Access Operation Besides an accessing method in which this LSI outputs a row address every time it accesses the SDRAM (called full access or normal access), some SDRAMs have a fast-page mode function in which fast speed access can be achieved by modifying only a column address with the same row address output when consecutive accesses are made to the same row address. The fast-page mode can be used by setting the BE bit in DRAMCR to 1. Rev.1.00 Jun. 07, 2006 Page 269 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) (1) Fast-Page Mode Operation Timing When access cycles to the SDRAM space are continued and the row addresses of the consecutive two cycles are the same, a column address output cycle follows. The row address bits to be compared are decided by bits MXC1 and MXC0 in DRAMCR. A fast-page mode access is performed when the access data size exceeds the bus width of the SDRAM and when consecutive accesses to the SDRAM are generated. Figures 6.72 and 6.73 show longword access timing of the 16-bit bus SDRAM and word access timing of the 8-bit bus SDRAM, respectively. Tp SD Address bus Precharge-sel CS RAS CAS WE CKE DQMLU DQMLL High Tr Tc1 Tc2 Tc1 Tc2 Row address Row address Column address 1 Column address 2 D15 to D8 D7 to D0 BS RD/WR PALL ACTV NOP WRIT NOP WRIT Figure 6.72 Longword Write Timing in 16-Bit Access Space (BE = 1, RCDM = 0) Rev.1.00 Jun. 07, 2006 Page 270 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Tp SD Tr Tc1 Tcl Tc2 Tc1 Tcl Tc2 Address bus Precharge-sel Row address Row address Column address 1 Column address 2 CS RAS CAS WE CKE DQMLL D7 to D0 High BS RD/WR PALL ACTV READ NOP READ NOP Figure 6.73 Word Read Timing in 8-Bit Access Space (BE = 1, RCDM = 0, CAS Latency = 2) Rev.1.00 Jun. 07, 2006 Page 271 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) (2) RAS Down Mode Set the RCDM and BE bits in DRAMCR to 1 to make a transition to the RAS down mode. The RCDM bit is enabled only when the BE bit is set to 1. Even if the fast-page mode is selected, the DRAM space is not consecutively accessed and other spaces may be accessed. The RAS signal can be held low during other space accesses. Similarly to the DRAM RAS down mode, the READ or WRIT command can be issued without the ACTV command. However, two DQM cycles are always inserted for a SDRAM read cycle. Figures 6.74 and 6.75 show a timing example of RAS down mode. The next cycle after one of the following conditions is satisfied is a full access cycle. * When a refresh cycle is performed during RAS down mode * When a self-refresh is performed * When a transition to software standby mode is made * When the external bus requested by the BREQ signal is released * When either the RCDM or BE bit is cleared to 0 * When setting the SDRAM mode register Some SDRAMs have a limitation on the time to hold each bank active. When such SDRAM is in use, if the user program cannot control the time (such as software standby or sleep mode), select the auto-refresh or self-refresh so that the given specification can be satisfied. If a refresh cycle is not used, the user program must control the time. Clear the RCDM bit to 0 for write access to SCKCR to set the clock frequencies. For SCKCR, see section 22, Clock Pulse Generator. (3) RAS Up Mode Clear the RCDM bit in DRAMCR to 0 to set the RAS up mode. Whenever a SDRAM space access is halted and other spaces are accessed, the next cycle is the PALL command cycle. Only when the SDRAM space continues to be accessed, the fast-page mode access is performed. Rev.1.00 Jun. 07, 2006 Page 272 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) SDRAM space read Tp SD Address bus Precharge-sel CS RAS CAS WE CKE DQMLU DQMLL High Row address Row address External space read Tc2 T1 T2 SDRAM space read Tc1 Tcl Tc2 Tr Tc1 Tcl Column address 1 External address External address Column address 2 D15 to D8 D7 to D0 BS RD/WR PALL ACTV READ NOP READ NOP Figure 6.74 Timing Example of RAS Down Mode (BE = 1, RCDM = 1, CAS Latency = 2) Rev.1.00 Jun. 07, 2006 Page 273 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) SDRAM space read Tp SD Address bus Precharge-sel CS RAS CAS WE CKE DQMLU DQMLL D15 to D8 D7 to D0 BS RD/WR PALL ACTV READ High Tr Tc1 Tcl Tc2 External space read T1 T2 SDRAM space read Tc1 Tc2 Row address Row address Column address 1 External address Column address 2 External address NOP WRIT Figure 6.75 Timing Example of RAS Down Mode (BE = 1, RCDM = 1, CAS Latency = 2) Rev.1.00 Jun. 07, 2006 Page 274 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.11.13 Refresh Control This LSI includes a DRAM refresh control function. The refresh method is the auto-refresh. Selfrefresh cycles can be performed in software standby mode. The refresh control function is enabled when area 2 is specified as the SDRAM space by the DRAME and DTYPE bits in DRAMCR. (1) Auto-Refresh Mode Set the RFSHE bit in REFCR to 1 to select the auto-refresh. An auto-refresh cycle is performed when the value set in RTCOR matches the RTCNT value (compare match). RTCNT is an up-counter operated on the input clock specified bits RTCK2 to RTCK0 in REFCR. RTCNT is initialized upon the compare match and restarts to count up with H'00. Accordingly, an auto-refresh cycle is repeated at intervals specified by bits RTCK2 to RTCK0 in RTCOR. Set the bits so that the required refresh intervals of the DRAM must be satisfied. Since setting bits RTCK2 to RTCK0 starts RTCNT to count up, set RTCNT and RTCOR before setting bits RTCK2 to RTCK0. When changing RTCNT and RTCOR, the count operation should be halted. When changing bits RTCK2 to RTCK0, change them only after disabling external bus release and, if the write data buffer function is in use, disabling the write data buffer function and reading the external space. The external space cannot be accessed during auto-refresh. Rev.1.00 Jun. 07, 2006 Page 275 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Figure 6.76 shows auto-refresh cycle timing. For details, see section 6.10.12, Refresh Control. TRp SD TRr TRc1 TRc2 Address bus Precharge-sel CS RAS CAS WE CKE BS RD/WR PALL REF High High High NOP Figure 6.76 Auto-Refresh Operation Rev.1.00 Jun. 07, 2006 Page 276 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) The time between the PALL or PRE command and the subsequent REF command can be changed by wait cycle insertion. The number of wait cycles is selected from one to three cycles by bits TPC1 and TPC0 in DRACCR. Set the bit according to the SDRAM to be used and the frequency of this LSI so that the number of wait cycles can be optimal. Figure 6.77 shows a timing example when the one wait cycles are inserted. TRp1 SD TRp2 TRr TRc1 TRc2 Address bus Precharge-sel CS RAS CAS WE High High High PALL NOP REF NOP CKE BS RD/WR Figure 6.77 Auto-Refresh Timing (TPC1 = 0, TPC0 = 1) Rev.1.00 Jun. 07, 2006 Page 277 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) When the time between the REF command and the subsequent ACTV command does not meet a given specification, a wait cycle can be inserted for one to seven cycles during a refresh cycle by bits RLW2 to RLW0 in REFCR. Set the bit according to the SDRAM to be used and the frequency of this LSI so that the number of wait cycles can be optimal. Figure 6.78 shows a timing example when the one wait cycle is inserted. TRp SD TRr TRc1 TRcw TRc2 Address bus Precharge-sel CS RAS CAS WE CKE BS RD/WR PALL REF High High High NOP Figure 6.78 Auto-Refresh Timing (TPC1 = 0, TPC0 = 0, RLW2 = 0, RLW1 = 0, RLW0 = 1) Rev.1.00 Jun. 07, 2006 Page 278 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) (2) Self-Refresh Mode Some SDRAMs have a self-refresh mode (battery backup mode). The self-refresh mode is a kind of standby mode and refresh timing and refresh address are controlled internally. The self-refresh mode is selected by setting the RFSHE and SLFRF bits in REFCR to 1. The SELF command is issued as shown in figure 6.79 by executing the SLEEP instruction to enter the self-refresh mode. When an auto-refresh is requested on a transition to the standby mode, the auto-refresh is first performed and then the self-refresh mode is entered. When making a transition to the self-refresh mode, set the OEE bit in SBYCR to 1 and connect the CKE pin. When the self-refresh mode is used, do not clear the OPE bit in SBYCR to 0. TRp SD TRr Software standby TRc2 TRc3 Address bus Precharge-sel CS RAS CAS WE CKE High High PALL SELF NOP BS RD/WR Figure 6.79 Self-Refresh Timing (TPC1 = 0, TPC0 = 0, RCW1 = 0, RCW0 = 0, RLW1 = 0, RLW0 = 0) Rev.1.00 Jun. 07, 2006 Page 279 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Some DRAMs with the self-refresh mode have a given time between cancellation of the selfrefresh mode and the subsequent command issued cycle. From one to seven of precharge cycles immediately after cancellation of the self-refresh mode can be inserted. Normal precharge is also performed according to bits TPC1 and TPC0 in DRACCR. Set the precharge time including the normal precharge so that the precharge time immediately after a self-refresh cycle is optimal. Figure 6.80 shows a timing example when one precharge cycle is added. SDRAM space write TRc2 TRc3 TRp1 Tp Tr Tc1 Tc2 Software standby SD Address bus Precharge-sel CS RAS CAS WE CKE DQMUU, DQMUL DQMLU, DQMLL Data bus BS RD/WR NOP PALL ACTV NOP WRITE Figure 6.80 Timing Example when 1 Precharge Cycle Added (TPC2 to TPC0 = H'1, TPC1 = 0, TPC0 = 0) Rev.1.00 Jun. 07, 2006 Page 280 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) (3) Refresh and All-Module Clock Stop Mode This LSI is entered in all-module clock stop mode by the following operation: Stop the clocks of all on-chip peripheral modules by setting the ACSE bit in MSTPCR to 1 (MSTPCRA, MSTPCRB = H'FFFFFFFF) or run only the 8-bit timer (MSTPCRA, MSTPCRB = H'F[C to F]FFFFFF), then execute the SLEEP instruction to enter the sleep mode. In all-module clock stop mode, clocks for the bus controller and I/O ports are stopped. Since the clock for the bus controller is stopped, an auto-refresh cycle cannot be performed. When external SDRAM is used and the contents of the SDRAM in sleep mode should be held, clear the ACSE bit in MSTPCE to 0. For details, see section 23.2.2, Module Stop Control Registers A and B (MSTPCR and MSTPCRB). 6.11.14 Setting SDRAM Mode Register To use SDRAM, the mode register must be specified after a power-on reset. Setting the MRSE bit in SDCR to 1 enables the SDRAM mode register setting. After this, write to the SDRAM space in bytes. When the value to be set in the SDRAM mode register is x, write to the following memory location (address). The value of x is written to the SDRAM mode register. * H'4000000/H'400000 + x for 8-bit bus SDRAM * H'4000000/H'400000 + 2x for 16-bit bus SDRAM The SDRAM mode register latches the address signals when the MRS command is issued. This LSI does not support the burst read/burst write mode of SDRAM. When setting the SDRAM mode register, use the burst read/single write mode and set the burst length to 1. Setting in the SDRAM mode register must be consistent with that in the bus controller. Rev.1.00 Jun. 07, 2006 Page 281 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Figure 6.81 shows the timing of setting SDRAM mode register. Tp SD Address bus Mode register setting Tr Tc1 Tc2 Precharge-sel CS RAS CAS WE CKE BS RD/WR PALL Mode register setting High High High NOP MRS NOP Figure 6.81 Timing of Setting SDRAM Mode Register 6.11.15 SDRAM Interface and Single Address Transfer by DMAC When fast-page mode (BE = 1) is set for the SDRAM space, either fast-page access or full access can be selected, by the setting of bit DDS in DRAMCR, for the single address transfer by the DMAC where the SDRAM space is specified as the transfer source or destination. At the same time, the output timing of the DACK and BS signals can be changed. When BE = 0, a full access to the SDRAM space is performed with a single address transfer regardless of the setting of bit DDS. However, the output timing of the DACK and BS signals can be changed by the setting of bit DDS. The assertion timing of the DACK signals can be changed by the bit DKC in BCR1. The output timing of the DACK signal can be independently set by the bits TRWL and CKSPE in SDCR and bit DCK in BCR1 regardless of the setting of bit DDS. Rev.1.00 Jun. 07, 2006 Page 282 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) (1) When DDS = 1 A fast-page access is performed regardless of the bus master, only according to the address. The DACK signal is asserted within the Tc1 cycle in both read and write accesses. Figures 6.82 and 6.83 show the output timing example of the DACK signal when DDS = 1. Tp SD Address bus Precharge-sel CS RAS CAS WE CKE DQMLU DQMLL D15 to D8 D7 to D0 BS RD/WR DACK PALL ACTV NOP WRIT NOP WRIT High Row address Row address Tr Tc1 Tc2 Tc1 Tc2 Column address 1 Column address 2 Figure 6.82 Output Timing Example of DACK when DDS = 1 (Write) Rev.1.00 Jun. 07, 2006 Page 283 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Tp SD Address bus Precharge-sel CS RAS CAS WE CKE DQMLU DQMLL D15 to D8 D7 to D0 BS RD/WR DACK PALL Tr Tc1 Tcl Tc2 Tc1 Tcl Tc2 Row address Row address Column address 1 Column address 2 High ACTV READ NOP READ NOP Figure 6.83 Output Timing Example of DACK when DDS = 1 (Read, CAS Latency = 2) Rev.1.00 Jun. 07, 2006 Page 284 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) (2) When DDS = 0 Single address transfer by the DMAC takes place as a full access (normal access) to the SDRAM space. The DACK signal is asserted within the Tr cycle and the BS signal is also asserted in the Tr cycle. When the SDRAM space is accessed with other than the single address transfer by the DMAC, a fast-page access is available. Figures 6.84 and 6.85 show an output timing example of the DACK signal when DDS = 0. Tp SD Address bus Precharge-sel CS RAS CAS WE CKE DQMLU DQMLL D15 to D8 D7 to D0 BS RD/WR DACK PALL ACTV NOP WRIT High Row address Row address Tr Tc1 Tc2 Column address Figure 6.84 Output Timing Example of DACK when DDS = 0 (Write) Rev.1.00 Jun. 07, 2006 Page 285 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Tp SD Address bus Precharge-sel CS RAS CAS WE CKE DQMLU DQMLL D15 to D8 D7 to D0 BS RD/WR DACK PALL Tr Tc1 Tcl Tc2 Row address Row address Cloumn address High ACTV READ NOP Figure 6.85 Output Timing Example of DACK when DDS = 0 (Read, CAS Latency = 2) Rev.1.00 Jun. 07, 2006 Page 286 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) (3) When TRWL = 1 When the SDRAM interface is written to, one Trwl cycle is inserted after the Tc2 cycle. The DACK signal stays asserted until the end of the Trwl cycle. The hold time of data output from an external device can be extended by one cycle. Figure 6.86 shows an output timing example of the DACK signal when TRWL = 1 with DDS = 1 and DKC = 0. Tp SD Address bus Precharge-sel CS RAS CAS WE CKE DQMLU DQMLL D15 to D8 D7 to D0 BS RD/WR DACK PALL ACTV NOP WRIT NOP WRIT NOP High Row address Row address Tr Tc1 Tc2 Trwl Tc1 Tc2 Trwl Column address 1 Column address 2 Figure 6.86 Output Timing Example of DACK when TRWL = 1 (Write) Rev.1.00 Jun. 07, 2006 Page 287 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) (4) When CKSPE = 1 When the SDRAM space is read, the read data settling cycle can be inserted for one cycle using the clock suspend mode. To enter the clock suspend mode, set the OEE bit to 1, and connect the CKE pin. Figure 6.87 shows an output timing example of the DACK signal when CKSPE = 1 with DDS = 1 and DKC = 0. Tp SD Address bus Precharge-sel CS RAS CAS WE CKE DQMLU DQMLL D15 to D8 D7 to D0 BS RD/WR DACK PALL ACTV READ NOP READ NOP Row address Row address Tr Tc1 Tcl Tsp Tc2 Tc1 Tcl Tsp Tc2 Column address 1 Column address 2 Figure 6.87 Output Timing Example of DACK when CKSPE = 1 (Read, CAS Latency = 2) Rev.1.00 Jun. 07, 2006 Page 288 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) (5) When DKC = 1 With DKC = 1, the DACK signal is asserted a half cycle earlier compared to the case when DKC = 0. In fast-page access, the DACK signal continues to be low. In this case, bus cycles can be distinguished by the BS output timing. Figure 6.88 shows an output timing example of the DACK signal when DKC = 1 and DDS = 1. Figure 6.89 shows an output timing example of the DACK signal when DKC = 1 and DDS = 0. Tp SD Address bus Precharge-sel CS RAS CAS WE CKE DQMLU DQMLL High Row address Row address Tr Tc1 Tc2 Tc1 Tc2 Column address 1 Column address 2 D15 to D8 D7 to D0 BS RD/WR DACK PALL ACTV NOP WRIT NOP WRIT Figure 6.88 Output Timing Example of DACK when DKC = 1 and DDS = 1 (Write) Rev.1.00 Jun. 07, 2006 Page 289 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Tp SD Address bus Precharge-sel CS RAS CAS WE CKE DQMLU DQMLL D15 to D8 D7 to D0 BS RD/WR DACK PALL Tr Tc1 Tc2 Row address Row address Cloumn address High ACTV NOP WRIT Figure 6.89 Output Timing Example of DACK when DKC = 1 and DDS = 0 (Write) Rev.1.00 Jun. 07, 2006 Page 290 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.12 Idle Cycle In this LSI, idle cycles can be inserted between the consecutive external accesses. By inserting the idle cycle, data conflicts between ROM read cycle whose output floating time is long and an access cycle from/to high-speed memory or I/O interface can be prevented. 6.12.1 Operation When this LSI consecutively accesses external address space, it can insert an idle cycle between bus cycles in the following four cases. These conditions are determined by the sequence of read and write and previously accessed area. 1. When read cycles of different areas in the external address space occur consecutively 2. When an external write cycle occurs immediately after an external read cycle 3. When an external read cycle occurs immediately after an external write cycle 4. When an external access occurs immediately after a DMAC single address transfer (write cycle) Up to four idle cycles can be inserted under the conditions shown above. The number of idle cycles to be inserted should be specified to prevent data conflicts between the output data from a previously accessed device and data from a subsequently accessed device. Under conditions 1 and 2, which are the conditions to insert idle cycles after read, the number of idle cycles can be selected from setting A specified by bits IDLCA1 and IDLCA0 in IDLCR or setting B specified by bits IDLCB1 and IDLCB0 in IDLCR: Setting A can be selected from one to four cycles, and setting B can be selected from one or two to four cycles. Setting A or B can be specified for each area by setting bits IDLSEL7 to IDLSEL0 in IDLCR. Note that bits IDLSEL7 to IDLSEL0 correspond to the previously accessed area of the consecutive accesses. The number of idle cycles to be inserted under conditions 3 and 4, which are conditions to insert idle cycles after write, can be determined by setting A as described above. After the reset release, IDLCR is initialized to four idle cycle insertion under all conditions 1 to 4 shown above. Table 6.28 shows the correspondence between conditions 1 to 4 and number of idle cycles to be inserted for each area. Table 6.29 shows the correspondence between the number of idle cycles to be inserted specified by settings A and B, and number of cycles to be inserted. Rev.1.00 Jun. 07, 2006 Page 291 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Table 6.28 Number of Idle Cycle Insertion Selection in Each Area Bit Settings IDLSn Insertion Condition n Setting 0 1 IDLSELn n = 0 to 7 0 1 Write after read 0 0 1 0 1 Read after write 2 0 1 External access after single address 3 transfer 0 1 A B A B A B A B A B A B 0 Area of Previous Access 1 2 3 4 5 6 7 Consecutive reads in different areas 1 Invalid A B A B A B A B A B Invalid A B A B A B A B A B Invalid A Invalid A [Legend] A: Number of idle cycle insertion A is selected. B: Number of idle cycle insertion B is selected. Invalid: No idle cycle is inserted for the corresponding condition. Table 6.29 Number of Idle Cycles Inserted Bit Settings A IDLCA1 0 0 1 1 IDLCA0 0 1 0 1 IDLCB1 0 0 1 1 B IDLCB0 0 1 0 1 Number of Cycles 0 1 2 3 4 Rev.1.00 Jun. 07, 2006 Page 292 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) (1) Consecutive Reads in Different Areas If consecutive reads in different areas occur while bit IDLS1 in IDLCR is set to 1, idle cycles specified by bits IDLCA1 and IDLCA0 when bit IDLSELn in IDLCR is cleared to 0, or bits IDLCB1 and IDLCB0 when bit IDLSELn is set to 1 are inserted at the start of the second read cycle (n = 0 to 7). Figure 6.90 shows an example of the operation in this case. In this example, bus cycle A is a read cycle for ROM with a long output floating time, and bus cycle B is a read cycle for SRAM, each being located in a different area. In (a), an idle cycle is not inserted, and a conflict occurs in bus cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted, and a data conflict is prevented. Bus cycle A T1 B Address bus CS (area A) CS (area B) RD T2 T3 Bus cycle B T1 T2 Bus cycle A T1 T2 T3 Bus cycle B Ti T1 T2 Data bus Data conflict Data hold time is long. (a) No idle cycle inserted (IDLS1 = 0) (b) Idle cycle inserted (IDLS1 = 1, IDLSELn = 0, IDLCA1 = 0, IDLCA0 = 0) Figure 6.90 Example of Idle Cycle Operation (Consecutive Reads in Different Areas) Rev.1.00 Jun. 07, 2006 Page 293 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) (2) Write after Read If an external write occurs after an external read while bit IDLS0 in IDLCR is set to 1, idle cycles specified by bits IDLCA1 and IDLCA0 when bit IDLSELn in IDLCR is cleared to 0 when IDLSELn = 0, or bits IDLCB1 and IDLCB0 when IDLSELn is set to 1 are inserted at the start of the write cycle (n = 0 to 7). Figure 6.91 shows an example of the operation in this case. In this example, bus cycle A is a read cycle for ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an idle cycle is not inserted, and a conflict occurs in bus cycle B between the read data from ROM and the CPU write data. In (b), an idle cycle is inserted, and a data conflict is prevented. Bus cycle A T1 B Address bus CS (area A) CS (area B) RD LLWR T2 T3 Bus cycle B T1 T2 Bus cycle A T1 T2 T3 Bus cycle B Ti T1 T2 Data bus Data conflict Data hold time is long. (a) No idle cycle inserted (IDLS0 = 0) (b) Idle cycle inserted (IDLS0 = 1, IDLSELn = 0, IDLCA1 = 0, IDLCA0 = 0) Figure 6.91 Example of Idle Cycle Operation (Write after Read) Rev.1.00 Jun. 07, 2006 Page 294 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) (3) Read after Write If an external read occurs after an external write while bit IDLS2 in IDLCR is set to 1, idle cycles specified by bits IDLCA1 and IDLCA0 are inserted at the start of the read cycle (n = 0 to 7). Figure 6.92 shows an example of the operation in this case. In this example, bus cycle A is a CPU write cycle and bus cycle B is a read cycle from the SRAM. In (a), an idle cycle is not inserted, and a conflict occurs in bus cycle B between the CPU write data and read data from an SRAM device. In (b), an idle cycle is inserted, and a data conflict is prevented. Bus cycle A T1 B Address bus CS (area A) CS (area B) RD LLWR Data bus Data conflict Output floating time is long. (a) No idle cycle inserted (IDLS2 = 0) (b) Idle cycle inserted (IDLS2 = 1, IDLCA1 = 0, IDLCA0 = 0) T2 T3 Bus cycle B T1 T2 Bus cycle A T1 T2 T3 Bus cycle B Ti T1 T2 Figure 6.92 Example of Idle Cycle Operation (Read after Write) Rev.1.00 Jun. 07, 2006 Page 295 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) (4) External Access after Single Address Transfer Write If an external access occurs after a single address transfer write while bit IDLS3 in IDLCR is set to 1, idle cycles specified by bits IDLCA1 and IDLCA0 are inserted at the start of the external access (n = 0 to 7). Figure 6.93 shows an example of the operation in this case. In this example, bus cycle A is a single address transfer (write cycle) and bus cycle B is a CPU write cycle. In (a), an idle cycle is not inserted, and a conflict occurs in bus cycle B between the external device write data and this LSI write data. In (b), an idle cycle is inserted, and a data conflict is prevented. Bus cycle A T1 B Address bus CS (area A) CS (area B) LLWR DACK Data bus Data conflict Output floating time is long. (a) No idle cycle inserted (IDLS3 = 0) (b) Idle cycle inserted (IDLS3 = 1, IDLCA1 = 0, IDLCA0 = 0) T2 T3 Bus cycle B T1 T2 Bus cycle A T1 T2 T3 Bus cycle B Ti T1 T2 Figure 6.93 Example of Idle Cycle Operation (Write after Single Address Transfer Write) Rev.1.00 Jun. 07, 2006 Page 296 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) (5) External NOP Cycles and Idle Cycles A cycle in which an external space is not accessed due to internal operations is called an external NOP cycle. Even when an external NOP cycle occurs between consecutive external bus cycles, an idle cycle can be inserted. In this case, the number of external NOP cycles is included in the number of idle cycles to be inserted. Figure 6.94 shows an example of external NOP and idle cycle insertion. No external access Idle cycle (NOP) (remaining) Ti Ti T1 Preceding bus cycle T1 B T2 Tpw T3 Following bus cycle T2 Tpw T3 Address bus CS (area A) CS (area B) RD Data bus Specified number of idle cycles or more including no external access cycles (NOP) (Condition: Number of idle cycles to be inserted when different reads continue: 4 cycles) Figure 6.94 Idle Cycle Insertion Example Rev.1.00 Jun. 07, 2006 Page 297 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) (6) Relationship between Chip Select (CS) Signal and Read (RD) Signal Depending on the system's load conditions, the RD signal may lag behind the CS signal. An example is shown in figure 6.95. In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap between the RD signal in bus cycle A and the CS signal in bus cycle B. Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS signals. In the initial state after reset release, idle cycle indicated in (b) is set. Bus cycle A T1 B Address bus CS (area A) CS (area B) RD T2 T3 Bus cycle B T1 T2 Bus cycle A T1 T2 T3 Bus cycle B Ti T1 T2 Overlap time may occur between the CS (area B) and RD (a) No idle cycle inserted (IDLS1 = 0) (b) Idle cycle inserted (IDLS1 = 1, IDLSELn = 0, IDLCA1 = 0, IDLCA0 = 0) Figure 6.95 Relationship between Chip Select (CS) and Read (RD) Rev.1.00 Jun. 07, 2006 Page 298 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) (7) Idle Cycle for Accessing to DRAM/SDRAM Space In the following read cycles, when the DRAM/SDRAM space is accessed in a full access, the Tp and Tr cycles are also counted as idle cycles. Figures 6.96 and 6.97 show timing examples of full accesses to the DRAM/SDRAM space when four idle cycles are inserted. When accessing the DRAM/SDRAM space, the Ti cycles are inserted so that the sum of the numbers of Tp (precharge), Tr (row address output), and Ti cycles satisfies the specified number of idle cycles. The Ti cycles are inserted before the column address output cycle. While the SDRAM space is accessed in a full access, the CS2 signal is driven low even in an idle cycle. The idle cycle insertion is enabled even in a fast-page access in RAS down mode. The specified number of idle cycles is inserted. Figure 6.98 shows a timing example of the idle cycle insertion in RAS down mode. External space read T1 B Address bus T2 T3 Tp Tr DRAM space read Ti Ti Tc1 Tc2 RD RAS LLCAS Data bus Figure 6.96 Example of DRAM Full Access after External Read (CAST = 0) Rev.1.00 Jun. 07, 2006 Page 299 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) External space (area A) read T1 SD T2 T3 Tp Tr SDRAM space read Ti Ti Tc1 Tcl Tc2 Address bus CS (area A) CS (area 2) RD RAS CAS WE DQMLL Data bus Figure 6.97 Example of SDRAM Full Access after External Read (CAS Latency = 2) Rev.1.00 Jun. 07, 2006 Page 300 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) DRAM space read Tp B Tr Tc1 Tc2 External space read T1 T2 T3 DRAM space write Ti Tc1 Tc2 Address bus RD RAS UCAS, LCAS Data bus WR Idle cycle Figure 6.98 Example of Idle Cycles in RAS Down Mode (Write after Read) Rev.1.00 Jun. 07, 2006 Page 301 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Table 6.30 Idle Cycles in Mixed Accesses to Normal Space and DRAM/SDRAM Space Previous Access IDLS Next Access 3 2 1 0 IDLSEL 7 to 0 1 IDLCA 0 1 IDLCB 0 Idle Cycle Disabled 1 cycle inserted 2 cycles inserted 3 cycles inserted 4 cycles inserted Normal/DRAM/ Normal/DRAM/ SDRAM space SDRAM space read read 0 1 0 0 0 1 1 0 1 0 1 1 0 0 1 1 0 1 0 1 0 cycle inserted 2 cycles inserted 3 cycles inserted 4 cycles inserted Disabled 1 cycle inserted 2 cycles inserted 3 cycles inserted 4 cycles inserted Normal/DRAM/ Normal/DRAM/ SDRAM space SDRAM space read read 0 1 0 0 0 1 1 0 1 0 1 1 0 0 1 1 0 1 0 1 0 cycle inserted 2 cycles inserted 3 cycles inserted 4 cycles inserted Disabled 1 cycle inserted 2 cycles inserted 3 cycles inserted 4 cycles inserted Normal/DRAM/ Normal/DRAM/ SDRAM space SDRAM space write read 0 1 0 0 1 1 0 1 0 1 0 1 0 1 Single address Normal/DRAM/ 0 write SDRAM space 1 write 0 0 1 1 Disabled 1 cycle inserted 2 cycles inserted 3 cycles inserted 4 cycles inserted Rev.1.00 Jun. 07, 2006 Page 302 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.12.2 Pin States in Idle Cycle Table 6.31 shows the pin states in an idle cycle. Table 6.31 Pin States in Idle Cycle Pins A23 to A0 D15 to D0 CSn (n = 7 to 0) LUCAS, LLCAS DQMLU, DQMLL AS RD BS RD/WR AH LHWR, LLWR LUB, LLB CKE OE RAS CAS WE DACKn (n = 3 to 0) Notes: 1. 2. 3. 4. Pin State Contents of following bus cycle High impedance High* High High* High High High High* low High High High High High/Low* High High High Low when accessing the SDRAM in full access cycle Low when reading the SDRAM in full access cycle Low when accessing or writing to the DRAM/SDRAM in full access cycle The pin state varies depending on the DRAM space access/ area access other than the DRAM space, or RAS up mode/RAS down mode. For details, see figures 6.96 and 6.98. 4 3 2 1 Rev.1.00 Jun. 07, 2006 Page 303 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.13 Bus Release This LSI can release the external bus in response to a bus request from an external device. In the external bus released state, the internal bus master continue operation as long as there is no external access. In addition, in the external bus released state, the BREQO signal can be driven low to output a bus request externally. 6.13.1 Operation In external extended mode, when the BRLE bit in BCR1 is set to 1, and the ICR bit for the corresponding pin is set to 1, the bus can be released to the external. Driving the BREQ pin low issues an external bus request to this LSI. When the BREQ pin is sampled, at the prescribed timing, the BACK pin is driven low, and the address bus, data bus, and bus control signals are placed in the high-impedance state, establishing the external bus released state. For ICR, see section 9, I/O Ports. In the external bus released state, the CPU, DTC, and DMAC can access the internal space using the internal bus. When any one of the CPU, DTC, and DMAC attempts to accesses the external address space, it temporarily defers initiation of the bus cycle, and waits for the bus request from the external bus master to be canceled. In the external bus released state, certain operations are suspended as follows until the bus request from the external bus master is canceled: * When a refresh is requested, refresh control is suspended. * When the SLEEP instruction is executed to enter software standby mode or all-module clockstop mode, control for software standby mode or all-module clock-stop mode is suspended. * When SCKCR is written to set the clock frequencies, changing of clock frequencies is suspended. For SCKCR, see section 22, Clock Pulse Generator. If the BREQOE bit in BCR1is set to 1, the BREQO pin can be driven low to request cancellation of the bus request when any of the following requests are issued. * When any one of the CPU, DTC, and DMAC attempts to access the external address space * When a refresh is requested * When a SLEEP instruction is executed to place the chip in software standby mode or allmodule-clock-stop mode * When SCKCR is written to set the clock frequencies Rev.1.00 Jun. 07, 2006 Page 304 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) If an external bus release request, external access, and a refresh request occur simultaneously, the order of priority is as follows: Refresh > External bus release > External access by CPU, DTC, and DMAC 6.13.2 Pin States in External Bus Released State Table 6.32 shows pin states in the external bus released state. Table 6.32 Pin States in Bus Released State Pins A23 to A0 D15 to D0 BS CSn (n = 7 to 0) AS AH RD/WR LUCAS, LLCAS RD RAS CAS WE DQMLU, DQMLL CKE OE LUB, LLB LHWR, LLWR DACKn (n = 3 to 0) Pin State High impedance High impedance High impedance High impedance High impedance High impedance High impedance High impedance High impedance High impedance High impedance High impedance High impedance High impedance High impedance High impedance High impedance High Rev.1.00 Jun. 07, 2006 Page 305 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.13.3 Transition Timing Figures 6.99 and 6.100 show the timing of transition to the bus released state. External space access cycle T1 B T2 External bus released state CPU cycle Address bus Data bus CSn AS RD LHWR, LLWR BREQ Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z BACK BREQO [1] [2] [3] [4] [7] [5] [8] [6] [1] A low level of the BREQ signal is sampled at the rising edge of the B signal. [2] The bus control signals are driven high at the end of the external space access cycle. It takes two cycles or more after the low level of the BREQ signal is sampled. [3] The BACK signal is driven low, releasing bus to the external bus master. [4] The BREQ signal state sampling is continued in the external bus released state. [5] A high level of the BREQ signal is sampled. [6] The external bus released cycles are ended one cycle after the BREQ signal is driven high. [7] When the external space is accessed by an internal bus master during external bus released while the BREQOE bit is set to 1, the BREQO signal goes low. [8] Normally the BREQO signal goes high at the rising edge of the BACK signal. Figure 6.99 Bus Released State Transition Timing (SRAM Interface is Not Used) Rev.1.00 Jun. 07, 2006 Page 306 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) External access cycle T1 SD T2 External bus released state CPU cycle Address bus Data bus Precharge-sel CS2 RAS CAS WE CKE DQMLU, DQMLL BREQ BACK BREQO Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z NOP [1] PALL NOP [2] [3] [4] [5] [8] [6] NOP [9] [7] [1] A low level of the BREQ signal is sampled at the rising edge of the B signal. [2] The PALL command is issued. [3] The bus control signals are driven high at the end of the external access cycle. It takes two cycles or more after the low level of the BREQ signal is sampled. [4] The BACK signal is driven low, releasing bus to the external bus master. [5] The BREQ signal state sampling is continued in the external bus released state. [6] A high level of the BREQ signal is sampled. [7] The BACK signal is driven high, ending external bus release cycle after one cycle. [8] When the external space is accessed by an internal bus master or a refresh cycle is requested during external bus released while the BREQOE bit is set to 1, the BREQO signal goes low. [9] Normally the BREQO signal goes high at the rising edge of the BACK signal. Figure 6.100 Bus Released State Transition Timing (SRAM Interface is Used) Rev.1.00 Jun. 07, 2006 Page 307 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.14 6.14.1 Internal Bus Access to Internal Address Space The internal address spaces of this LSI are the on-chip ROM space, on-chip RAM space, and register space for the on-chip peripheral modules. The number of cycles necessary for access differs according the space. Table 6.33 shows the number of access cycles for each on-chip memory space. Table 6.33 Number of Access Cycles for On-Chip Memory Spaces Access Space On-chip ROM space On-chip RAM space Access Read Write Read Write Number of Access Cycles One I cycle Three I cycles One I cycle One I cycle In access to the registers for on-chip peripheral modules, the number of access cycles differs according to the register to be accessed. When the dividing ratio of the operating clock of a bus master and that of a peripheral module is 1 : n, synchronization cycles using a clock divided by 0 to n-1 are inserted for register access in the same way as for external bus clock division. Table 6.34 lists the number of access cycles for registers of on-chip peripheral modules. Table 6.34 Number of Access Cycles for Registers of On-Chip Peripheral Modules Number of Cycles Module to be Accessed DMAC registers Read Two I Write Three I Write Data Buffer Function Disabled Disabled MCU operating mode, clock pulse generator, Two I power-down control registers, interrupt controller, bus controller, and DTC registers I/O port registers of PFCR and WDT I/O port registers other than PFCR and PORTM, TPU, PPG, TMR, SCI, SCI0 to SCI2, SCI4, A/D, and D/A registers I/O port registers of PORTM, USB, SCI5, and SCI6 Two P Two P Three P Disabled Enabled Three P Enabled Rev.1.00 Jun. 07, 2006 Page 308 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.15 6.15.1 Write Data Buffer Function Write Data Buffer Function for External Data Bus This LSI has a write data buffer function for the external data bus. Using the write data buffer function enables internal accesses in parallel with external writes or DMAC single address transfers. The write data buffer function is made available by setting the WDBE bit to 1 in BCR1. Figure 6.101 shows an example of the timing when the write data buffer function is used. When this function is used, if an external address space write or a DMAC single address transfer continues for two cycles or longer, and there is an internal access next, an external write only is executed in the first two cycles. However, from the next cycle onward, internal accesses (on-chip memory or internal I/O register read/write) and the external address space write rather than waiting until it ends are executed in parallel. On-chip memory read Peripheral module read External write cycle I Internal address bus On-chip memory 1 On-chip memory 2 Peripheral module address T1 B T2 T3 Address bus External address Write to external space CSn LHWR, LLWR D15 to D0 Figure 6.101 Example of Timing when Write Data Buffer Function is Used Rev.1.00 Jun. 07, 2006 Page 309 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.15.2 Write Data Buffer Function for Peripheral Modules This LSI has a write data buffer function for the peripheral module access. Using the write data buffer function enables peripheral module writes and on-chip memory or external access to be executed in parallel. The write data buffer function is made available by setting the PWDBE bit in BCR2 to 1. For details on the on-chip peripheral module registers, see table 6.34, Number of Access Cycles for Registers of On-Chip Peripheral Modules in section 6.14, Internal Bus. Figure 6.102 shows an example of the timing when the write data buffer function is used. When this function is used, if an internal I/O register write continues for two cycles or longer and then there is an on-chip RAM, an on-chip ROM, or an external access, internal I/O register write only is performed in the first two cycles. However, from the next cycle onward an internal memory or an external access and internal I/O register write are executed in parallel rather than waiting until it ends. On-chip memory read Peripheral module write I Internal address bus P Internal I/O address bus Internal I/O data bus Peripheral module address Figure 6.102 Example of Timing when Peripheral Module Write Data Buffer Function is Used Rev.1.00 Jun. 07, 2006 Page 310 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.16 Bus Arbitration This LSI has bus arbiters that arbitrate bus mastership operations (bus arbitration). This LSI incorporates internal access and external access bus arbiters that can be used and controlled independently. The internal bus arbiter handles the CPU, DTC, and DMAC accesses. The external bus arbiter handles the external access by the CPU, DTC, and DMAC, refresh, and external bus release request (external bus master). The bus arbiters determine priorities at the prescribed timing, and permit use of the bus by means of the bus request acknowledge signal. 6.16.1 Operation The bus arbiter detects the bus masters' bus request signals, and if the bus is requested, sends a bus request acknowledge signal to the bus master. If there are bus requests from more than one bus master, the bus request acknowledge signal is sent to the one with the highest priority. When a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is canceled. The priority of the internal bus arbitration: DMAC > DTC > CPU The priority of the external bus arbitration: Refresh > External bus release request > External access by the CPU, DTC, or DMAC If the DMAC or DTC accesses continue, the CPU can be given priority over the DMAC or DTC to execute the bus cycles alternatively between them by setting the IBCCS bit in BCR2. In this case, the priority between the DMAC and DTC does not change. An internal bus access by the CPU, DTC, or DMAC, an external bus release, and the refresh can be executed in parallel. Rev.1.00 Jun. 07, 2006 Page 311 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.16.2 Bus Transfer Timing Even if a bus request is received from a bus master with a higher priority over that of the bus master that has taken control of the bus and is currently operating, the bus is not necessarily transferred immediately. There are specific timings at which each bus master can release the bus. (1) CPU The CPU is the lowest-priority bus master, and if a bus request is received from the DTC or DMAC, the bus arbiter transfers the bus to the bus master that issued the request. The timing for transfer of the bus is at the end of the bus cycle. In sleep mode, the bus is transferred synchronously with the clock. Note, however, that the bus cannot be transferred in the following cases. * The word or longword access is performed in some divisions. * Stack handling is performed in multiple bus cycles. * Transfer data read or write by memory transfer instructions, block transfer instructions, or TAS instruction. (In the block transfer instructions, the bus can be transferred in the write cycle and the following transfer data read cycle.) * From the target read to write in the bit manipulation instructions or memory operation instructions. (In an instruction that performs no write operation according to the instruction condition, up to a cycle corresponding the write cycle) (2) DTC The DTC sends the internal bus arbiter a request for the bus when an activation request is generated. When the DTC accesses an external bus space, the DTC first takes control of the bus from the internal bus arbiter and then requests a bus to the external bus arbiter. Once the DTC takes control of the bus, the DTC continues the transfer processing cycles. If a bus master whose priority is higher than the DTC requests the bus, the DTC transfers the bus to the higher priority bus master. If the IBCCS bit in BCR2 is set to 1, the DTC transfers the bus to the CPU. Note, however, that the bus cannot be transferred in the following cases. Rev.1.00 Jun. 07, 2006 Page 312 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) * During transfer information read * During the first data transfer * During transfer information write back The DTC releases the bus when the consecutive transfer cycles completed. (3) DMAC The DMAC sends the internal bus arbiter a request for the bus when an activation request is generated. When the DMAC accesses an external bus space, the DMAC first takes control of the bus from the internal bus arbiter and then requests a bus to the external bus arbiter. After the DMAC takes control of the bus, it may continue the transfer processing cycles or release the bus at the end of every bus cycle depending on the conditions. The DMAC continues transfers without releasing the bus in the following case: * Between the read cycle in the dual-address mode and the write cycle corresponding to the read cycle If no bus master of a higher priority than the DMAC requests the bus and the IBCCS bit in BCR2 is cleared to 0, the DMAC continues transfers without releasing the bus in the following cases: * During 1-block transfers in the block transfer mode * During transfers in the burst mode In other cases, the DMAC transfers the bus at the end of the bus cycle. (4) External Bus Release When the BREQ pin goes low and an external bus release request is issued while the BRLE bit in BCR1 is set to 1 with the corresponding ICR bit set to 1, a bus request is sent to th (5) Refresh When area 2 is specified as the DRAM space or SDRAM space with the RFSHE bit in REFCR set to 1, RTCNT starts to count up. When the RTCOR value matches RTCNT, a bus request is sent to the bus arbiter. A refresh cycle is inserted on completion of the external bus cycle. A refresh cycle is not consecutively inserted. Once a refresh cycle is inserted, the bus is passed to another bus master. When the bus is passed, if there is no bus request from other bus masters, NOP cycles are inserted. Rev.1.00 Jun. 07, 2006 Page 313 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) 6.17 Bus Controller Operation in Reset In a reset, this LSI, including the bus controller, enters the reset state immediately, and any executing bus cycle is aborted. 6.18 (1) Usage Notes Setting Registers The BSC registers must be specified before accessing the external address space. In on-chip ROM disabled mode, the BSC registers must be specified before accessing the external address space for other than an instruction fetch access. (2) Mode Settings The burst read-burst write mode of synchronous DRAM is not supported. When setting the mode register of synchronous DRAM, the burst read-single write mode must be selected and the burst length must be 1. (3) External Bus Release Function and All-Module-Clock-Stop Mode In this LSI, if the ACSE bit in MSTPCRA is set to 1 and a SLEEP instruction is executed to enter the sleep state after shutting off the clocks to all peripheral modules (MSTPCRA and MSTPCRB = H'FFFFFFF) or allowing operation of the 8-bit timer module alone (MSTPCRA and MSTPCRB = H'F[C to F]FFFFFF), the all-module-clock-stop mode is entered in which the clock for the bus controller and I/O ports is also stopped. For details, see section 23, Power-Down Modes. In this state, the external bus release function is halted. To use the external bus release function in sleep mode, the ACSE bit in MSTPCR must be cleared to 0. Conversely, if a SLEEP instruction to place the chip in all-module-clock-stop mode is executed in the external bus released state, the transition to all-module-clock-stop mode is deferred and performed until after the bus is recovered. (4) External Bus Release Function and Software Standby Mode In this LSI, internal bus master operation does not stop even while the bus is released, as long as the program is running in on-chip ROM, etc., and no external access occurs. If a SLEEP instruction to place the chip in software standby mode is executed while the external bus is released, the transition to software standby mode is deferred and performed after the bus is recovered. Rev.1.00 Jun. 07, 2006 Page 314 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) Also, since clock oscillation halts in software standby mode, if the BREQ signal goes low in this mode, indicating an external bus release request, the request cannot be answered until the chip has recovered from the software standby mode. Note that the BACK and BREQO pins are both in the high-impedance state in software standby mode. (5) External Bus Release Function and CBR-Refresh or Auto-Refresh Cycle The CBR refresh or auto-refresh cycle cannot be performed while the external bus is released. When a CBR-refresh or an auto-refresh cycle is requested, the BREQO signal can be output by setting the BREQOE bit in BCR1 to 1. (6) BREQO Output Timing When the BREQOE bit is set to 1 and the BREQO signal is output, both the BREQO and BACK signals may go low simultaneously. This will occur if the next external access request occurs while internal bus arbitration is in progress after the chip samples a low level of the BREQ signal. (7) Refresh Settings In single-chip activation mode, the setting of the RFSHE bit in REFCR should be made after setting the EXPE bit in SYSCR to 1. For SYSCR, see section 3, MCU Operating Modes. (8) Refresh Timer Settings The setting of bits RTCK2 to RTCK0 in REFCR should be made after RTCNT and RTCOR have been set. When changing RTCNT and RTCOR, the counter operation should be halted. When changing bits RTCK2 to RTCK0, change them only after disabling external bus release and, if the write data buffer function is in use, disabling the write data buffer function and reading the external space. Rev.1.00 Jun. 07, 2006 Page 315 of 1102 REJ09B0294-0100 Section 6 Bus Controller (BSC) (9) Switching Between Refresh Timer and Interval Timer When changing the RFSHE bit in REFCR from 1 to 0, a refresh cycle may be inserted until the bit change is reflected. After this, when using RTCNT as an interval timer, the compare match flag (CMF) may be set to 1. Therefore, confirm the state before setting the CMIE bit to 1. (10) RAS Down Mode and Software Standby Mode for DRAM Interface When making a transition to software standby mode with the OPE bit in SBYCR set to 0 without using the self-refresh mode, the transition should be made in RAS up mode (RCDM = 0). When RAS down mode (RCDM = 1) is used, execute the SLEEP instruction after setting the RCDM bit to 0. RAS down mode should be set again after recovery from software standby mode. For SBYCR, see section 23, Power-Down Modes. (11) RAS Down Mode and Clock Frequencies Setting for DRAM/SDRAM Write access to SCKCR for setting the clock frequencies should be performed in RAS up mode (RCDM = 0). When RAS down mode (RCDM = 1) is used, set the RCDM bit to 0 before writing to SCKCR. RAS down mode should be set again after clock frequencies are set. For SCKCR, see section 22, Clock Pulse Generator. (12) Cluster Transfer to SDRAM Space Cluster transfer mode is available for the SDRAM with CAS latency of 2. When the SDRAM is used in cluster transfer mode, the SDRAM with CAS latency of 2 should be used. In cluster transfer mode, the write-precharge output delay function by the TRWL bit is not available. The TRWL bit must be cleared to 0. Rev.1.00 Jun. 07, 2006 Page 316 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) Section 7 DMA Controller (DMAC) This LSI includes a 4-channel DMA controller (DMAC). 7.1 Features * Maximum of 4-G byte address space can be accessed * Byte, word, or longword can be set as data transfer unit * Maximum of 4-G bytes (4,294,967,295 bytes) can be set as total transfer size Supports free-running mode in which total transfer size setting is not needed * DMAC activation methods are auto-request, on-chip module interrupt, and external request. Auto request: CPU activates (cycle stealing or burst access can be selected) On-chip module interrupt: Interrupt requests from on-chip peripheral modules can be selected as an activation source External request: Low level or falling edge detection of the DREQ signal can be selected. External request is available for all four channels. In block transfer mode, low level detection is only available. * Dual or single address mode can be selected as address mode Dual address mode: Both source and destination are specified by addresses Single address mode: Either source or destination is specified by the DREQ signal and the other is specified by address * Normal, repeat, or block transfer can be selected as transfer mode Normal transfer mode: Repeat transfer mode: One byte, one word, or one longword data is transferred at a single transfer request One byte, one word, or one longword data is transferred at a single transfer request Repeat size of data is transferred and then a transfer address returns to the transfer start address Up to 65536 transfers (65,536 bytes/words/longwords) can be set as repeat size Block transfer mode: One block data is transferred at a single transfer request Up to 65,536 bytes/words/longwords can be set as block size Rev.1.00 Jun. 07, 2006 Page 317 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) * Extended repeat area function which repeats the addressees within a specified area using the transfer address with the fixed upper bits (ring buffer transfer can be performed, as an example) is available One bit (two bytes) to 27 bits (128 Mbytes) for transfer source and destination can be set as extended repeat areas * Address update can be selected from fixed address, offset addition, and increment or decrement by 1, 2, or 4 Address update by offset addition enables to transfer data at addresses which are not placed continuously * Word or longword data can be transferred to an address which is not aligned with the respective boundary Data is divided according to its address (byte or word) when it is transferred * Two types of interrupts can be requested to the CPU A transfer end interrupt is generated after the number of data specified by the transfer counter is transferred. A transfer escape end interrupt is generated when the remaining total transfer size is less than the transfer data size at a single transfer request, when the repeat size of data transfer is completed, or when the extended repeat area overflows. Rev.1.00 Jun. 07, 2006 Page 318 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) A block diagram of the DMAC is shown in figure 7.1. Internal address bus External pins DREQn DACKn TENDn Interrupt signals requested to the CPU by each channel Internal activation sources ... Controller Address buffer Operation unit Operation unit DOFR_n DSAR_n Internal activation source detector DMDR_n DMRSR_n DACR_n DDAR_n DTCR_n DBSR_n Internal data bus Data buffer Module data bus [Legend] DSAR_n: DDAR_n: DOFR_n: DTCR_n: DBSR_n: DMDR_n: DACR_n: DMRSR_n: DMA source address register DMA destination address register DMA offset register DMA transfer count register DMA block size register DMA mode control register DMA address control register DMA module request select register DREQn: DMA transfer request DACKn: DMA transfer acknowledge TENDn: DMA transfer end n = 0 to 3 Figure 7.1 Block Diagram of DMAC Rev.1.00 Jun. 07, 2006 Page 319 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) 7.2 Input/Output Pins Table 7.1 shows the pin configuration of the DMAC. Table 7.1 Channel 0 Pin Configuration Pin Name DMA transfer request 0 DMA transfer acknowledge 0 DMA transfer end 0 Abbr. DREQ0 DACK0 TEND0 DREQ1 DACK1 TEND1 DREQ2 DACK2 TEND2 DREQ3 DACK3 TEND3 I/O Input Output Output Input Output Output Input Output Output Input Output Output Function Channel 0 external request Channel 0 single address transfer acknowledge Channel 0 transfer end Channel 1 external request Channel 1 single address transfer acknowledge Channel 1 transfer end Channel 2 external request Channel 2 single address transfer acknowledge Channel 2 transfer end Channel 3 external request Channel 3 single address transfer acknowledge Channel 3 transfer end 1 DMA transfer request 1 DMA transfer acknowledge 1 DMA transfer end 1 2 DMA transfer request 2 DMA transfer acknowledge 2 DMA transfer end 2 3 DMA transfer request 3 DMA transfer acknowledge 3 DMA transfer end 3 Rev.1.00 Jun. 07, 2006 Page 320 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) 7.3 Register Descriptions The DMAC has the following registers. Channel 0: * DMA source address register_0 (DSAR_0) * DMA destination address register_0 (DDAR_0) * DMA offset register_0 (DOFR_0) * DMA transfer count register_0 (DTCR_0) * DMA block size register_0 (DBSR_0) * DMA mode control register_0 (DMDR_0) * DMA address control register_0 (DACR_0) * DMA module request select register_0 (DMRSR_0) Channel 1: * DMA source address register_1 (DSAR_1) * DMA destination address register_1 (DDAR_1) * DMA offset register_1 (DOFR_1) * DMA transfer count register_1 (DTCR_1) * DMA block size register_1 (DBSR_1) * DMA mode control register_1 (DMDR_1) * DMA address control register_1 (DACR_1) * DMA module request select register_1 (DMRSR_1) Channel 2: * DMA source address register_2 (DSAR_2) * DMA destination address register_2 (DDAR_2) * DMA offset register_2 (DOFR_2) * DMA transfer count register_2 (DTCR_2) * DMA block size register_2 (DBSR_2) * DMA mode control register_2 (DMDR_2) * DMA address control register_2 (DACR_2) * DMA module request select register_2 (DMRSR_2) Rev.1.00 Jun. 07, 2006 Page 321 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) Channel 3: * DMA source address register_3 (DSAR_3) * DMA destination address register_3 (DDAR_3) * DMA offset register_3 (DOFR_3) * DMA transfer count register_3 (DTCR_3) * DMA block size register_3 (DBSR_3) * DMA mode control register_3 (DMDR_3) * DMA address control register_3 (DACR_3) * DMA module request select register_3 (DMRSR_3) 7.3.1 DMA Source Address Register (DSAR) DSAR is a 32-bit readable/writable register that specifies the transfer source address. DSAR updates the transfer source address every time data is transferred. When DDAR is specified as the destination address (the DIRS bit in DACR is 1) in single address mode, DSAR is ignored. Although DSAR can always be read from by the CPU, it must be read from in longwords and must not be written to while data for the channel is being transferred. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 23 0 R/W 22 0 R/W 21 0 R/W 20 0 R/W 19 0 R/W 18 0 R/W 17 0 R/W 16 31 30 29 28 27 26 25 24 Rev.1.00 Jun. 07, 2006 Page 322 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) 7.3.2 DMA Destination Address Register (DDAR) DDAR is a 32-bit readable/writable register that specifies the transfer destination address. DDAR updates the transfer destination address every time data is transferred. When DSAR is specified as the source address (the DIRS bit in DACR is 0) in single address mode, DDAR is ignored. Although DDAR can always be read from by the CPU, it must be read from in longwords and must not be written to while data for the channel is being transferred. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 23 0 R/W 22 0 R/W 21 0 R/W 20 0 R/W 19 0 R/W 18 0 R/W 17 0 R/W 16 31 30 29 28 27 26 25 24 Rev.1.00 Jun. 07, 2006 Page 323 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) 7.3.3 DMA Offset Register (DOFR) DOFR is a 32-bit readable/writable register that specifies the offset to update the source and destination addresses. Although different values are specified for individual channels, the same values must be specified for the source and destination sides of a single channel. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 23 0 R/W 22 0 R/W 21 0 R/W 20 0 R/W 19 0 R/W 18 0 R/W 17 0 R/W 16 31 30 29 28 27 26 25 24 Rev.1.00 Jun. 07, 2006 Page 324 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) 7.3.4 DMA Transfer Count Register (DTCR) DTCR is a 32-bit readable/writable register that specifies the size of data to be transferred (total transfer size). To transfer 1-byte data in total, set H'00000001 in DTCR. When H'00000000 is set in this register, it means that the total transfer size is not specified and data is transferred with the transfer counter stopped (free running mode). When H'FFFFFFFF is set, the total transfer size is 4 Gbytes (4,294,967,295), which is the maximum size. While data is being transferred, this register indicates the remaining transfer size. The value corresponding to its data access size is subtracted every time data is transferred (byte: -1, word: -2, and longword: -4). Although DTCR can always be read from by the CPU, it must be read from in longwords and must not be written to while data for the channel is being transferred. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 23 0 R/W 22 0 R/W 21 0 R/W 20 0 R/W 19 0 R/W 18 0 R/W 17 0 R/W 16 31 30 29 28 27 26 25 24 Rev.1.00 Jun. 07, 2006 Page 325 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) 7.3.5 DMA Block Size Register (DBSR) DBSR specifies the repeat size or block size. DBSR is enabled in repeat transfer mode and block transfer mode and is disabled in normal transfer mode. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 31 BKSZH31 0 R/W 23 BKSZH23 0 R/W 15 BKSZ15 0 R/W 7 BKSZ7 0 R/W 30 BKSZH30 0 R/W 22 BKSZH22 0 R/W 14 BKSZ14 0 R/W 6 BKSZ6 0 R/W 29 BKSZH29 0 R/W 21 BKSZH21 0 R/W 13 BKSZ13 0 R/W 5 BKSZ5 0 R/W 28 BKSZH28 0 R/W 20 BKSZH20 0 R/W 12 BKSZ12 0 R/W 4 BKSZ4 0 R/W 27 BKSZH27 0 R/W 19 BKSZH19 0 R/W 11 BKSZ11 0 R/W 3 BKSZ3 0 R/W 26 BKSZH26 0 R/W 18 BKSZH18 0 R/W 10 BKSZ10 0 R/W 2 BKSZ2 0 R/W 25 BKSZH25 0 R/W 17 BKSZH17 0 R/W 9 BKSZ9 0 R/W 1 BKSZ1 0 R/W 24 BKSZH24 0 R/W 16 BKSZH16 0 R/W 8 BKSZ8 0 R/W 0 BKSZ0 0 R/W Bit Bit Name Initial Value R/W Description Specify the repeat size or block size. When H'0001 is set, the repeat or block size is one byte, one word, or one longword. When H'0000 is set, it means the maximum value (refer to table 7.1). While the DMA is in operation, the setting is fixed. Indicate the remaining repeat or block size while the DMA is in operation. The value is decremented by 1 every time data is transferred. When the remaining size becomes 0, the value of the BKSZH bits is loaded. Set the same value as the BKSZH bits. 31 to 16 BKSZH31 to Undefined R/W BKSZH16 15 to 0 BKSZ15 to BKSZ0 Undefined R/W Rev.1.00 Jun. 07, 2006 Page 326 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) Table 7.2 Mode Data Access Size, Valid Bits, and Settable Size Data Access Size BKSZH Valid Bits BKSZ Valid Bits 31 to 16 15 to 0 Settable Size (Byte) 1 to 65,536 2 to 131,072 4 to 262,144 Byte Repeat transfer and block transfer Word Longword 7.3.6 DMA Mode Control Register (DMDR) DMDR controls the DMAC operation. * DMDR_0 Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Note: * 31 DTE 0 R/W 23 ACT 0 R 15 DTSZ1 0 R/W 7 DTF1 0 R/W 30 DACKE 0 R/W 22 0 R 14 DTSZ0 0 R/W 6 DTF0 0 R/W 29 TENDE 0 R/W 21 0 R 13 MDS1 0 R/W 5 DTA 0 R/W 28 0 R/W 20 0 R 12 MDS0 0 R/W 4 0 R 27 DREQS 0 R/W 19 ERRF 0 R/(W)* 11 TSEIE 0 R/W 3 0 R 26 NRD 0 R/W 18 0 R 10 0 R 2 DMAP2 0 R/W 25 0 R 17 ESIF 0 R/(W)* 9 ESIE 0 R/W 1 DMAP1 0 R/W 24 0 R 16 DTIF 0 R/(W)* 8 DTIE 0 R/W 0 DMAP0 0 R/W Only 0 can be written to this bit after having been read as 1, to clear the flag. Rev.1.00 Jun. 07, 2006 Page 327 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) * DMDR_1 to DMDR_3 Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Note: * 31 DTE 0 R/W 23 ACT 0 R 15 DTSZ1 0 R/W 7 DTF1 0 R/W 30 DACKE 0 R/W 22 0 R 14 DTSZ0 0 R/W 6 DTF0 0 R/W 29 TENDE 0 R/W 21 0 R 13 MDS1 0 R/W 5 DTA 0 R/W 28 0 R/W 20 0 R 12 MDS0 0 R/W 4 0 R 27 DREQS 0 R/W 19 0 R 11 TSEIE 0 R/W 3 0 R 26 NRD 0 R/W 18 0 R 10 0 R 2 DMAP2 0 R/W 25 0 R 17 ESIF 0 R/(W)* 9 ESIE 0 R/W 1 DMAP1 0 R/W 24 0 R 16 DTIF 0 R/(W)* 8 DTIE 0 R/W 0 DMAP0 0 R/W Only 0 can be written to this bit after having been read as 1, to clear the flag. Rev.1.00 Jun. 07, 2006 Page 328 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) Bit 31 Bit Name DTE Initial Value 0 R/W R/W Description Data Transfer Enable Enables/disables a data transfer for the corresponding channel. When this bit is set to 1, it indicates that the DMAC is in operation. Setting this bit to 1 starts a transfer when the autorequest is selected. When the on-chip module interrupt or external request is selected, a transfer request after setting this bit to 1 starts the transfer. While data is being transferred, clearing this bit to 0 stops the transfer. In block transfer mode, if writing 0 to this bit while data is being transferred, this bit is cleared to 0 after the current 1-block size data transfer. If an event which stops (sustains) a transfer occurs externally, this bit is automatically cleared to 0 to stop the transfer. Operating modes and transfer methods must not be changed while this bit is set to 1. 0: Disables a data transfer 1: Enables a data transfer (DMA is in operation) [Clearing conditions] * * * * * When the specified total transfer size of transfers is completed When a transfer is stopped by an overflow interrupt by a repeat size end When a transfer is stopped by an overflow interrupt by an extended repeat size end When a transfer is stopped by a transfer size error interrupt When clearing this bit to 0 to stop a transfer In block transfer mode, this bit changes after the current block transfer. * * When an address error or an NMI interrupt is requested In the reset state or hardware standby mode Rev.1.00 Jun. 07, 2006 Page 329 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) Bit 30 Bit Name DACKE Initial Value 0 R/W R/W Description DACK Signal Output Enable Enables/disables the DACK signal output in single address mode. This bit is ignored in dual address mode. 0: Enables DACK signal output 1: Disables DACK signal output 29 TENDE 0 R/W TEND Signal Output Enable Enables/disables the TEND signal output. 0: Enables TEND signal output 1: Disables TEND signal output 28 27 DREQS 0 0 R/W R/W Reserved Initial value should not be changed. DREQ Select Selects whether a low level or the falling edge of the DREQ signal used in external request mode is detected. When a block transfer is performed in external request mode, clear this bit to 0. 0: Low level detection 1: Falling edge detection (the first transfer after a transfer enabled is detected on a low level) 26 NRD 0 R/W Next Request Delay Selects the accepting timing of the next transfer request. 0: Starts accepting the next transfer request after completion of the current transfer 1: Starts accepting the next transfer request one cycle after completion of the current transfer 25, 24 All 0 R Reserved These bits are always read as 0 and cannot be modified. 23 ACT 0 R Active State Indicates the operating state for the channel. 0: Waiting for a transfer request or a transfer disabled state by clearing the DTE bit to 0 1: Active state 22 to 20 All 0 R Reserved These bits are always read as 0 and cannot be modified. Rev.1.00 Jun. 07, 2006 Page 330 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) Bit 19 Bit Name ERRF Initial Value 0 R/W Description R/(W)* System Error Flag Indicates that an address error or an NMI interrupt has been generated. This bit is available only in DMDR_0. Setting this bit to 1 prohibits writing to the DTE bit for all the channels. This bit is reserved in DMDR_1 to DMDR_3. It is always read as 0 and cannot be modified. 0: An address error or an NMI interrupt has not been generated 1: An address error or an NMI interrupt has been generated [Clearing condition] * * When clearing to 0 after reading ERRF = 1 When an address error or an NMI interrupt has been generated [Setting condition] However, when an address error or an NMI interrupt has been generated in DMAC module stop mode, this bit is not set to 1. 18 17 ESIF 0 0 R Reserved This bit is always read as 0 and cannot be modified. R/(W)* Transfer Escape Interrupt Flag Indicates that a transfer escape end interrupt has been requested. A transfer escape end means that a transfer is terminated before the transfer counter reaches 0. 0: A transfer escape end interrupt has not been requested 1: A transfer escape end interrupt has been requested [Clearing conditions] * * * * * When setting the DTE bit to 1 When clearing to 0 before reading ESIF = 1 When a transfer size error interrupt is requested When a repeat size end interrupt is requested When a transfer end interrupt by an extended repeat area overflow is requested [Setting conditions] Rev.1.00 Jun. 07, 2006 Page 331 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) Bit 16 Bit Name DTIF Initial Value 0 R/W Description R/(W)* Data Transfer Interrupt Flag Indicates that a transfer end interrupt by the transfer counter has been requested. 0: A transfer end interrupt by the transfer counter has not been requested 1: A transfer end interrupt by the transfer counter has been requested [Clearing conditions] * * * When setting the DTE bit to 1 When clearing to 0 after reading DTIF = 1 When DTCR reaches 0 and the transfer is completed [Setting condition] 15 14 DTSZ1 DTSZ0 0 0 R/W R/W Data Access Size 1 and 0 Select the data access size for a transfer. 00: Byte size (eight bits) 01: Word size (16 bits) 10: Longword size (32 bits) 11: Setting prohibited 13 12 MDS1 MDS0 0 0 R/W R/W Transfer Mode Select 1 and 0 Select the transfer mode. 00: Normal transfer mode 01: Block transfer mode 10: Repeat transfer mode 11: Setting prohibited Rev.1.00 Jun. 07, 2006 Page 332 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) Bit 11 Bit Name TSEIE Initial Value 0 R/W R/W Description Transfer Size Error Interrupt Enable Enables/disables a transfer size error interrupt. When the next transfer is requested while this bit is set to 1 and the contents of the transfer counter is less than the size of data to be transferred at a single transfer request, the DTE bit is cleared to 0. At this time, the ESIF bit is set to 1 to indicate that a transfer size error interrupt has been requested. The sources of a transfer size error are as follows: * * In normal or repeat transfer mode, the total transfer size set in DTCR is less than the data access size In block transfer mode, the total transfer size set in DTCR is less than the block size 0: Disables a transfer size error interrupt request 1: Enables a transfer size error interrupt request 10 9 ESIE 0 0 R R/W Reserved This bit is always read as 0 and cannot be modified. Transfer Escape Interrupt Enable Enables/disables a transfer escape end interrupt request. When the ESIF bit is set to 1 with this bit set to 1, a transfer escape end interrupt is requested to the CPU or DTC. The transfer end interrupt request is cleared by clearing this bit or the ESIF bit to 0. 0: Disables a transfer escape end interrupt 1: Enables a transfer escape end interrupt 8 DTIE 0 R/W Data Transfer End Interrupt Enable Enables/disables a transfer end interrupt request by the transfer counter. When the DTIF bit is set to 1 with this bit set to 1, a transfer end interrupt is requested to the CPU or DTC. The transfer end interrupt request is cleared by clearing this bit or the DTIF bit to 0. 0: Disables a transfer end interrupt 1: Enables a transfer end interrupt Rev.1.00 Jun. 07, 2006 Page 333 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) Bit 7 6 Bit Name DTF1 DTF0 Initial Value 0 0 R/W R/W R/W Description Data Transfer Factor 1 and 0 Select a DMAC activation source. When the on-chip peripheral module setting is selected, the interrupt source should be selected by DMRSR. When the external request setting is selected, the sampling method should be selected by the DREQS bit. 00: Auto request (cycle stealing) 01: Auto request (burst access) 10: On-chip module interrupt 11: External request 5 DTA 0 R/W Data Transfer Acknowledge This bit is valid in DMA transfer by the on-chip module interrupt source. This bit enables or disables to clear the source flag selected by DMRSR. 0: To clear the source in DMA transfer is disabled. Since the on-chip module interrupt source is not cleared in DMA transfer, it should be cleared by the CPU or DTC transfer. 1: To clear the source in DMA transfer is enabled. Since the on-chip module interrupt source is cleared in DMA transfer, it does not require an interrupt by the CPU or DTC transfer. 4, 3 All 0 R Reserved These bits are always read as 0 and cannot be modified. Rev.1.00 Jun. 07, 2006 Page 334 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) Bit 2 1 0 Bit Name DMAP2 DMAP1 DMAP0 Initial Value 0 0 0 R/W R/W R/W R/W Description DMA Priority Level 2 to 0 Select the priority level of the DMAC when using the CPU priority control function over DTC and DMAC. When the CPU has priority over the DMAC, the DMAC masks a transfer request and waits for the timing when the CPU priority becomes lower than the DMAC priority. The priority levels can be set to the individual channels. This bit is valid when the CPUPCE bit in CPUPCR is set to 1. 000: Priority level 0 (low) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (high) Note: * Only 0 can be written to, to clear the flag. Rev.1.00 Jun. 07, 2006 Page 335 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) 7.3.7 DMA Address Control Register (DACR) DACR specifies the operating mode and transfer method. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 31 AMS 0 R/W 23 0 R 15 SARIE 0 R/W 7 DARIE 0 R/W 30 DIRS 0 R/W 22 0 R 14 0 R 6 0 R 29 0 R 21 SAT1 0 R/W 13 0 R 5 0 R 28 0 R 20 SAT0 0 R/W 12 SARA4 0 R/W 4 DARA4 0 R/W 27 0 R 19 0 R 11 SARA3 0 R/W 3 DARA3 0 R/W 26 RPTIE 0 R/W 18 0 R 10 SARA2 0 R/W 2 DARA2 0 R/W 25 ARS1 0 R/W 17 DAT1 0 R/W 9 SARA1 0 R/W 1 DARA1 0 R/W 24 ARS0 0 R/W 16 DAT0 0 R/W 8 SARA0 0 R/W 0 DARA0 0 R/W Bit 31 Bit Name AMS Initial Value 0 R/W R/W Description Address Mode Select Selects address mode from single or dual address mode. In single address mode, the DACK pin is enabled according to the DACKE bit. 0: Dual address mode 1: Single address mode 30 DIRS 0 R/W Single Address Direction Select Specifies the data transfer direction in single address mode. This bit s ignored in dual address mode. 0: Specifies DSAR as source address 1: Specifies DDAR as destination address 29 to 27 0 R/W Reserved These bits are always read as 0 and cannot be modified. Rev.1.00 Jun. 07, 2006 Page 336 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) Bit 26 Bit Name RPTIE Initial Value 0 R/W R/W Description Repeat Size End Interrupt Enable Enables/disables a repeat size end interrupt request. In repeat transfer mode, when the next transfer is requested after completion of a 1-repeat-size data transfer while this bit is set to 1, the DTE bit in DMDR is cleared to 0. At this time, the ESIF bit in DMDR is set to 1 to indicate that a repeat size end interrupt is requested. Even when the repeat area is not specified (ARS1 = 1 and ARS0 = 0), a repeat size end interrupt after a 1-block data transfer can be requested. In addition, in block transfer mode, when the next transfer is requested after 1-block data transfer while this bit is set to 1, the DTE bit in DMDR is cleared to 0. At this time, the ESIF bit in DMDR is set to 1 to indicate that a repeat size end interrupt is requested. 0: Disables a repeat size end interrupt 1: Enables a repeat size end interrupt Area Select 1 and 0 Specify the block area or repeat area in block or repeat transfer mode. 00: Specify the block area or repeat area on the source address 01: Specify the block area or repeat area on the destination address 10: Do not specify the block area or repeat area 11: Setting prohibited Reserved These bits are always read as 0 and cannot be modified. Source Address Update Mode 1 and 0 Select the update method of the source address (DSAR). When DSAR is not specified as the transfer source in single address mode, this bit is ignored. 00: Source address is fixed 01: Source address is updated by adding the offset 10: Source address is updated by adding 1, 2, or 4 according to the data access size 11: Source address is updated by subtracting 1, 2, or 4 according to the data access size 25 24 ARS1 ARS0 0 0 R/W R/W 23, 22 All 0 R 21 20 SAT1 SAT0 0 0 R/W R/W Rev.1.00 Jun. 07, 2006 Page 337 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) Bit 19, 18 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0 and cannot be modified. 17 16 DAT1 DAT0 0 0 R/W R/W Destination Address Update Mode 1 and 0 Select the update method of the destination address (DDAR). When DDAR is not specified as the transfer destination in single address mode, this bit is ignored. 00: Destination address is fixed 01: Destination address is updated by adding the offset 10: Destination address is updated by adding 1, 2, or 4 according to the data access size 11: Destination address is updated by subtracting 1, 2, or 4 according to the data access size 15 SARIE 0 R/W Interrupt Enable for Source Address Extended Area Overflow Enables/disables an interrupt request for an extended area overflow on the source address. When an extended repeat area overflow on the source address occurs while this bit is set to 1, the DTE bit in DMDR is cleared to 0. At this time, the ESIF bit in DMDR is set to 1 to indicate an interrupt by an extended repeat area overflow on the source address is requested. When block transfer mode is used with the extended repeat area function, an interrupt is requested after completion of a 1-block size transfer. When setting the DTE bit in DMDR of the channel for which a transfer has been stopped to 1, the transfer is resumed from the state when the transfer is stopped. When the extended repeat area is not specified, this bit is ignored. 0: Disables an interrupt request for an extended area overflow on the source address 1: Enables an interrupt request for an extended area overflow on the source address 14, 13 All 0 R Reserved These bits are always read as 0 and cannot be modified. Rev.1.00 Jun. 07, 2006 Page 338 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) Bit 12 11 10 9 8 Bit Name SARA4 SARA3 SARA2 SARA1 SARA0 Initial Value 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Description Source Address Extended Repeat Area Specify the extended repeat area on the source address (DSAR). With the extended repeat area, the specified lower address bits are updated and the remaining upper address bits are fixed. The extended repeat area size is specified from four bytes to 128 Mbytes in units of byte and a power of 2. When the lower address is overflowed from the extended repeat area by address update, the address becomes the start address and the end address of the area for address addition and subtraction, respectively. When an overflow in the extended repeat area occurs with the SARIE bit set to 1, an interrupt can be requested. Table 7.3 shows the settings and areas of the extended repeat area. 7 DARIE 0 R/W Destination Address Extended Repeat Area Overflow Interrupt Enable Enables/disables an interrupt request for an extended area overflow on the destination address. When an extended repeat area overflow on the destination address occurs while this bit is set to 1, the DTE bit in DMDR is cleared to 0. At this time, the ESIF bit in DMDR is set to 1 to indicate an interrupt by an extended repeat area overflow on the destination address is requested. When block transfer mode is used with the extended repeat area function, an interrupt is requested after completion of a 1-block size transfer. When setting the DTE bit in DMDR of the channel for which the transfer has been stopped to 1, the transfer is resumed from the state when the transfer is stopped. When the extended repeat area is not specified, this bit is ignored. 0: Disables an interrupt request for an extended area overflow on the destination address 1: Enables an interrupt request for an extended area overflow on the destination address 6, 5 All 0 R Reserved These bits are always read as 0 and cannot be modified. Rev.1.00 Jun. 07, 2006 Page 339 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) Bit 4 3 2 1 0 Bit Name DARA4 DARA3 DARA2 DARA1 DARA0 Initial Value 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Description Destination Address Extended Repeat Area Specify the extended repeat area on the destination address (DDAR). With the extended repeat area, the specified lower address bits are updated and the remaining upper address bits are fixed. The extended repeat area size is specified from four bytes to 128 Mbytes in units of byte and a power of 2. When the lower address is overflowed from the extended repeat area by address update, the address becomes the start address and the end address of the area for address addition and subtraction, respectively. When an overflow in the extended repeat area occurs with the DARIE bit set to 1, an interrupt can be requested. Table 7.3 shows the settings and areas of the extended repeat area. Rev.1.00 Jun. 07, 2006 Page 340 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) Table 7.3 Settings and Areas of Extended Repeat Area SARA4 to SARA0 or DARA4 to DARA0 Extended Repeat Area 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 111xx [Legend] x: Don't care Not specified 2 bytes specified as extended repeat area by the lower 1 bit of the address 4 bytes specified as extended repeat area by the lower 2 bits of the address 8 bytes specified as extended repeat area by the lower 3 bits of the address 16 bytes specified as extended repeat area by the lower 4 bits of the address 32 bytes specified as extended repeat area by the lower 5 bits of the address 64 bytes specified as extended repeat area by the lower 6 bits of the address 128 bytes specified as extended repeat area by the lower 7 bits of the address 256 bytes specified as extended repeat area by the lower 8 bits of the address 512 bytes specified as extended repeat area by the lower 9 bits of the address 1 kbyte specified as extended repeat area by the lower 10 bits of the address 2 kbytes specified as extended repeat area by the lower 11 bits of the address 4 kbytes specified as extended repeat area by the lower 12 bits of the address 8 kbytes specified as extended repeat area by the lower 13 bits of the address 16 kbytes specified as extended repeat area by the lower 14 bits of the address 32 kbytes specified as extended repeat area by the lower 15 bits of the address 64 kbytes specified as extended repeat area by the lower 16 bits of the address 128 kbytes specified as extended repeat area by the lower 17 bits of the address 256 kbytes specified as extended repeat area by the lower 18 bits of the address 512 kbytes specified as extended repeat area by the lower 19 bits of the address 1 Mbyte specified as extended repeat area by the lower 20 bits of the address 2 Mbytes specified as extended repeat area by the lower 21 bits of the address 4 Mbytes specified as extended repeat area by the lower 22 bits of the address 8 Mbytes specified as extended repeat area by the lower 23 bits of the address 16 Mbytes specified as extended repeat area by the lower 24 bits of the address 32 Mbytes specified as extended repeat area by the lower 25 bits of the address 64 Mbytes specified as extended repeat area by the lower 26 bits of the address 128 Mbytes specified as extended repeat area by the lower 27 bits of the address Setting prohibited Rev.1.00 Jun. 07, 2006 Page 341 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) 7.3.8 DMA Module Request Select Register (DMRSR) DMRSR is an 8-bit readable/writable register that specifies the on-chip module interrupt source. The vector number of the interrupt source is specified in eight bits. However, 0 is regarded as no interrupt source. For the vector numbers of the interrupt sources, refer to table 7.5. Bit Bit Name Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 6 5 4 3 2 1 0 7.4 Transfer Modes Table 7.4 shows the DMAC transfer modes. The transfer modes can be specified to the individual channels. Table 7.4 Transfer Modes Address Register Address Mode Transfer mode Dual address * * * Normal transfer Repeat transfer Block transfer Activation Source * Auto request (activated by CPU) On-chip module interrupt External request Common Function * Total transfer size: 1 to 4 Gbytes or not specified Offset addition Extended repeat area function DSAR/ DACK DACK/ DDAR Source DSAR Destination DDAR Repeat or block size * = 1 to 65,536 bytes, 1 to 65,536 words, or * 1 to 65,536 longwords Single address * * * Instead of specifying the source or destination address registers, data is directly transferred from/to the external device using the DACK pin The same settings as above are available other than address register setting (e.g., above transfer modes can be specified) One transfer can be performed in one bus cycle (the types of transfer modes are the same as those of dual address modes) * * Rev.1.00 Jun. 07, 2006 Page 342 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) When the auto request setting is selected as the activation source, the cycle stealing or burst access can be selected. When the total transfer size is not specified (DTCR = H'00000000), the transfer counter is stopped and the transfer is continued without the limitation of the transfer count. 7.5 7.5.1 (1) Operations Address Modes Dual Address Mode In dual address mode, the transfer source address is specified in DSAR and the transfer destination address is specified in DDAR. A transfer at a time is performed in two bus cycles (when the data bus width is less than the data access size or the access address is not aligned with the boundary of the data access size, the number of bus cycles are needed more than two because one bus cycle is divided into multiple bus cycles). In the first bus cycle, data at the transfer source address is read and in the next cycle, the read data is written to the transfer destination address. The read and write cycles are not separated. Other bus cycles (bus cycle by other bus masters, refresh cycle, and external bus release cycle) are not generated between read and write cycles. The TEND signal output is enabled or disabled by the TENDE bit in DMDR. The TEND signal is output in two bus cycles. When an idle cycle is inserted before the bus cycle, the TEND signal is also output in the idle cycle. The DACK signal is not output. Figure 7.2 shows an example of the signal timing in dual address mode and figure 7.3 shows the operation in dual address mode. Rev.1.00 Jun. 07, 2006 Page 343 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) DMA read cycle B Address bus RD WR TEND DSAR DMA write cycle DDAR Figure 7.2 Example of Signal Timing in Dual Address Mode Address TA Transfer Address TB Address BA Address update setting is as follows: Source address increment Fixed destination address Figure 7.3 Operations in Dual Address Mode (2) Single Address Mode In single address mode, data between an external device and an external memory is directly transferred using the DACK pin instead of DSAR or DDAR. A transfer at a time is performed in one bus cycle. In this mode, the data bus width must be the same as the data access size. For details on the data bus width, see section 6, Bus Controller (BSC). The DMAC accesses an external device as the transfer source or destination by outputting the strobe signal (DACK) to the external device with DACK and accesses the other transfer target by outputting the address. Accordingly, the DMA transfer is performed in one bus cycle. Figure 7.4 shows an example of a transfer between an external memory and an external device with the DACK pin. In this example, the external device outputs data on the data bus and the data is written to the external memory in the same bus cycle. Rev.1.00 Jun. 07, 2006 Page 344 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) The transfer direction is decided by the DIRS bit in DACR which specifies an external device with the DACK pin as the transfer source or destination. When DIRS = 0, data is transferred from an external memory (DSAR) to an external device with the DACK pin. When DIRS = 1, data is transferred from an external device with the DACK pin to an external memory (DDAR). The settings of registers which are not used as the transfer source or destination are ignored. The DACK signal output is enabled in single address mode by the DACKE bit in DMDR. The DACK signal is low active. The TEND signal output is enabled or disabled by the TENDE bit in DMDR. The TEND signal is output in one bus cycle. When an idle cycle is inserted before the bus cycle, the TEND signal is also output in the idle cycle. Figure 7.5 shows an example of timing charts in single address mode and figure 7.6 shows an example of operation in single address mode. External address bus LSI External memory External data bus DMAC External device with DACK DACK DREQ Data flow Figure 7.4 Data Flow in Single Address Mode Rev.1.00 Jun. 07, 2006 Page 345 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) Transfer from external memory to external device with DACK DMA cycle B Address bus RD WR DACK Data bus TEND Data output by external memory DSAR Address for external memory space RD signal for external memory space High Transfer from external device with DACK to external memory DMA cycle B Address bus RD WR DACK Data bus TEND Data output by external device with DACK DDAR Address for external memory space High WR signal for external memory space Figure 7.5 Example of Signal Timing in Single Address Mode Address T Transfer DACK Address B Figure 7.6 Operations in Single Address Mode Rev.1.00 Jun. 07, 2006 Page 346 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) 7.5.2 (1) Transfer Modes Normal Transfer Mode In normal transfer mode, one data access size of data is transferred at a single transfer request. Up to 4 Gbytes can be specified as a total transfer size by DTCR. DBSR is ignored in normal transfer mode. The TEND signal is output only in the last DMA transfer. The DACK signal is output every time a transfer request is received and a transfer starts. Figure 7.7 shows an example of the signal timing in normal transfer mode and figure 7.8 shows the operation in normal transfer mode. Auto request transfer in dual address mode: DMA transfer cycle Bus cycle TEND External request transfer in single address mode: DREQ Bus cycle DACK DMA DMA Read Write Last DMA transfer cycle Read Write Figure 7.7 Example of Signal Timing in Normal Transfer Mode Rev.1.00 Jun. 07, 2006 Page 347 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) Address TA Transfer Address TB Total transfer size (DTCR) Address BA Address BB Figure 7.8 Operations in Normal Transfer Mode (2) Repeat Transfer Mode In repeat transfer mode, one data access size of data is transferred at a single transfer request. Up to 4 Gbytes can be specified as a total transfer size by DTCR. The repeat size can be specified in DBSR up to 65536 x data access size. The repeat area can be specified for the source or destination address side by bits ARS1 and ARS0 in DACR. The address specified as the repeat area returns to the transfer start address when the repeat size of transfers is completed. This operation is repeated until the total transfer size specified in DTCR is completed. When H'00000000 is specified in DTCR, it is regarded as the free running mode and repeat transfer is continued until the DTE bit in DMDR is cleared to 0. In addition, a DMA transfer can be stopped and a repeat size end interrupt can be requested to the CPU or DTC when the repeat size of transfers is completed. When the next transfer is requested after completion of a 1-repeat size data transfer while the RPTIE bit is set to 1, the DTE bit in DMDR is cleared to 0 and the ESIF bit in DMDR is set to 1 to complete the transfer. At this time, an interrupt is requested to the CPU or DTC when the ESIE bit in DMDR is set to 1. The timings of the TEND and DACK signals are the same as in normal transfer mode. Figure 7.9 shows the operation in repeat transfer mode while dual address mode is set. When the repeat area is specified as neither source nor destination address side, the operation is the same as the normal transfer mode operation shown in figure 7.8. In this case, a repeat size end interrupt can also be requested to the CPU when the repeat size of transfers is completed. Rev.1.00 Jun. 07, 2006 Page 348 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) Address TA Transfer Address TB Repeat size = BKSZH x data access size Address BA Total transfer size (DTCR) Operation when the repeat area is specified to the source side Address BB Figure 7.9 Operations in Repeat Transfer Mode (3) Block Transfer Mode In block transfer mode, one block size of data is transferred at a single transfer request. Up to 4 Gbytes can be specified as total transfer size by DTCR. The block size can be specified in DBSR up to 65536 x data access size. While one block of data is being transferred, transfer requests from other channels are suspended. When the transfer is completed, the bus is released to the other bus master. The block area can be specified for the source or destination address side by bits ARS1 and ARS0 in DACR. The address specified as the block area returns to the transfer start address when the block size of data is completed. When the block area is specified as neither source nor destination address side, the operation continues without returning the address to the transfer start address. A repeat size end interrupt can be requested. The TEND signal is output every time 1-block data is transferred in the last DMA transfer cycle. When the external request is selected as an activation source, the low level detection of the DREQ signal (DREQS = 0) should be selected. When an interrupt request by an extended repeat area overflow is used in block transfer mode, settings should be selected carefully. For details, see section 7.5.5, Extended Repeat Area Function. Rev.1.00 Jun. 07, 2006 Page 349 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) Figure 7.10 shows an example of the DMA transfer timing in block transfer mode. The transfer conditions are as follows: * Address mode: single address mode * Data access size: byte * 1-block size: three bytes The block transfer mode operations in single address mode and in dual address mode are shown in figures 7.11 and 7.12, respectively. DREQ Transfer cycles for one block Bus cycle CPU CPU DMAC DMAC DMAC CPU No CPU cycle generated TEND Figure 7.10 Operations in Block Transfer Mode Address T Block BKSZH x data access size Address B Transfer DACK Figure 7.11 Operation in Single Address Mode in Block Transfer Mode (Block Area Specified) Rev.1.00 Jun. 07, 2006 Page 350 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) Address TA First block BKSZH x data access size Address TB Transfer First block Second block Second block Total transfer size (DTCR) Nth block Nth block Address BB Address BA Figure 7.12 Operation in Dual Address Mode in Block Transfer Mode (Block Area Not Specified) Rev.1.00 Jun. 07, 2006 Page 351 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) 7.5.3 Activation Sources The DMAC is activated by an auto request, an on-chip module interrupt, and an external request. The activation source is specified by bits DTF1 and DTF0 in DMDR. (1) Activation by Auto Request The auto request activation is used when a transfer request from an external device or an on-chip peripheral module is not generated such as a transfer between memory and memory or between memory and an on-chip peripheral module which does not request a transfer. A transfer request is automatically generated inside the DMAC. In auto request activation, setting the DTE bit in DMDR starts a transfer. The bus mode can be selected from cycle stealing and burst modes. (2) Activation by On-Chip Module Interrupt An interrupt request from an on-chip peripheral module (on-chip peripheral module interrupt) is used as a transfer request. When a DMA transfer is enabled (DTE = 1), the DMA transfer is started by an on-chip module interrupt. The activation source of the on-chip module interrupt is selected by the DMA module request select register (DMRSR). The activation sources are specified to the individual channels. Table 7.5 is a list of on-chip module interrupts for the DMAC. The interrupt request selected as the activation source can generate an interrupt request simultaneously to the CPU or DTC. For details, refer to section 5, Interrupt Controller. The DMAC receives interrupt requests by on-chip peripheral modules independent of the interrupt controller. Therefore, the DMAC is not affected by priority given in the interrupt controller. When the DMAC is activated while DTA = 1, the interrupt request flag is automatically cleared by a DMA transfer. If multiple channels use a single transfer request as an activation source, when the channel having priority is activated, the interrupt request flag is cleared. In this case, other channels may not be activated because the transfer request is not held in the DMAC. When the DMAC is activated while DTA = 0, the interrupt request flag is not cleared by the DMAC and should be cleared by the CPU or DTC transfer. When an activation source is selected while DTE = 0, the activation source does not request a transfer to the DMAC. It requests an interrupt to the CPU or DTC. In addition, make sure that an interrupt request flag as an on-chip module interrupt source is cleared to 0 before writing 1 to the DTE bit. Rev.1.00 Jun. 07, 2006 Page 352 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) Table 7.5 List of On-chip module interrupts to DMAC On-Chip Module A/D TPU_0 TPU_1 TPU_2 TPU_3 TPU_4 TPU_5 SCI_0 SCI_0 SCI_1 SCI_1 SCI_2 SCI_2 SCI_4 SCI_4 SCI_5 SCI_5 SCI_6 SCI_6 USB USB DMRSR (Vector Number) 86 88 93 97 101 106 110 145 146 149 150 153 154 161 162 220 221 224 225 232 233 On-Chip Module Interrupt Source ADI (conversion end interrupt for A/D converter) TGI0A (TGI0A input capture/compare match) TGI1A (TGI1A input capture/compare match) TGI2A (TGI2A input capture/compare match) TGI3A (TGI3A input capture/compare match) TGI4A (TGI4A input capture/compare match) TGI5A (TGI5A input capture/compare match) RXI0 (receive data full interrupt for SCI channel 0) TXI0 (transmit data empty interrupt for SCI channel 0) RXI1 (receive data full interrupt for SCI channel 1) TXI1 (transmit data empty interrupt for SCI channel 1) RXI2 (receive data full interrupt for SCI channel 2) TXI2 (transmit data empty interrupt for SCI channel 2) RXI4 (receive data full interrupt for SCI channel 4) TXI4 (transmit data empty interrupt for SCI channel 4) RXI5 (receive data full interrupt for SCI channel 5) TXI5 (transmit data empty interrupt for SCI channel 5) RXI6 (receive data full interrupt for SCI channel 6) TXI6 (transmit data empty interrupt for SCI channel 6) USBINTN0 (EP1FIFO full interrupt) USBINTN1 (EP2FIFO empty interrupt) Rev.1.00 Jun. 07, 2006 Page 353 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) (3) Activation by External Request A transfer is started by a transfer request signal (DREQ) from an external device. When a DMA transfer is enabled (DTE = 1), the DMA transfer is started by the DREQ assertion. When a DMA transfer between on-chip peripheral modules is performed, select an activation source from the auto request and on-chip module interrupt (the external request cannot be used). A transfer request signal is input to the DREQ pin. The DREQ signal is detected on the falling edge or low level. Whether the falling edge or low level detection is used is selected by the DREQS bit in DMDR. To perform a block transfer, select the low level detection (DREQS = 0). When an external request is selected as an activation source, clear the DDR bit to 0 and set the ICR bit to 1 for the corresponding pin. For details, see section 9, I/O Ports. 7.5.4 Bus Access Modes There are two types of bus access modes: cycle stealing and burst. When an activation source is the auto request, the cycle stealing or burst mode is selected by bit DTF0 in DMDR. When an activation source is the on-chip module interrupt or external request, the cycle stealing mode is selected. (1) Cycle Stealing Mode In cycle stealing mode, the DMAC releases the bus every time one unit of transfers (byte, word, longword, or 1-block size) is completed. After that, when a transfer is requested, the DMAC obtains the bus to transfer 1-unit data and then releases the bus on completion of the transfer. This operation is continued until the transfer end condition is satisfied. When a transfer is requested to another channel during a DMA transfer, the DMAC releases the bus and then transfers data for the requested channel. For details on operations when a transfer is requested to multiple channels, see section 7.5.8, Priority of Channels. Rev.1.00 Jun. 07, 2006 Page 354 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) Figure 7.13 shows an example of timing in cycle stealing mode. The transfer conditions are as follows: * Address mode: Single address mode * Sampling method of the DREQ signal: Low level detection DREQ Bus cycle CPU CPU DMAC CPU DMAC CPU Bus released temporarily for the CPU Figure 7.13 Example of Timing in Cycle Stealing Mode (2) Burst Access Mode In burst mode, once it takes the bus, the DMAC continues a transfer without releasing the bus until the transfer end condition is satisfied. Even if a transfer is requested from another channel having priority, the transfer is not stopped once it is started. The DMAC releases the bus in the next cycle after the transfer for the channel in burst mode is completed. This is similarly to operation in cycle stealing mode. However, setting the IBCCS bit in IBCR of the bus controller makes the DMAC release the bus to pass the bus to another bus master. In block transfer mode, the burst mode setting is ignored (operation is the same as that in burst mode during one block of transfers). The DMAC is always operated in cycle stealing mode. Clearing the DTE bit in DMDR stops a DMA transfer. A transfer requested before the DTE bit is cleared to 0 by the DMAC is executed. When an interrupt by a transfer size error, a repeat size end, or an extended repeat area overflow occurs, the DTE bit is cleared to 0 and the transfer ends. Figure 7.14 shows an example of timing in burst mode. Bus cycle CPU CPU DMAC DMAC DMAC CPU CPU No CPU cycle generated Figure 7.14 Example of Timing in Burst Mode Rev.1.00 Jun. 07, 2006 Page 355 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) 7.5.5 Extended Repeat Area Function The source and destination address sides can be specified as the extended repeat area. The contents of the address register repeat addresses within the area specified as the extended repeat area. For example, to use a ring buffer as the transfer target, the contents of the address register should return to the start address of the buffer every time the contents reach the end address of the buffer (overflow on the ring buffer address). This operation can automatically be performed using the extended repeat area function of the DMAC. The extended repeat areas can be specified independently to the source address register (DSAR) and destination address register (DDAR). The extended repeat area on the source address is specified by bits SARA4 to SARA0 in DACR. The extended repeat area on the destination address is specified by bits DARA4 to DARA0 in DACR. The extended repeat area sizes for each side can be specified independently. A DMA transfer is stopped and an interrupt by an extended repeat area overflow can be requested to the CPU when the contents of the address register reach the end address of the extended repeat area. When an overflow on the extended repeat area set in DSAR occurs while the SARIE bit in DACR is set to 1, the ESIF bit in DMDR is set to 1 and the DTE bit in DMDR is cleared to 0 to stop the transfer. At this time, if the ESIE bit in DMDR is set to 1, an interrupt by an extended repeat area overflow is requested to the CPU. When the DARIE bit in DACR is set to 1, an overflow on the extended repeat area set in DDAR occurs, meaning that the destination side is a target. During the interrupt handling, setting the DTE bit in DMDR resumes the transfer. Rev.1.00 Jun. 07, 2006 Page 356 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) Figure 7.15 shows an example of the extended repeat area operation. When the area represented by the lower three bits of DSAR (eight bytes) is specified as the extended repeat area (SARA4 to SARA0 = B'00011) External memory Area specified by DSAR H'23FFFE H'23FFFF H'240000 H'240001 H'240002 H'240003 H'240004 H'240005 H'240006 H'240007 H'240008 H'240009 H'240000 H'240001 H'240002 H'240003 H'240004 H'240005 H'240006 H'240007 An interrupt request by extended repeat area overflow can be generated. Repeat Figure 7.15 Example of Extended Repeat Area Operation When an interrupt by an extended repeat area overflow is used in block transfer mode, the following should be taken into consideration. When a transfer is stopped by an interrupt by an extended repeat area overflow, the address register must be set so that the block size is a power of 2 or the block size boundary is aligned with the extended repeat area boundary. When an overflow on the extended repeat area occurs during a transfer of one block, the interrupt by the overflow is suspended and the transfer overruns. ... ... Rev.1.00 Jun. 07, 2006 Page 357 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) Figure 7.16 shows examples when the extended repeat area function is used in block transfer mode. When the are represented by the lower three bits (eight bytes) of DSAR are specified as the extended repeat area (SARA4 to SARA0 = 3) and the block size in block transfer mode is specified to 5 (bits 23 to 16 in DTCR = 5). External memory Area specified 1st block 2nd block by DSAR transfer transfer H'23FFFE H'23FFFF H'240000 H'240001 H'240002 H'240003 H'240004 H'240005 H'240006 H'240007 H'240008 H'240009 H'240000 H'240001 H'240002 H'240003 H'240004 H'240005 H'240006 H'240007 H'240000 H'240001 H'240002 H'240003 H'240004 H'240005 H'240006 H'240007 Block transfer continued H'240000 H'240001 Interrupt request generated Figure 7.16 Example of Extended Repeat Area Function in Block Transfer Mode Rev.1.00 Jun. 07, 2006 Page 358 of 1102 REJ09B0294-0100 ... ... Section 7 DMA Controller (DMAC) 7.5.6 Address Update Function using Offset The source and destination addresses are updated by fixing, increment/decrement by 1, 2, or 4, or offset addition. When the offset addition is selected, the offset specified by the offset register (DOFR) is added to the address every time the DMAC transfers the data access size of data. This function realizes a data transfer where addresses are allocated to separated areas. Figure 7.17 shows the address update method. External memory External memory External memory 0 1, 2, or 4 + offset Address not updated Data access size added to or subtracted from address (addresses are continuous) (b) Increment or decrement by 1, 2, or 4 Offset is added to address (addresses are not continuous) (c) Offset addition (a) Address fixed Figure 7.17 Address Update Method In item (a), Address fixed, the transfer source or destination address is not updated indicating the same address. In item (b), Increment or decrement by 1, 2, or 4, the transfer source or destination address is incremented or decremented by the value according to the data access size at each transfer. Byte, word, or longword can be specified as the data access size. The value of 1 for byte, 2 for word, and 4 for longword is used for updating the address. This operation realizes the data transfer placed in consecutive areas. In item (c), Offset addition, the address update does not depend on the data access size. The offset specified by DOFR is added to the address every time the DMAC transfers data of the data access size. Rev.1.00 Jun. 07, 2006 Page 359 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) The address is calculated by the offset set in DOFR and the contents of DSAR and DDAR. Although the DMAC calculates only addition, an offset subtraction can be realized by setting the negative value in DOFR. In this case, the negative value must be 2's complement. (1) Basic Transfer Using Offset Figure 7.18 shows a basic operation of a transfer using the offset addition. Data 1 Address A1 Transfer Offset Data 1 Data 2 Data 3 Data 4 Data 5 : Address B1 Address B2 = Address B1 + 4 Address B3 = Address B2 + 4 Address B4 = Address B3 + 4 Address B5 = Address B4 + 4 Data 2 Address A2 = Address A1 + Offset : : : Offset Data 3 Address A3 = Address A2 + Offset Offset Transfer source: Offset addition Transfer destination: Increment by 4 (longword) Address A4 = Address A3 + Offset Data 4 Offset Data 5 Address A5 = Address A4 + Offset Figure 7.18 Operation of Offset Addition In figure 7.18, the offset addition is selected as the transfer source address update and increment or decrement by 1, 2, or 4 is selected as the transfer destination address. The address update means that data at the address which is away from the previous transfer source address by the offset is read from. The data read from the address away from the previous address is written to the consecutive area in the destination side. Rev.1.00 Jun. 07, 2006 Page 360 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) (2) XY Conversion Using Offset Figure 7.19 shows the XY conversion using the offset addition in repeat transfer mode. Data 1 Data 5 Data 9 Data 13 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data 10 Data 11 Data 12 Data 13 Data 14 Data 15 Data 16 1st transfer 2nd transfer Transfer 3rd transfer 4th transfer Data 2 Data 6 Data 10 Data 14 Data 3 Data 7 Data 11 Data 15 Data 4 Data 8 Data 12 Data 16 1st transfer Offset Offset Offset Data 1 Data 5 Data 9 Data 13 Data 2 Data 6 Data 10 Data 14 Data 3 Data 7 Data 11 Data 15 Data 4 Data 8 Data 12 Data 16 2nd transfer Transfer source 3rd transfer addresses changed by CPU Data 1 Data 1 Data 5 Data 5 Address initialized Data 9 Data 9 Address initialized Data 13 Data 13 Data 2 Data 2 Data 6 Data 6 Data 10 Data 10 Data 14 Data 14 Data 3 Data 3 Data 7 Data 7 Data 11 Data 11 Data 15 Data 15 Data 4 Data 4 Data 8 Data 8 Interrupt request Data 12 Data 12 Interrupt generated request Data 16 Data 16 generated Transfer Transfer source addresses changed by CPU Interrupt request generated Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data 10 Data 11 Data 12 Data 13 Data 14 Data 15 Data 16 1st transfer 2nd transfer 3rd transfer 4th transfer Figure 7.19 XY Conversion Operation Using Offset Addition in Repeat Transfer Mode In figure 7.19, the source address side is specified to the repeat area by DACR and the offset addition is selected. The offset value is set to 4 x data access size (when the data access size is longword, H'00000010 is set in DOFR, as an example). The repeat size is set to 4 x data access size (when the data access size is longword, the repeat size is set to 4 x 4 = 16 bytes, as an example). The increment or decrement by 1, 2, or 4 is specified as the transfer destination address. A repeat size end interrupt is requested when the repeat size of transfers is completed. Rev.1.00 Jun. 07, 2006 Page 361 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) When a transfer starts, the transfer source address is added to the offset every time data is transferred. The transfer data is written to the destination continuous addresses. When data 4 is transferred meaning that the repeat size of transfers is completed, the transfer source address returns to the transfer start address (address of data 1 on the transfer source) and a repeat size end interrupt is requested. While this interrupt stops the transfer temporarily, the contents of DSAR are written to the address of data 5 by the CPU (when the data access size is longword, write the data 1 address + 4). When the DTE bit in DMDR is set to 1, the transfer is resumed from the state when the transfer is stopped. Accordingly, operations are repeated and the transfer source data is transposed to the destination area (XY conversion). Figure 7.20 shows a flowchart of the XY conversion. Start Set address and transfer count Set repeat transfer mode Enable repeat escape interrupt Set DTE bit to 1 Receives transfer request Transfers data Decrements transfer count and repeat size No Transfer count = 0? No Yes Repeat size = 0? Yes Initializes transfer source address Generates repeat size end interrupt request Set transfer source address + 4 (Longword transfer) End : User operation : DMAC operation Figure 7.20 XY Conversion Flowchart Using Offset Addition in Repeat Transfer Mode Rev.1.00 Jun. 07, 2006 Page 362 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) (3) Offset Subtraction When setting the negative value in DOFR, the offset value must be 2's complement. The 2's complement is obtained by the following formula. 2's complement of offset = 1 + ~offset (~: bit inversion) Example: 2's complement of H'0001FFFF = H'FFFE0000 + H'00000001 = H'FFFE0001 The value of 2's complement can be obtained by the NEG.L instruction. 7.5.7 Register during DMA Transfer The DMAC registers are updated by a DMA transfer. The value to be updated differs according to the other settings and transfer state. The registers to be updated are DSAR, DDAR, DTCR, bits BKSZH and BKSZ in DBSR, and the DTE, ACT, ERRF, ESIF, and DTIF bits in DMDR. (1) DMA Source Address Register When the transfer source address set in DSAR is accessed, the contents of DSAR are output and then are updated to the next address. The increment or decrement can be specified by bits SAT1 and SAT0 in DACR. When SAT1 and SAT0 = B'00, the address is fixed. When SAT1 and SAT0 = B'01, the address is added with the offset. When SAT1 and SAT0 = B'10, the address is incremented. When SAT1 and SAT0 = B'11, the address is decremented. The size of increment or decrement depends on the data access size. The data access size is specified by bits DTSZ1 and DTSZ0 in DMDR. When DTSZ1 and DTSZ0 = B'00, the data access size is byte and the address is incremented or decremented by 1. When DTSZ1 and DTSZ0 = B'01, the data access size is word and the address is incremented or decremented by 2. When DTSZ1 and DTSZ0 = B'10, the data access size is longword and the address is incremented or decremented by 4. Even if the access data size of the source address is word or longword, when the source address is not aligned with the word or longword boundary, the read bus cycle is divided into byte or word cycles. While data of one word or one longword is being read, the size of increment or decrement is changing according to the actual data access size, for example, +1 or +2 for byte or word data. After one word or one longword of data is read, the address when the read cycle is started is incremented or decremented by the value according to bits SAT1 and SAT0. Rev.1.00 Jun. 07, 2006 Page 363 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) In block or repeat transfer mode, when the block or repeat size of data transfers is completed while the block or repeat area is specified to the source address side, the source address returns to the transfer start address and is not affected by the address update. When the extended repeat area is specified to the source address side, operation follows the setting. The upper address bits are fixed and is not affected by the address update. While data is being transferred, DSAR must be accessed in longwords. If the upper word and lower word are read separately, incorrect data may be read from since the contents of DSAR during the transfer may be updated regardless of the access by the CPU. Moreover, DSAR for the channel being transferred must not be written to. (2) DMA Destination Address Register When the transfer destination address set in DDAR is accessed, the contents of DDAR are output and then are updated to the next address. The increment or decrement can be specified by bits DAT1 and DAT0 in DACR. When DAT1 and DAT0 = B'00, the address is fixed. When DAT1 and DAT0 = B'01, the address is added with the offset. When DAT1 and DAT0 = B'10, the address is incremented. When DAT1 and DAT0 = B'11, the address is decremented. The incrementing or decrementing size depends on the data access size. The data access size is specified by bits DTSZ1 and DTSZ0 in DMDR. When DTSZ1 and DTSZ0 = B'00, the data access size is byte and the address is incremented or decremented by 1. When DTSZ1 and DTSZ0 = B'01, the data access size is word and the address is incremented or decremented by 2. When DTSZ1 and DTSZ0 = B'10, the data access size is longword and the address is incremented or decremented by 4. Even if the access data size of the destination address is word or longword, when the destination address is not aligned with the word or longword boundary, the write bus cycle is divided into byte and word cycles. While one word or one longword of data is being written, the incrementing or decrementing size is changing according to the actual data access size, for example, +1 or +2 for byte or word data. After the one word or one longword of data is written, the address when the write cycle is started is incremented or decremented by the value according to bits SAT1 and SAT0. In block or repeat transfer mode, when the block or repeat size of data transfers is completed while the block or repeat area is specified to the destination address side, the destination address returns to the transfer start address and is not affected by the address update. When the extended repeat area is specified to the destination address side, operation follows the setting. The upper address bits are fixed and is not affected by the address update. Rev.1.00 Jun. 07, 2006 Page 364 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) While data is being transferred, DDAR must be accessed in longwords. If the upper word and lower word are read separately, incorrect data may be read from since the contents of DDAR during the transfer may be updated regardless of the access by the CPU. Moreover, DDAR for the channel being transferred must not be written to. (3) DMA Transfer Count Register (DTCR) A DMA transfer decrements the contents of DTCR by the transferred bytes. When byte data is transferred, DTCR is decremented by 1. When word data is transferred, DTCR is decremented by 2. When longword data is transferred, DTCR is decremented by 4. However, when DTCR = 0, the contents of DTCR are not changed since the number of transfers is not counted. While data is being transferred, all the bits of DTCR may be changed. DTCR must be accessed in longwords. If the upper word and lower word are read separately, incorrect data may be read from since the contents of DTCR during the transfer may be updated regardless of the access by the CPU. Moreover, DTCR for the channel being transferred must not be written to. When a conflict occurs between the address update by DMA transfer and write access by the CPU, the CPU has priority. When a conflict occurs between change from 1, 2, or 4 to 0 in DTCR and write access by the CPU (other than 0), the CPU has priority in writing to DTCR. However, the transfer is stopped. (4) DMA Block Size Register (DBSR) DBSR is enabled in block or repeat transfer mode. Bits 31 to 16 in DBSR function as BKSZH and bits 15 to 0 in DBSR function as BKSZ. The BKSZH bits (16 bits) store the block size and repeat size and its value is not changed. The BKSZ bits (16 bits) function as a counter for the block size and repeat size and its value is decremented every transfer by 1. When the BKSZ value is to change from 1 to 0 by a DMA transfer, 0 is not stored but the BKSZH value is loaded into the BKSZ bits. Since the upper 16 bits of DBSR are not updated, DBSR can be accessed in words. DBSR for the channel being transferred must not be written to. Rev.1.00 Jun. 07, 2006 Page 365 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) (5) DTE Bit in DMDR Although the DTE bit in DMDR enables or disables data transfer by the CPU write access, it is automatically cleared to 0 according to the DMA transfer state by the DMAC. The conditions for clearing the DTE bit by the DMAC are as follows: * When the total size of transfers is completed * When a transfer is completed by a transfer size error interrupt * When a transfer is completed by a repeat size end interrupt * When a transfer is completed by an extended repeat area overflow interrupt * When a transfer is stopped by an NMI interrupt * When a transfer is stopped by and address error * Reset state * Hardware standby mode * When a transfer is stopped by writing 0 to the DTE bit Writing to the registers for the channels when the corresponding DTE bit is set to 1 is prohibited (except for the DTE bit). When changing the register settings after writing 0 to the DTE bit, confirm that the DTE bit has been cleared to 0. Figure 7.21 show the procedure for changing the register settings for the channel being transferred. Changing register settings of channel during operation Write 0 to DTE bit [1] [1] Write 0 to the DTE bit in DMDR. [2] Read the DTE bit. [3] Confirm that DTE = 0. DTE = 1 indicates that DMA is transferring. [4] Write the desired values to the registers. Read DTE bit [2] [3] DTE = 0? Yes Change register settings End of changing register settings No [4] Figure 7.21 Procedure for Changing Register Setting For Channel being Transferred Rev.1.00 Jun. 07, 2006 Page 366 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) (6) ACT Bit in DMDR The ACT bit in DMDR indicates whether the DMAC is in the idle or active state. When DTE = 0 or DTE = 1 and the DMAC is waiting for a transfer request, the ACT bit is 0. Otherwise (the DMAC is in the active state), the ACT bit is 1. When individual transfers are stopped by writing 0 and the transfer is not completed, the ACT bit retains 1. In block transfer mode, even if individual transfers are stopped by writing 0 to the DTE bit, the 1block size of transfers is not stopped. The ACT bit retains 1 from writing 0 to the DTE bit to completion of a 1-block size transfer. In burst mode, up to three times of DMA transfer are performed from the cycle in which the DTE bit is written to 0. The ACT bit retains 1 from writing 0 to the DTE bit to completion of DMA transfer. (7) ERRF Bit in DMDR When an address error or an NMI interrupt occur, the DMAC clears the DTE bits for all the channels to stop a transfer. In addition, it sets the ERRF bit in DMDR_0 to 1 to indicate that an address error or an NMI interrupt has occurred regardless of whether or not the DMAC is in operation. (8) ESIF Bit in DMDR When an interrupt by an transfer size error, a repeat size end, or an extended repeat area overflow is requested, the ESIF bit in DMDR is set to 1. When both the ESIF and ESIE bits are set to 1, a transfer escape interrupt is requested to the CPU or DTC. The ESIF bit is set to 1 when the ACT bit in DMDR is cleared to 0 to stop a transfer after the bus cycle of the interrupt source is completed. The ESIF bit is automatically cleared to 0 and a transfer request is cleared if the transfer is resumed by setting the DTE bit to 1 during interrupt handling. For details on interrupts, see section 7.8, Interrupt Sources. Rev.1.00 Jun. 07, 2006 Page 367 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) (9) DTIF Bit in DMDR The DTIF bit in DMDR is set to 1 after the total transfer size of transfers is completed. When both the DTIF and DTIE bits in DMDR are set to 1, a transfer end interrupt by the transfer counter is requested to the CPU or DTC. The DTIF bit is set to 1 when the ACT bit in DMDR is cleared to 0 to stop a transfer after the bus cycle is completed. The DTIF bit is automatically cleared to 0 and a transfer request is cleared if the transfer is resumed by setting the DTE bit to 1 during interrupt handling. For details on interrupts, see section 7.8, Interrupt Sources. 7.5.8 Priority of Channels The channels of the DMAC are given following priority levels: channel 0 > channel 1 > channel 2 > channel3. Table 7.6 shows the priority levels among the DMAC channels. Table 7.6 Channel Channel 0 Channel 1 Channel 2 Channel 3 Low Priority among DMAC Channels Priority High The channel having highest priority other than the channel being transferred is selected when a transfer is requested from other channels. The selected channel starts the transfer after the channel being transferred releases the bus. At this time, when a bus master other than the DMAC requests the bus, the cycle for the bus master is inserted. In a burst transfer or a block transfer, channels are not switched. Rev.1.00 Jun. 07, 2006 Page 368 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) Figure 7.22 shows a transfer example when multiple transfer requests from channels 0 to 2. Channel 0 transfer Channel 1 transfer Channel 2 transfer B Address bus DMAC operation Channel 0 Bus released Channel 1 Bus released Channel 2 Wait Channel 0 Channel 1 Channel 2 Wait Channel 0 Request cleared Channel 1 Request cleared Request Selected retained Request Not Request retained selected retained Selected Request cleared Channel 2 Figure 7.22 Example of Timing for Channel Priority Rev.1.00 Jun. 07, 2006 Page 369 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) 7.5.9 DMA Basic Bus Cycle Figure 7.23 shows an examples of signal timing of a basic bus cycle. In figure 7.23, data is transferred in words from the 16-bit 2-state access space to the 8-bit 3-state access space. When the bus mastership is passed from the DMAC to the CPU, data is read from the source address and it is written to the destination address. The bus is not released between the read and write cycles by other bus requests. DMAC bus cycles follows the bus controller settings. CPU cycle T1 B Source address Address bus T2 T1 DMAC cycle (one word transfer) T2 T3 T1 T2 T3 CPU cycle Destination address RD LHWR LLWR High Figure 7.23 Example of Bus Timing of DMA Transfer Rev.1.00 Jun. 07, 2006 Page 370 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) 7.5.10 (1) Bus Cycles in Dual Address Mode Normal Transfer Mode (Cycle Stealing Mode) In cycle stealing mode, the bus is released every time one transfer size of data (one byte, one word, or one longword) is completed. One bus cycle or more by the CPU or DTC are executed in the bus released cycles. In figure 7.24, the TEND signal output is enabled and data is transferred in words from the external 16-bit 2-state access space to the external 16-bit 2-state access space in normal transfer mode by cycle stealing. DMA read cycle DMA write cycle DMA read cycle DMA write cycle DMA read cycle DMA write cycle B Address bus RD LHWR, LLWR TEND Bus released Bus released Bus released Last transfer cycle Bus released Figure 7.24 Example of Transfer in Normal Transfer Mode by Cycle Stealing In figures 7.25 and 7.26, the TEND signal output is enabled and data is transferred in longwords from the external 16-bit 2-state access space to the 16-bit 2-state access space in normal transfer mode by cycle stealing. In figure 7.25, the transfer source (DSAR) is not aligned with a longword boundary and the transfer destination (DDAR) is aligned with a longword boundary. In figure 7.26, the transfer source (DSAR) is aligned with a longword boundary and the transfer destination (DDAR) is not aligned with a longword boundary. Rev.1.00 Jun. 07, 2006 Page 371 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) DMA byte read cycle DMA word read cycle DMA byte read cycle DMA word write cycle DMA word write cycle DMA byte read cycle DMA word read cycle DMA byte read cycle DMA word write cycle DMA word write cycle B Address bus RD LHWR LLWR TEND 4m + 1 4m + 2 4m + 4 4n 4n +2 4m + 5 4m + 6 4m + 8 4n + 4 4n + 6 Bus released Bus released Last transfer cycle Bus released m and n are integers. Figure 7.25 Example of Transfer in Normal Transfer Mode by Cycle Stealing (Transfer Source DSAR = Odd Address and Source Address Increment) DMA word read cycle DMA word read cycle DMA byte write cycle DMA word write cycle DMA byte write cycle DMA word read cycle DMA word read cycle DMA byte write cycle DMA word write cycle DMA byte write cycle B Address bus RD LHWR LLWR TEND 4m 4m + 2 4n + 5 4n + 6 4n + 8 4m + 4 4m + 6 4n + 1 4n + 2 4n + 4 Bus released Bus released Last transfer cycle Bus released m and n are integers. Figure 7.26 Example of Transfer in Normal Transfer Mode by Cycle Stealing (Transfer Destination DDAR = Odd Address and Destination Address Decrement) Rev.1.00 Jun. 07, 2006 Page 372 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) (2) Normal Transfer Mode (Burst Mode) In burst mode, one byte, one word, or one longword of data continues to be transferred until the transfer end condition is satisfied. When a burst transfer starts, a transfer request from a channel having priority is suspended until the burst transfer is completed. In figure 7.27, the TEND signal output is enabled and data is transferred in words from the external 16-bit 2-state access space to the external 16-bit 2-state access space in normal transfer mode by burst access. DMA read cycle DMA write cycle DMA read cycle DMA write cycle DMA read cycle DMA write cycle B Address bus RD LHWR, LLWR TEND Last transfer cycle Burst transfer Bus released Bus released Figure 7.27 Example of Transfer in Normal Transfer Mode by Burst Access Rev.1.00 Jun. 07, 2006 Page 373 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) (3) Block Transfer Mode In block transfer mode, the bus is released every time a 1-block size of transfers at a single transfer request is completed. In figure 7.28, the TEND signal output is enabled and data is transferred in words from the external 16-bit 2-state access space to the external 16-bit 2-state access space in block transfer mode. DMA read cycle DMA write cycle DMA read cycle DMA write cycle DMA read cycle DMA write cycle DMA read cycle DMA write cycle B Address bus RD LHWR, LLWR TEND Bus released Block transfer Bus released Last block transfer cycle Bus released Figure 7.28 Example of Transfer in Block Transfer Mode Rev.1.00 Jun. 07, 2006 Page 374 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) (4) Activation Timing by DREQ Falling Edge Figure 7.29 shows an example of normal transfer mode activated by the DREQ signal falling edge. The DREQ signal is sampled every cycle from the next rising edge of the B signal immediately after the DTE bit write cycle. When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer request is cleared and starts detecting a high level of the DREQ signal for falling edge detection. If a high level of the DREQ signal has been detected until completion of the DMA write cycle, receiving the next transfer request resumes and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is completed. DMA read cycle DMA write cycle DMA read cycle DMA write cycle Bus released Bus released Bus released B DREQ Address bus DMA operation Wait Transfer source Transfer destination Transfer source Transfer destination Read Write Wait Read Write Wait Channel Request Duration of transfer request disabled Request Duration of transfer request disabled Min. of 3 cycles Min. of 3 cycles [1] [2] [3] [4] [5] [6] [7] Transfer request enable resumed [1] Transfer request enable resumed After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. [2][5] The DMAC is activated and the transfer request is cleared. [3][6] A DMA cycle is started and sampling the DREQ signal at the rising edge of the B signal is started to detect a high level of the DREQ signal. [4][7] When a high level of the DREQ signal has been detected, transfer request enable is resumed after completion of the write cycle. (A low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. This is the same as [1].) Figure 7.29 Example of Transfer in Normal Transfer Mode Activated by DREQ Falling Edge Rev.1.00 Jun. 07, 2006 Page 375 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) Figure 7.30 shows an example of block transfer mode activated by the DREQ signal falling edge. The DREQ signal is sampled every cycle from the next rising edge of the B signal immediately after the DTE bit write cycle. When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer request is cleared and starts detecting a high level of the DREQ signal for falling edge detection. If a high level of the DREQ signal has been detected until completion of the DMA write cycle, receiving the next transfer request resumes and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is completed. 1-block transfer 1-block transfer Bus released DMA read cycle DMA write cycle Bus released DMA read cycle DMA write cycle Bus released B DREQ Address bus DMA operation Wait Transfer source Transfer destination Transfer source Transfer destination Read Write Wait Read Write Wait Channel Request Duration of transfer request disabled Request Duration of transfer request disabled Min. of 3 cycles Min. of 3 cycles [1] [2] [3] [4] [5] [6] [7] Transfer request enable resumed [1] Transfer request enable resumed After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. [2][5] The DMAC is activated and the transfer request is cleared. [3][6] A DMA cycle is started and sampling the DREQ signal at the rising edge of the B signal is started to detect a high level of the DREQ signal. [4][7] When a high level of the DREQ signal has been detected, transfer request enable is resumed after completion of the write cycle. (A low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. This is the same as [1].) Figure 7.30 Example of Transfer in Block Transfer Mode Activated by DREQ Falling Edge Rev.1.00 Jun. 07, 2006 Page 376 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) (5) Activation Timing by DREQ Low Level Figure 7.31 shows an example of normal transfer mode activated by the DREQ signal low level. The DREQ signal is sampled every cycle from the next rising edge of the B signal immediately after the DTE bit write cycle. When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer request is cleared. Receiving the next transfer request resumes after completion of the write cycle and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is completed. DMA read cycle DMA write cycle DMA read cycle DMA write cycle Bus released Bus released Bus released B DREQ Address bus DMA operation Wait Read Transfer source Write Transfer destination Wait Read Transfer source Write Transfer destination Wait Channel Request Duration of transfer request disabled Request Duration of transfer request disabled Min. of 3 cycles Min. of 3 cycles [1] [2] [3] [4] [5] [6] [7] Transfer request enable resumed [1] Transfer request enable resumed After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. [2][5] The DMAC is activated and the transfer request is cleared. [3][6] A DMA cycle is started. [4][7] Transfer request enable is resumed after completion of the write cycle. (A low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. This is the same as [1].) Figure 7.31 Example of Transfer in Normal Transfer Mode Activated by DREQ Low Level Rev.1.00 Jun. 07, 2006 Page 377 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) Figure 7.32 shows an example of block transfer mode activated by the DREQ signal low level. The DREQ signal is sampled every cycle from the next rising edge of the B signal immediately after the DTE bit write cycle. When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer request is cleared. Receiving the next transfer request resumes after completion of the write cycle and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is completed. 1-block transfer Bus released DMA read cycle DMA write cycle Bus released 1-block transfer DMA read cycle DMA write cycle Bus released B DREQ Address bus DMA operation Wait Read Transfer source Transfer destination Transfer source Transfer destination Write Wait Read Write Wait Channel Request Duration of transfer request disabled Request Duration of transfer request disabled Min. of 3 cycles Min. of 3 cycles [1] [2] [3] [4] [5] [6] [7] Transfer request enable resumed [1] Transfer request enable resumed After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. [2][5] The DMAC is activated and the transfer request is cleared. [3][6] A DMA cycle is started. [4][7] Transfer request enable is resumed after completion of the write cycle. (A low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. This is the same as [1].) Figure 7.32 Example of Transfer in Block Transfer Mode Activated by DREQ Low Level Rev.1.00 Jun. 07, 2006 Page 378 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) (6) Activation Timing by DREQ Low Level with NRD = 1 When the NRD bit in DMDR is set to 1, the timing of receiving the next transfer request is delayed for one cycle. Figure 7.33 shows an example of normal transfer mode activated by the DREQ signal low level with NRD = 1. The DREQ signal is sampled every cycle from the next rising edge of the B signal immediately after the DTE bit write cycle. When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer request is cleared. Receiving the next transfer request resumes after completion of the write cycle and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is completed. DMA read cycle DMA read cycle DMA read cycle DMA read cycle Bus released Bus released Bus released B DREQ Address bus Transfer source Transfer destination Transfer source Transfer destination Channel Request Duration of transfer request disabled Duration of transfer request disabled which is extended by NRD Request Duration of transfer request disabled Duration of transfer request disabled which is extended by NRD Min. of 3 cycles Min. of 3 cycles [1] [2] [3] [4] [5] [6] [7] Transfer request enable resumed Transfer request enable resumed After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. [2][5] The DMAC is activated and the transfer request is cleared. [3][6] A DMA cycle is started. [4][7] Transfer request enable is resumed one cycle after completion of the write cycle. (A low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. This is the same as [1].) [1] Figure 7.33 Example of Transfer in Normal Transfer Mode Activated by DREQ Low Level with NRD = 1 Rev.1.00 Jun. 07, 2006 Page 379 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) 7.5.11 (1) Bus Cycles in Single Address Mode Single Address Mode (Read and Cycle Stealing) In single address mode, one byte, one word, or one longword of data is transferred at a single transfer request and after the transfer the bus is released temporarily. One bus cycle or more by the CPU or DTC are executed in the bus released cycles. In figure 7.34, the TEND signal output is enabled and data is transferred in bytes from the external 8-bit 2-state access space to the external device in single address mode (read). DMA read cycle B Address bus RD DACK TEND Bus released Bus released Bus released Bus Last transfer Bus released released cycle DMA read cycle DMA read cycle DMA read cycle Figure 7.34 Example of Transfer in Single Address Mode (Byte Read) Rev.1.00 Jun. 07, 2006 Page 380 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) (2) Single Address Mode (Write and Cycle Stealing) In single address mode, data of one byte, one word, or one longword is transferred at a single transfer request and after the transfer the bus is released temporarily. One bus cycle or more by the CPU or DTC are executed in the bus released cycles. In figure 7.35, the TEND signal output is enabled and data is transferred in bytes from the external 8-bit 2-state access space to the external device in single address mode (write). DMA write cycle B DMA write cycle DMA write cycle DMA write cycle Address bus LLWR DACK TEND Last transfer Bus Bus cycle released released Bus released Bus released Bus released Figure 7.35 Example of Transfer in Single Address Mode (Byte Write) Rev.1.00 Jun. 07, 2006 Page 381 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) (3) Activation Timing by DREQ Falling Edge Figure 7.36 shows an example of single address mode activated by the DREQ signal falling edge. The DREQ signal is sampled every cycle from the next rising edge of the B signal immediately after the DTE bit write cycle. When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer request is cleared and starts detecting a high level of the DREQ signal for falling edge detection. If a high level of the DREQ signal has been detected until completion of the single cycle, receiving the next transfer request resumes and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is completed. Bus released B DMA single cycle Bus released DMA single cycle Bus released DREQ Address bus Transfer source/ Transfer destination Transfer source/ Transfer destination DACK DMA operation Wait Single Wait Single Wait Channel Request Duration of transfer request disabled Request Duration of transfer request disabled Min. of 3 cycles Min. of 3 cycles [1] [2] [3] [4] [5] [6] [7] Transfer request enable resumed [1] Transfer request enable resumed After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. [2][5] The DMAC is activated and the transfer request is cleared. [3][6] A DMA cycle is started and sampling the DREQ signal at the rising edge of the B signal is started to detect a high level of the DREQ signal. [4][7] When a high level of the DREQ signal has been detected, transfer enable is resumed after completion of the write cycle. (A low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. This is the same as [1].) Figure 7.36 Example of Transfer in Single Address Mode Activated by DREQ Falling Edge Rev.1.00 Jun. 07, 2006 Page 382 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) (4) Activation Timing by DREQ Low Level Figure 7.37 shows an example of normal transfer mode activated by the DREQ signal low level. The DREQ signal is sampled every cycle from the next rising edge of the B signal immediately after the DTE bit write cycle. When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer request is cleared. Receiving the next transfer request resumes after completion of the single cycle and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is completed. Bus released B DMA single cycle Bus released DMA single cycle Bus released DREQ Address bus DACK DMA Wait operation Transfer source/ Transfer destination Transfer source/ Transfer destination Single Wait Single Wait Channel Request Duration of transfer request disabled Request Duration of transfer request disabled Min. of 3 cycles Min. of 3 cycles [1] [2] [3] [4] [5] [6] [7] Transfer request enable resumed [1] Transfer request enable resumed After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. [2][5] The DMAC is activated and the transfer request is cleared. [3][6] A DMA cycle is started. [4][7] Transfer request enable is resumed after completion of the single cycle. (A low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. This is the same as [1].) Figure 7.37 Example of Transfer in Single Address Mode Activated by DREQ Low Level Rev.1.00 Jun. 07, 2006 Page 383 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) (5) Activation Timing by DREQ Low Level with NRD = 1 When the NRD bit in DMDR is set to 1, the timing of receiving the next transfer request is delayed for one cycle. Figure 7.38 shows an example of single address mode activated by the DREQ signal low level with NRD = 1. The DREQ signal is sampled every cycle from the next rising edge of the B signal immediately after the DTE bit write cycle. When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer request is cleared. Receiving the next transfer request resumes after one cycle of the transfer request duration inserted by NRD = 1 on completion of the single cycle and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is completed. Bus released DMA single cycle Bus released DMA single cycle Bus released B DREQ Address bus Transfer source/ Transfer destination Transfer source/ Transfer destination Channel Request Duration of transfer request disabled which is extended by NRD Duration of transfer Request request disabled Duration of transfer request disabled which is extended by NRD Duration of transfer request disabled Min. of 3 cycles Min. of 3 cycles [1] [2] [3] [4] [5] [6] [7] Transfer request enable resumed Transfer request enable resumed [1] After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. [2][5] The DMAC is activated and the transfer request is cleared. [3][6] A DMA cycle is started. [4][7] Transfer request enable is resumed one cycle after completion of the single cycle. (A low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. This is the same as [1].) Figure 7.38 Example of Transfer in Single Address Mode Activated by DREQ Low Level with NRD = 1 Rev.1.00 Jun. 07, 2006 Page 384 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) 7.6 DMA Transfer End Operations on completion of a transfer differ according to the transfer end condition. DMA transfer completion is indicated that the DTE and ACT bits in DMDR are changed from 1 to 0. (1) Transfer End by DTCR Change from 1, 2, or 4, to 0 When DTCR is changed from 1, 2, or 4 to 0, a DMA transfer for the channel is completed. The DTE bit in DMDR is cleared to 0 and the DTIF bit in DMDR is set to 1. At this time, when the DTIE bit in DMDR is set to 1, a transfer end interrupt by the transfer counter is requested. When the DTCR value is 0 before the transfer, the transfer is not stopped. (2) Transfer End by Transfer Size Error Interrupt When the following conditions are satisfied while the TSEIE bit in DMDR is set to 1, a transfer size error occurs and a DMA transfer is terminated. At this time, the DTE bit in DMR is cleared to 0 and the ESIF bit in DMDR is set to 1. * In normal transfer mode and repeat transfer mode, when the next transfer is requested while a transfer is disabled due to the DTCR value less than the data access size * In block transfer mode, when the next transfer is requested while a transfer is disabled due to the DTCR value less than the block size When the TSEIE bit in DMDR is cleared to 0, data is transferred until the DTCR value reaches 0. A transfer size error is not generated. Operation in each transfer mode is shown below. * In normal transfer mode and repeat transfer mode, when the DTCR value is less than the data access size, data is transferred in bytes * In block transfer mode, when the DTCR value is less than the block size, the specified size of data in DTCR is transferred instead of transferring the block size of data. The transfer is performed in bytes. Rev.1.00 Jun. 07, 2006 Page 385 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) (3) Transfer End by Repeat Size End Interrupt In repeat transfer mode, when the next transfer is requested after completion of a 1-repeat size data transfer while the RPTIE bit in DACR is set to 1, a repeat size end interrupt is requested. When the interrupt is requested to complete DMA transfer, the DTE bit in DMDR is cleared to 0 and the ESIF bit in DMDR is set to 1. Under this condition, setting the DTE bit to 1 resumes the transfer. In block transfer mode, when the next transfer is requested after completion of a 1-block size data transfer, a repeat size end interrupt can be requested. (4) Transfer End by Interrupt on Extended Repeat Area Overflow When an overflow on the extended repeat area occurs while the extended repeat area is specified and the SARIE or DARIE bit in DACR is set to 1, an interrupt by an extended repeat area overflow is requested. When the interrupt is requested, the DMA transfer is terminated, the DTE bit in DMDR is cleared to 0, and the ESIF bit in DMDR is set to 1. In dual address mode, even if an interrupt by an extended repeat area overflow occurs during a read cycle, the following write cycle is performed. In block transfer mode, even if an interrupt by an extended repeat area overflow occurs during a 1block transfer, the remaining data is transferred. The transfer is not terminated by an extended repeat area overflow interrupt unless the current transfer is complete. (5) Transfer End by Clearing DTE Bit in DMDR When the DTE bit in DMDR is cleared to 0 by the CPU, a transfer is completed after the current DMA cycle and a DMA cycle in which the transfer request is accepted are completed. In block transfer mode, a DMA transfer is completed after 1-block data is transferred. Rev.1.00 Jun. 07, 2006 Page 386 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) (6) Transfer End by NMI Interrupt When an NMI interrupt is requested, the DTE bits for all the channels are cleared to 0 and the ERRF bit in DMDR_0 is set to 1. When an NMI interrupt is requested during a DMA transfer, the transfer is forced to stop. To perform DMA transfer after an NMI interrupt is requested, clear the ERRF bit to 0 and then set the DTE bits for the channels to 1. The transfer end timings after an NMI interrupt is requested are shown below. (a) Normal Transfer Mode and Repeat Transfer Mode In dual address mode, a DMA transfer is completed after completion of the write cycle for one transfer unit. In single address mode, a DMA transfer is completed after completion of the bus cycle for one transfer unit. (b) Block Transfer Mode A DMA transfer is forced to stop. Since a 1-block size of transfers is not completed, operation is not guaranteed. In dual address mode, the write cycle corresponding to the read cycle is performed. This is similar to (a) in normal transfer mode. (7) Transfer End by Address Error When an address error occurs, the DTE bits for all the channels are cleared to 0 and the ERRF bit in DMDR_0 is set to 1. When an address error occurs during a DMA transfer, the transfer is forced to stop. To perform a DMA transfer after an address error occurs, clear the ERRF bit to 0 and then set the DTE bits for the channels. The transfer end timing after an address error is the same as that after an NMI interrupt. (8) Transfer End by Hardware Standby Mode or Reset The DMAC is initialized by a reset and a transition to the hardware standby mode. A DMA transfer is not guaranteed. Rev.1.00 Jun. 07, 2006 Page 387 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) 7.7 7.7.1 Relationship among DMAC and Other Bus Masters CPU Priority Control Function Over DMAC The CPU priority control function over DMAC can be used according to the CPU priority control register (CPUPCR) setting. For details, see section 5.7, CPU Priority Control Function Over DTC and DMAC. The priority level of the DMAC is specified by bits DMAP2 to DMAP0 and can be specified for each channel. The priority level of the CPU is specified by bits CPUP2 to CPUP0. The value of bits CPUP2 to CPUP0 is updated according to the exception handling priority. If the CPU priority control is enabled by the CPUPCE bit in CPUPCR, when the CPU has priority over the DMAC, a transfer request for the corresponding channel is masked and the transfer is not activated. When another channel has priority over or the same as the CPU, a transfer request is received regardless of the priority between channels and the transfer is activated. The transfer request masked by the CPU priority control function is suspended. When the transfer channel is given priority over the CPU by changing priority levels of the CPU or channel, the transfer request is received and the transfer is resumed. Writing 0 to the DTE bit clears the suspended transfer request. When the CPUPCE bit is cleared to 0, it is regarded as the lowest priority. Rev.1.00 Jun. 07, 2006 Page 388 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) 7.7.2 Bus Arbitration among DMAC and Other Bus Masters When DMA transfer cycles are consecutively performed, bus cycles of other bus masters may be inserted between the transfer cycles. The DMAC can release the bus temporarily to pass the bus to other bus masters. The consecutive DMA transfer cycles may not be divided according to the transfer mode settings to achieve high-speed access. The read and write cycles of a DMA transfer are not separated. Refreshing, external bus release, and on-chip bus master (CPU or DTC) cycles are not inserted between the read and write cycles of a DMA transfer. In block transfer mode and an auto request transfer by burst access, bus cycles of the DMA transfer are consecutively performed. For this duration, since the DMAC has priority over the CPU and DTC, accesses to the external space is suspended (the IBCCS bit in the bus control register 2 (BCR2) is cleared to 0). When the bus is passed to another channel or an auto request transfer by cycle stealing, bus cycles of the DMAC and on-chip bus master are performed alternatively. When the arbitration function among the DMAC and on-chip bus masters is enabled by setting the IBCCS bit in BCR2, the bus is used alternatively except the bus cycles which are not separated. For details, see section 6, Bus Controller (BSC). A conflict may occur between external space access of the DMAC and an external bus release cycle. Even if a burst or block transfer is performed by the DMAC, the transfer is stopped temporarily and a cycle of external bus release is inserted by the BSC according to the external bus priority (when the CPU external access and the DTC external access do not have priority over a DMAC transfer, the transfers are not operated until the DMAC releases the bus). In dual address mode, the DMAC releases the external bus after the external space write cycle. Since the read and write cycles are not separated, the bus is not released. An internal space (on-chip memory and internal I/O registers) access of the DMAC and an external bus release cycle may be performed at the same time. Rev.1.00 Jun. 07, 2006 Page 389 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) 7.8 Interrupt Sources The DMAC interrupt sources are a transfer end interrupt by the transfer counter and a transfer escape end interrupt which is generated when a transfer is terminated before the transfer counter reaches 0. Table 7.7 shows interrupt sources and priority. Table 7.7 Abbr. DMTEND0 DMTEND1 DMTEND2 DMTEND3 DMEEND0 Interrupt Sources and Priority Interrupt Sources Transfer end interrupt by channel 0 transfer counter Transfer end interrupt by channel 1 transfer counter Transfer end interrupt by channel 2 transfer counter Transfer end interrupt by channel 3 transfer counter Interrupt by channel 0 transfer size error Interrupt by channel 0 repeat size end Interrupt by channel 0 extended repeat area overflow on source address Interrupt by channel 0 extended repeat area overflow on destination address Priority High DMEEND1 Interrupt by channel 1 transfer size error Interrupt by channel 1 repeat size end Interrupt by channel 1 extended repeat area overflow on source address Interrupt by channel 1 extended repeat area overflow on destination address DMEEND2 Interrupt by channel 2 transfer size error Interrupt by channel 2 repeat size end Interrupt by channel 2 extended repeat area overflow on source address Interrupt by channel 2 extended repeat area overflow on destination address DMEEND3 Interrupt by channel 3 transfer size error Interrupt by channel 3 repeat size end Interrupt by channel 3 extended repeat area overflow on source address Interrupt by channel 3 extended repeat area overflow on destination address Low Each interrupt is enabled or disabled by the DTIE and ESIE bits in DMDR for the corresponding channel. A DMTEND interrupt is generated by the combination of the DTIF and DTIE bits in DMDR. A DMEEND interrupt is generated by the combination of the ESIF and ESIE bits in DMDR. The DMEEND interrupt sources are not distinguished. The priority among channels are decided by the interrupt controller and it is shown in table 7.7. For details, see section 5, Interrupt Controller. Rev.1.00 Jun. 07, 2006 Page 390 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) Each interrupt source is specified by the interrupt enable bit in the register for the corresponding channel. A transfer end interrupt by the transfer counter, a transfer size error interrupt, a repeat size end interrupt, an interrupt by an extended repeat area overflow on the source address, and an interrupt by an extended repeat area overflow on the destination address are enabled or disabled by the DTIE bit in DMDR, the TSEIE bit in DMDR, the RPTIE bit in DACR, SARIE bit in DACR, and the DARIE bit in DACR, respectively. A transfer end interrupt by the transfer counter is generated when the DTIF bit in DMDR is set to 1. The DTIF bit is set to 1 when DTCR becomes 0 by a transfer while the DTIE bit in DMDR is set to 1. An interrupt other than the transfer end interrupt by the transfer counter is generated when the ESIF bit in DMDR is set to 1. The ESIF bit is set to 1 when the conditions are satisfied by a transfer while the enable bit is set to 1. A transfer size error interrupt is generated when the next transfer cannot be performed because the DTCR value is less than the data access size, meaning that the data access size of transfers cannot be performed. In block transfer mode, the block size is compared with the DTCR value for transfer error decision. A repeat size end interrupt is generated when the next transfer is requested after completion of the repeat size of transfers in repeat transfer mode. Even when the repeat area is not specified in the address register, the transfer can be stopped periodically according to the repeat size. At this time, when a transfer end interrupt by the transfer counter is generated, the ESIF bit is set to 1. An interrupt by an extended repeat area overflow on the source and destination addresses is generated when the address exceeds the extended repeat area (overflow). At this time, when a transfer end interrupt by the transfer counter, the ESIF bit is set to 1. Figure 7.39 is a block diagram of interrupts and interrupt flags. To clear an interrupt, clear the DTIF or ESIF bit in DMDR to 0 in the interrupt handling routine or continue the transfer by setting the DTE bit in DMDR after setting the register. Figure 7.40 shows procedure to resume the transfer by clearing a interrupt. Rev.1.00 Jun. 07, 2006 Page 391 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) TSIE bit DMAC is activated in transfer size error state RPTIE bit DMAC is activated after BKSZ bits are changed from 1 to 0 SARIE bit Extended repeat area overflow occurs in source address DARIE bit Extended repeat area overflow occurs in destination address DTIE bit DTIF bit [Setting condition] When DTCR becomes 0 and transfer ends ESIE bit ESIF bit Transfer escape end interrupt Transfer end interrupt Setting condition is satisfied Figure 7.39 Interrupt and Interrupt Sources Transfer end interrupt handling routine Consecutive transfer processing Registers are specified DTE bit is set to 1 Interrupt handling routine ends (RTE instruction executed) [1] [2] [3] Transfer resumed after interrupt handling routine DTIF and ESIF bits are cleared to 0 Interrupt handling routine ends Registers are specified DTE bit is set to 1 [4] [5] [6] [7] Transfer resume processing end Transfer resume processing end [1] Specify the values in the registers such as transfer counter and address register. [2] Set the DTE bit in DMDR to 1 to resume DMA operation. Setting the DTE bit to 1 automatically clears the DTIF or ESIF bit in DMDR to 0 and an interrupt source is cleared. [3] End the interrupt handling routine by the RTE instruction. [4] Read that the DTIF or the ESIF bit in DMDR = 1 and then write 0 to the bit. [5] Complete the interrupt handling routine and clear the interrupt mask. [6] Specify the values in the registers such as transfer counter and address register. [7] Set the DTE bit to 1 to resume DMA operation. Figure 7.40 Procedure Example of Resuming Transfer by Clearing Interrupt Source Rev.1.00 Jun. 07, 2006 Page 392 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) 7.9 Notes on Usage 1. DMAC Register Access During Operation Except for clearing the DTE bit in DMDR, the settings for channels being transferred (including waiting state) must not be changed. The register settings must be changed during the transfer prohibited state. 2. Settings of Module Stop Function The DMAC operation can be enabled or disabled by the module stop control register. The DMAC is enabled by the initial value. Setting bit MSTPA13 in MSTPCRA stops the clock supplied to the DMAC and the DMAC enters the module stop state. However, when a transfer for a channel is enabled or when an interrupt is being requested, bit MSTPA13 cannot be set to 1. Clear the DTE bit to 0, clear the DTIF or DTIE bit in DMDR to 0, and then set bit MSTPA13. When the clock is stopped, the DMAC registers cannot be accessed. However, the following register settings are valid in the module stop state. Disable them before entering the module stop state, if necessary. TENDE bit in DMDR is 1 (the TEND signal output enabled) DACKE bit in DMDR is 1 (the DACK signal output enabled) 3. Activation by DREQ Falling Edge The DREQ falling edge detection is synchronized with the DMAC internal operation. A. Activation request waiting state: Waiting for detecting the DREQ low level. A transition to 2. is made. B. Transfer waiting state: Waiting for a DMAC transfer. A transition to 3. is made. C. Transfer prohibited state: Waiting for detecting the DREQ high level. A transition to 1. is made. After a DMAC transfer enabled, a transition to 1. is made. Therefore, the DREQ signal is sampled by low level detection at the first activation after a DMAC transfer enabled. 4. Acceptation of Activation Source At the beginning of an activation source reception, a low level is detected regardless of the setting of DREQ falling edge or low level detection. Therefore, if the DREQ signal is driven low before setting DMDR, the low level is received as a transfer request. When the DMAC is activated, clear the DREQ signal of the previous transfer. Rev.1.00 Jun. 07, 2006 Page 393 of 1102 REJ09B0294-0100 Section 7 DMA Controller (DMAC) Rev.1.00 Jun. 07, 2006 Page 394 of 1102 REJ09B0294-0100 Section 8 Data Transfer Controller (DTC) Section 8 Data Transfer Controller (DTC) This LSI includes a data transfer controller (DTC). The DTC can be activated to transfer data by an interrupt request. 8.1 Features * Transfer possible over any number of channels: Multiple data transfer enabled for one activation source (chain transfer) Chain transfer specifiable after data transfer (when the counter is 0) * Three transfer modes Normal/repeat/block transfer modes selectable Transfer source and destination addresses can be selected from increment/decrement/fixed * Short address mode or full address mode selectable Short address mode Transfer information is located on a 3-longword boundary The transfer source and destination addresses can be specified by 24 bits to select a 16Mbyte address space directly Full address mode Transfer information is located on a 4-longword boundary The transfer source and destination addresses can be specified by 32 bits to select a 4Gbyte address space directly * Size of data for data transfer can be specified as byte, word, or longword The bus cycle is divided if an odd address is specified for a word or longword transfer. The bus cycle is divided if address 4n + 2 is specified for a longword transfer. * A CPU interrupt can be requested for the interrupt that activated the DTC A CPU interrupt can be requested after one data transfer completion A CPU interrupt can be requested after the specified data transfer completion * Read skip of the transfer information specifiable * Writeback skip executed for the fixed transfer source and destination addresses * Module stop state specifiable Rev.1.00 Jun. 07, 2006 Page 395 of 1102 REJ09B0294-0100 Section 8 Data Transfer Controller (DTC) Figure 8.1 shows a block diagram of the DTC. The DTC transfer information can be allocated to the data area*. When the transfer information is allocated to the on-chip RAM, a 32-bit bus connects the DTC to the on-chip RAM, enabling 32-bit/1-state reading and writing of the DTC transfer information. Note: * When the transfer information is stored in the on-chip RAM, the RAME bit in SYSCR must be set to 1. Interrupt controller DTCERA to DTCERE, DTCERG, and DTCERH DTC On-chip ROM MRA Internal bus (32 bits) Peripheral bus DTCCR On-chip RAM On-chip peripheral module Register control MRB DAR CRA Activation control CRB DTC activation request vector number CPU interrupt request Interrupt source clear request 8 Interrupt control External device (memory mapped) External bus External memory Bus interface Bus controller DTCVBR REQ ACK [Legend] MRA, MRB: SAR: DAR: CRA, CRB: DTCERA to DTCERE, DTCERG, and DTCERH: DTCCR: DTCVBR: DTC mode registers A, B DTC source address register DTC destination address register DTC transfer count registers A, B DTC enable registers A to E, G, and sH DTC control register DTC vector base register Figure 8.1 Block Diagram of DTC Rev.1.00 Jun. 07, 2006 Page 396 of 1102 REJ09B0294-0100 DTC internal bus SAR Section 8 Data Transfer Controller (DTC) 8.2 Register Descriptions DTC has the following registers. * DTC mode register A (MRA) * DTC mode register B (MRB) * DTC source address register (SAR) * DTC destination address register (DAR) * DTC transfer count register A (CRA) * DTC transfer count register B (CRB) These six registers MRA, MRB, SAR, DAR, CRA, and CRB cannot be directly accessed by the CPU. The contents of these registers are stored in the data area as transfer information. When a DTC activation request occurs, the DTC reads a start address of transfer information that is stored in the data area according to the vector address, reads the transfer information, and transfers data. After the data transfer, it writes a set of updated transfer information back to the data area. * DTC enable registers A to E, G, and H (DTCERA to DTCERE, DTCERG, and DTCERH) * DTC control register (DTCCR) * DTC vector base register (DTCVBR) Rev.1.00 Jun. 07, 2006 Page 397 of 1102 REJ09B0294-0100 Section 8 Data Transfer Controller (DTC) 8.2.1 DTC Mode Register A (MRA) MRA selects DTC operating mode. MRA cannot be accessed directly by the CPU. Bit Bit Name Initial Value R/W 7 MD1 Undefined 6 MD0 Undefined 5 Sz1 Undefined 4 Sz0 Undefined 3 SM1 Undefined 2 SM0 Undefined 1 Undefined 0 Undefined Bit 7 6 Bit Name MD1 MD0 Initial Value R/W Description DTC Mode 1 and 0 Specify DTC transfer mode. 00: Normal mode 01: Repeat mode 10: Block transfer mode 11: Setting prohibited Undefined Undefined 5 4 Sz1 Sz0 Undefined Undefined DTC Data Transfer Size 1 and 0 Specify the size of data to be transferred. 00: Byte-size transfer 01: Word-size transfer 10: Longword-size transfer 11: Setting prohibited 3 2 SM1 SM0 Undefined Undefined Source Address Mode 1 and 0 Specify an SAR operation after a data transfer. 0x: SAR is fixed (SAR writeback is skipped) 10: SAR is incremented after a transfer (by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10) 11: SAR is decremented after a transfer (by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10) 1, 0 Undefined Reserved The write value should always be 0. [Legend] X: Don't care Rev.1.00 Jun. 07, 2006 Page 398 of 1102 REJ09B0294-0100 Section 8 Data Transfer Controller (DTC) 8.2.2 DTC Mode Register B (MRB) MRB selects DTC operating mode. MRB cannot be accessed directly by the CPU. Bit Bit Name Initial Value R/W 7 CHNE Undefined 6 CHNS Undefined 5 DISEL Undefined 4 DTS Undefined 3 DM1 Undefined 2 DM0 Undefined 1 Undefined 0 Undefined Bit 7 Bit Name CHNE Initial Value R/W Description DTC Chain Transfer Enable Specifies the chain transfer. For details, see section 8.5.7, Chain Transfer. The chain transfer condition is selected by the CHNS bit. 0: Disables the chain transfer 1: Enables the chain transfer Undefined 6 CHNS Undefined DTC Chain Transfer Select Specifies the chain transfer condition. If the following transfer is a chain transfer, the completion check of the specified transfer count is not performed and activation source flag or DTCER is not cleared. 0: Chain transfer every time 1: Chain transfer only when transfer counter = 0 5 DISEL Undefined DTC Interrupt Select When this bit is set to 1, a CPU interrupt request is generated every time after a data transfer ends. When this bit is set to 0, a CPU interrupt request is only generated when the specified number of data transfer ends. 4 DTS Undefined DTC Transfer Mode Select Specifies either the source or destination as repeat or block area during repeat or block transfer mode. 0: Specifies the destination as repeat or block area 1: Specifies the source as repeat or block area Rev.1.00 Jun. 07, 2006 Page 399 of 1102 REJ09B0294-0100 Section 8 Data Transfer Controller (DTC) Bit 3 2 Bit Name DM1 DM0 Initial Value R/W Description Destination Address Mode 1 and 0 Specify a DAR operation after a data transfer. 0X: DAR is fixed (DAR writeback is skipped) 10: DAR is incremented after a transfer (by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10) 11: SAR is decremented after a transfer (by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10) Undefined Undefined 1, 0 Undefined Reserved The write value should always be 0. [Legend] X: Don't care 8.2.3 DTC Source Address Register (SAR) SAR is a 32-bit register that designates the source address of data to be transferred by the DTC. In full address mode, 32 bits of SAR are valid. In short address mode, the lower 24 bits of SAR is valid and bits 31 to 24 are ignored. At this time, the upper eight bits are filled with the value of bit 23. If a word or longword access is performed while an odd address is specified in SAR or if a longword access is performed while address 4n + 2 is specified in SAR, the bus cycle is divided into multiple cycles to transfer data. For details, see section 8.5.1, Bus Cycle Division. SAR cannot be accessed directly from the CPU. Rev.1.00 Jun. 07, 2006 Page 400 of 1102 REJ09B0294-0100 Section 8 Data Transfer Controller (DTC) 8.2.4 DTC Destination Address Register (DAR) DAR is a 32-bit register that designates the destination address of data to be transferred by the DTC. In full address mode, 32 bits of DAR are valid. In short address mode, the lower 24 bits of DAR is valid and bits 31 to 24 are ignored. At this time, the upper eight bits are filled with the value of bit 23. If a word or longword access is performed while an odd address is specified in DAR or if a longword access is performed while address 4n + 2 is specified in DAR, the bus cycle is divided into multiple cycles to transfer data. For details, see section 8.5.1, Bus Cycle Division. DAR cannot be accessed directly from the CPU. 8.2.5 DTC Transfer Count Register A (CRA) CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC. In normal transfer mode, CRA functions as a 16-bit transfer counter (1 to 65,536). It is decremented by 1 every time data is transferred, and bit DTCEn (n = 15 to 0) corresponding to the activation source is cleared and then an interrupt is requested to the CPU when the count reaches H'0000. The transfer count is 1 when CRA = H'0001, 65,535 when CRA = H'FFFF, and 65,536 when CRA = H'0000. In repeat transfer mode, CRA is divided into two parts: the upper eight bits (CRAH) and the lower eight bits (CRAL). CRAH holds the number of transfers while CRAL functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the contents of CRAH are sent to CRAL when the count reaches H'00. The transfer count is 1 when CRAH = CRAL = H'01, 255 when CRAH = CRAL = H'FF, and 256 when CRAH = CRAL = H'00. In block transfer mode, CRA is divided into two parts: the upper eight bits (CRAH) and the lower eight bits (CRAL). CRAH holds the block size while CRAL functions as an 8-bit block-size counter (1 to 256 for byte, word, or longword). CRAL is decremented by 1 every time a byte (word or longword) data is transferred, and the contents of CRAH are sent to CRAL when the count reaches H'00. The block size is 1 byte (word or longword) when CRAH = CRAL =H'01, 255 bytes (words or longwords) when CRAH = CRAL = H'FF, and 256 bytes (words or longwords) when CRAH = CRAL =H'00. CRA cannot be accessed directly from the CPU. Rev.1.00 Jun. 07, 2006 Page 401 of 1102 REJ09B0294-0100 Section 8 Data Transfer Controller (DTC) 8.2.6 DTC Transfer Count Register B (CRB) CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1 every time data is transferred, and bit DTCEn (n = 15 to 0) corresponding to the activation source is cleared and then an interrupt is requested to the CPU when the count reaches H'0000. The transfer count is 1 when CRB = H'0001, 65,535 when CRB = H'FFFF, and 65,536 when CRB = H'0000. CRB is not available in normal and repeat modes and cannot be accessed directly by the CPU. 8.2.7 DTC enable registers A to E, G, and H (DTCERA to DTCERE, DTCERG, and DTCERH) DTCER which is comprised of eight registers, DTCERA to DTCERE, DTCERG, and DTCERH, is a register that specifies DTC activation interrupt sources. The correspondence between interrupt sources and DTCE bits is shown in table 8.1. Use bit manipulation instructions such as BSET and BCLR to read or write a DTCE bit. If all interrupts are masked, multiple activation sources can be set at one time (only at the initial setting) by writing data after executing a dummy read on the relevant register. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 DTCE15 0 R/W 7 DTCE7 0 R/W 14 DTCE14 0 R/W 6 DTCE6 0 R/W 13 DTCE13 0 R/W 5 DTCE5 0 R/W 12 DTCE12 0 R/W 4 DTCE4 0 R/W 11 DTCE11 0 R/W 3 DTCE3 0 R/W 10 DTCE10 0 R/W 2 DTCE2 0 R/W 9 DTCE9 0 R/W 1 DTCE1 0 R/W 8 DTCE8 0 R/W 0 DTCE0 0 R/W Rev.1.00 Jun. 07, 2006 Page 402 of 1102 REJ09B0294-0100 Section 8 Data Transfer Controller (DTC) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name DTCE15 DTCE14 DTCE13 DTCE12 DTCE11 DTCE10 DTCE9 DTCE8 DTCE7 DTCE6 DTCE5 DTCE4 DTCE3 DTCE2 DTCE1 DTCE0 Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description DTC Activation Enable 15 to 0 Setting this bit to 1 specifies a relevant interrupt source to a DTC activation source. [Clearing conditions] * When writing 0 to the bit to be cleared after reading 1 * When the DISEL bit is 1 and the data transfer has ended * When the specified number of transfers have ended These bits are not cleared when the DISEL bit is 0 and the specified number of transfers have not ended 8.2.8 DTC Control Register (DTCCR) DTCCR specifies transfer information read skip. Bit Bit Name Initial Value R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 RRS 0 R/W 3 RCHNE 0 R/W 2 0 R 1 0 R 0 ERR 0 R/(W)* Note: * Only 0 can be written to clear the flag. Bit 7 to 5 Bit Name Initial Value All 0 R/W R/W Description Reserved These bits are always read as 0. The write value should always be 0. Rev.1.00 Jun. 07, 2006 Page 403 of 1102 REJ09B0294-0100 Section 8 Data Transfer Controller (DTC) Bit 4 Bit Name RRS Initial Value 0 R/W R/W Description DTC Transfer Information Read Skip Enable Controls the vector address read and transfer information read. A DTC vector number is always compared with the vector number for the previous activation. If the vector numbers match and this bit is set to 1, the DTC data transfer is started without reading a vector address and transfer information. If the previous DTC activation is a chain transfer, the vector address read and transfer information read are always performed. 0: Transfer read skip is not performed. 1: Transfer read skip is performed when the vector numbers match. 3 RCHNE 0 R/W Chain Transfer Enable After DTC Repeat Transfer Enables/disables the chain transfer while transfer counter (CRAL) is 0 in repeat transfer mode. In repeat transfer mode, the CRAH value is written to CRAL when CRAL is 0. Accordingly, chain transfer may not occur when CRAL is 0. If this bit is set to 1, the chain transfer is enabled when CRAH is written to CRAL. 0: Disables the chain transfer after repeat transfer 1: Enables the chain transfer after repeat transfer 2, 1 0 ERR All 0 0 R Reserved These are read-only bits and cannot be modified. R/(W)* Transfer Stop Flag Indicates that an address error or an NMI interrupt occurs. If an address error or an NMI interrupt occurs, the DTC stops. 0: No interrupt occurs 1: An interrupt occurs [Clearing condition] * When writing 0 after reading 1 Note: * Only 0 can be written to clear this flag. Rev.1.00 Jun. 07, 2006 Page 404 of 1102 REJ09B0294-0100 Section 8 Data Transfer Controller (DTC) 8.2.9 DTC Vector Base Register (DTCVBR) DTCVBR is a 32-bit register that specifies the base address for vector table address calculation. Bits 31 to 28 and bits 11 to 0 are fixed 0 and cannot be written to. The initial value of DTCVBR is H'00000000. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 15 0 R 14 0 R 13 0 R 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 8.3 Activation Sources The DTC is activated by an interrupt request. The interrupt source is selected by DTCER. A DTC activation source can be selected by setting the corresponding bit in DTCER; the CPU interrupt source can be selected by clearing the corresponding bit in DTCER. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the activation source interrupt flag or corresponding DTCER bit is cleared. 8.4 Location of Transfer Information and DTC Vector Table Locate the transfer information in the data area. The start address of transfer information should be located at the address that is a multiple of four (4n). Otherwise, the lower two bits are ignored during access ([1:0] = B'00.) Transfer information can be located in either short address mode (three longwords) or full address mode (four longwords). The DTCMD bit in SYSCR specifies either short address mode (DTCMD = 1) or full address mode (DTCMD = 0). For details, see section 3.2.2, System Control Register (SYSCR). Transfer information located in the data area is shown in figure 8.2 The DTC reads the start address of transfer information from the vector table according to the activation source, and then reads the transfer information from the start address. Figure 8.3 shows correspondences between the DTC vector address and transfer information. Rev.1.00 Jun. 07, 2006 Page 405 of 1102 REJ09B0294-0100 Section 8 Data Transfer Controller (DTC) Transfer information in short address mode Lower addresses Start address 0 MRA MRB Chain transfer CRA MRA MRB CRA 4 bytes 1 2 SAR DAR CRB SAR DAR CRB Transfer information for one transfer (3 longwords) Transfer information for the 2nd transfer in chain transfer (3 longwords) Chain transfer 3 Start address Transfer information in full address mode Lower addresses 0 1 2 3 Transfer information for one transfer (4 longwords) Reserved (0 write) MRA MRB SAR DAR CRA MRA MRB CRB Reserved (0 write) SAR DAR CRA 4 bytes CRB Transfer information for the 2nd transfer in chain transfer (4 longwords) Figure 8.2 Transfer Information on Data Area Upper: DTCVBR Lower: H'400 + vector number x 4 DTC vector address +4 Vector table Transfer information (1) Transfer information (1) start address Transfer information (2) start address : : : Transfer information (n) start address 4 bytes Transfer information (n) : : : Transfer information (2) +4n Figure 8.3 Correspondence between DTC Vector Address and Transfer Information Rev.1.00 Jun. 07, 2006 Page 406 of 1102 REJ09B0294-0100 Section 8 Data Transfer Controller (DTC) Table 8.1 shows correspondence between the DTC activation source and vector address. Table 8.1 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs Vector Number 64 65 66 67 68 69 70 71 72 73 74 75 86 88 89 90 91 93 94 97 98 101 102 103 104 106 107 110 111 DTC Vector Address Offset H'500 H'504 H'508 H'50C H'510 H'514 H'518 H'51C H'520 H'524 H'528 H'52C H'558 H'560 H'564 H'568 H'56C H'574 H'578 H'584 H'588 H'594 H'598 H'59C H'5A0 H'5A8 H'5AC H'5B8 H'5BC DTCE* DTCEA15 DTCEA14 DTCEA13 DTCEA12 DTCEA11 DTCEA10 DTCEA9 DTCEA8 DTCEA7 DTCEA6 DTCEA5 DTCEA4 DTCEB15 DTCEB13 DTCEB12 DTCEB11 DTCEB10 DTCEB9 DTCEB8 DTCEB7 DTCEB6 DTCEB5 DTCEB4 DTCEB3 DTCEB2 DTCEB1 DTCEB0 DTCEC15 DTCEC14 Low Priority High Origin of Activation Activation Source Source External pin IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 A/D TPU_0 ADI TGI0A TGI0B TGI0C TGI0D TPU_1 TPU_2 TPU_3 TGI1A TGI1B TGI2A TGI2B TGI3A TGI3B TGI3C TGI3D TPU_4 TPU_5 TGI4A TGI4B TGI5A TGI5B Rev.1.00 Jun. 07, 2006 Page 407 of 1102 REJ09B0294-0100 Section 8 Data Transfer Controller (DTC) Origin of Activation Activation Source Source TMR_0 TMR_1 TMR_2 TMR_3 DMAC CMI0A CMI0B CMI1A CMI1B CMI2A CMI2B CMI3A CMI3B DMTEND0 DMTEND1 DMTEND2 DMTEND3 DMAC DMEEND0 DMEEND1 DMEEND2 DMEEND3 SCI_0 SCI_1 SCI_2 SCI_4 Note: * RXI0 TXI0 RXI1 TXI1 RXI2 TXI2 RXI4 TXI4 Vector Number 116 117 119 120 122 123 125 126 128 129 130 131 136 137 138 139 145 146 149 150 153 154 161 162 DTC Vector Address Offset H'5D0 H'5D4 H'5DC H'5E0 H'5E8 H'5EC H'5F4 H'5F8 H'600 H'604 H'608 H'60C H'620 H'624 H'628 H'62C H'644 H'648 H'654 H'658 H'664 H'668 H'684 H'688 DTCE* DTCEC13 DTCEC12 DTCEC11 DTCEC10 DTCEC9 DTCEC8 DTCEC7 DTCEC6 DTCEC5 DTCEC4 DTCEC3 DTCEC2 DTCED13 DTCED12 DTCED11 DTCED10 DTCED5 DTCED4 DTCED3 DTCED2 DTCED1 DTCED0 DTCEE13 DTCEE12 Priority High Low The DTCE bits with no corresponding interrupt are reserved, and the write value should always be 0. To leave software standby mode or all-module-clock-stop mode with an interrupt, write 0 to the corresponding DTCE bit. Rev.1.00 Jun. 07, 2006 Page 408 of 1102 REJ09B0294-0100 Section 8 Data Transfer Controller (DTC) 8.5 Operation The DTC stores transfer information in the data area. When activated, the DTC reads transfer information that is stored in the data area and transfers data on the basis of that transfer information. After the data transfer, it writes updated transfer information back to the data area. Since transfer information is in the data area, it is possible to transfer data over any required number of channels. There are three transfer modes: normal, repeat, and block. The DTC specifies the source address and destination address in SAR and DAR, respectively. After a transfer, SAR and DAR are incremented, decremented, or fixed independently. Table 8.2 shows the DTC transfer modes. Table 8.2 Transfer Mode Normal Repeat* Block* 2 1 DTC Transfer Modes Size of Data Transferred at One Transfer Request 1 byte/word/longword 1 byte/word/longword Memory Address Increment or Decrement Transfer Count Incremented/decremented by 1, 2, or 4, 1 to 65536 or fixed Incremented/decremented by 1, 2, or 4, 1 to 256* or fixed 3 Block size specified by CRAH (1 Incremented/decremented by 1, 2, or 4, 1 to 65536 to 256 bytes/words/longwords) or fixed Notes: 1. Either source or destination is specified to repeat area. 2. Either source or destination is specified to block area. 3. After transfer of the specified transfer count, initial state is recovered to continue the operation. Setting the CHNE bit in MRB to 1 makes it possible to perform a number of transfers with a single activation (chain transfer). Setting the CHNS bit in MRB to 1 can also be made to have chain transfer performed only when the transfer counter value is 0. Figure 8.4 shows a flowchart of DTC operation, and table 8.3 summarizes the chain transfer conditions (combinations for performing the second and third transfers are omitted). Rev.1.00 Jun. 07, 2006 Page 409 of 1102 REJ09B0294-0100 Section 8 Data Transfer Controller (DTC) Start Match & RRS = 1 Vector number comparison Not match | RRS = 0 Read DTC vector Next transfer Read transfer information Transfer data Update transfer information Update the start address of transfer information Write transfer information CHNE = 1 Yes No Transfer counter = 0 or DISEL = 1 Yes No CHNS = 0 Yes No Transfer counter = 0 Yes No DISEL = 1 No Yes Clear activation source flag Clear DTCER/request an interrupt to the CPU End Figure 8.4 Flowchart of DTC Operation Rev.1.00 Jun. 07, 2006 Page 410 of 1102 REJ09B0294-0100 Section 8 Data Transfer Controller (DTC) Table 8.3 Chain Transfer Conditions 1st Transfer 2nd Transfer Transfer 1 CHNE CHNS DISEL Counter* DTC Transfer 0 0 0 0 0 1 0 0 1 Not 0 0* Not 0 0* 2 2 Transfer 1 CHNE CHNS DISEL Counter* 0 0 0 1 0 0 0 1 Not 0 0* 2 Ends at 1st transfer Ends at 1st transfer Interrupt request to CPU Ends at 2nd transfer Ends at 2nd transfer Interrupt request to CPU Ends at 1st transfer Ends at 2nd transfer Ends at 2nd transfer Interrupt request to CPU Ends at 1st transfer Interrupt request to CPU 1 1 1 1 0 Not 0 0* 2 0 0 0 1 1 1 Not 0 Notes: 1. CRA in normal mode transfer, CRAL in repeat transfer mode, or CRB in block transfer mode 2. When the contents of the CRAH is written to the CRAL in repeat transfer mode 8.5.1 Bus Cycle Division When the transfer data size is word and the SAR and DAR values are not a multiple of 2, the bus cycle is divided and the transfer data is read from or written to in bytes. Similarly, when the transfer data size is longword and the SAR and DAR values are not a multiple of 4, the bus cycle is divided and the transfer data is read from or written to in words. Table 8.4 shows the relationship among, SAR, DAR, transfer data size, bus cycle divisions, and access data size. Figure 8.5 shows the bus cycle division example. Table 8.4 Number of Bus Cycle Divisions and Access Size Specified Data Size SAR and DAR Values Byte (B) Address 4n Address 2n + 1 Address 4n + 2 1 (B) 1 (B) 1 (B) Word (W) 1 (W) 2 (B-B) 1 (W) Longword (LW) 1 (LW) 3 (B-W-B) 2 (W-W) Rev.1.00 Jun. 07, 2006 Page 411 of 1102 REJ09B0294-0100 Section 8 Data Transfer Controller (DTC) [Example 1: When an odd address and even address are specified in SAR and DAR, respectively, and when the data size of transfer is specified as word] Clock DTC activation request DTC request R W B W Address B Vector read Transfer information Data transfer Transfer information read write [Example 2: When an odd address and address 4n are specified in SAR and DAR, respectively, and when the data size of transfer is specified as longword] Clock DTC activation request DTC request R W B L Address B W Vector read Transfer information read Data transfer Transfer information write [Example 3: When address 4n + 2 and address 4n are specified in SAR and DAR, respectively, and when the data size of transfer is specified as longword] Clock DTC activation request DTC request R W W L Address W Vector read Transfer information Data transfer Transfer information read write Figure 8.5 Bus Cycle Division Example Rev.1.00 Jun. 07, 2006 Page 412 of 1102 REJ09B0294-0100 Section 8 Data Transfer Controller (DTC) 8.5.2 Transfer Information Read Skip Function By setting the RRS bit of DTCCR, the vector address read and transfer information read can be skipped. The current DTC vector number is always compared with the vector number of previous activation. If the vector numbers match when RRS = 1, a DTC data transfer is performed without reading the vector address and transfer information. If the previous activation is a chain transfer, the vector address read and transfer information read are always performed. Figure 8.6 shows the transfer information read skip timing. To modify the vector table and transfer information, temporarily clear the RRS bit to 0, modify the vector table and transfer information, and then set the RRS bit to 1 again. When the RRS bit is cleared to 0, the stored vector number is deleted, and the updated vector table and transfer information are read at the next activation. Clock DTC activation (1) request DTC request Transfer information read skip Address Vector read R W (2) R W Transfer information Data Transfer information read transfer write Data Transfer information transfer write Note: Transfer information read is skipped when the activation sources of (1) and (2) (vector numbers) are the same while RRS = 1. Figure 8.6 Transfer Information Read Skip Timing Rev.1.00 Jun. 07, 2006 Page 413 of 1102 REJ09B0294-0100 Section 8 Data Transfer Controller (DTC) 8.5.3 Transfer Information Writeback Skip Function By specifying bit SM1 in MRA and bit DM1 in MRB to the fixed address mode, a part of transfer information will not be written back. This function is performed regardless of short or full address mode. Table 8.5 shows the transfer information writeback skip condition and writeback skipped registers. Note that the CRA and CRB are always written back regardless of the short or full address mode. In addition in full address mode, the writeback of the MRA and MRB are always skipped. Table 8.5 Transfer Information Writeback Skip Condition and Writeback Skipped Registers DM1 0 1 0 1 SAR Skipped Skipped Written back Written back DAR Skipped Written back Skipped Written back SM1 0 0 1 1 8.5.4 Normal Transfer Mode In normal transfer mode, one operation transfers one byte, one word, or one longword of data. From 1 to 65,536 transfers can be specified. The transfer source and destination addresses can be specified as incremented, decremented, or fixed. When the specified number of transfers ends, an interrupt can be requested to the CPU. Table 8.6 lists the register function in normal transfer mode. Figure 8.7 shows the memory map in normal transfer mode. Table 8.6 Register SAR DAR CRA CRB Note: * Register Function in Normal Transfer Mode Function Source address Destination address Transfer count A Transfer count B Transfer information writeback is skipped. Written Back Value Incremented/decremented/fixed* Incremented/decremented/fixed* CRA - 1 Not updated Rev.1.00 Jun. 07, 2006 Page 414 of 1102 REJ09B0294-0100 Section 8 Data Transfer Controller (DTC) Transfer source data area Transfer destination data area SAR Transfer DAR Figure 8.7 Memory Map in Normal Transfer Mode 8.5.5 Repeat Transfer Mode In repeat transfer mode, one operation transfers one byte, one word, or one longword of data. By the DTS bit in MRB, either the source or destination can be specified as a repeat area. From 1 to 256 transfers can be specified. When the specified number of transfers ends, the transfer counter and address register specified as the repeat area is restored to the initial state, and transfer is repeated. The other address register is then incremented, decremented, or left fixed. In repeat transfer mode, the transfer counter (CRAL) is updated to the value specified in CRAH when CRAL becomes H'00. Thus the transfer counter value does not reach H'00, and therefore a CPU interrupt cannot be requested when DISEL = 0. Table 8.7 lists the register function in repeat transfer mode. Figure 8.8 shows the memory map in repeat transfer mode. Rev.1.00 Jun. 07, 2006 Page 415 of 1102 REJ09B0294-0100 Section 8 Data Transfer Controller (DTC) Table 8.7 Register Function in Repeat Transfer Mode Written Back Value Register Function SAR Source address CRAL is not 1 CRAL is 1 Incremented/decremented/fixed DTS =0: Incremented/ * decremented/fixed* DTS = 1: SAR initial value DAR Destination address Incremented/decremented/fixed DTS = 0: DAR initial value * DTS =1: Incremented/ decremented/fixed* Transfer count storage Transfer count A Transfer count B * CRAH CRAL - 1 Not updated CRAH CRAH Not updated CRAH CRAL CRB Note: Transfer information writeback is skipped. Transfer source data area (specified as repeat area) Transfer destination data area SAR Transfer DAR Figure 8.8 Memory Map in Repeat Transfer Mode (When Transfer Source is Specified as Repeat Area) Rev.1.00 Jun. 07, 2006 Page 416 of 1102 REJ09B0294-0100 Section 8 Data Transfer Controller (DTC) 8.5.6 Block Transfer Mode In block transfer mode, one operation transfers one block of data. Either the transfer source or the transfer destination is designated as a block area by the DTS bit in MRB. The block size is 1 to 256 bytes (1 to 256 words, or 1 to 256 longwords). When the transfer of one block ends, the block size counter (CRAL) and address register (SAR when DTS = 1 or DAR when DTS = 0) specified as the block area is restored to the initial state. The other address register is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be specified. When the specified number of transfers ends, an interrupt is requested to the CPU. Table 8.8 lists the register function in block transfer mode. Figure 8.9 shows the memory map in block transfer mode. Table 8.8 Register Function in Block Transfer Mode Written Back Value DTS =0: Incremented/decremented/fixed* DTS = 1: SAR initial value DAR CRAH CRAL CRB Note: * Destination address Block size storage Block size counter Block transfer counter DTS = 0: DAR initial value DTS =1: Incremented/decremented/fixed* CRAH CRAH CRB - 1 Register Function SAR Source address Transfer information writeback is skipped. Transfer source data area Transfer destination data area (specified as block area) SAR 1st block : : Nth block Transfer Block area DAR Figure 8.9 Memory Map in Block Transfer Mode (When Transfer Destination is Specified as Block Area) Rev.1.00 Jun. 07, 2006 Page 417 of 1102 REJ09B0294-0100 Section 8 Data Transfer Controller (DTC) 8.5.7 Chain Transfer Setting the CHNE bit in MRB to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. Setting the CHNE and CHNS bits in MRB set to 1 enables a chain transfer only when the transfer counter reaches 0. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 8.10 shows the chain transfer operation. In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the end of the specified number of transfers or by setting the DISEL bit to 1, and the interrupt source flag for the activation source and DTCER are not affected. In repeat transfer mode, setting the RCHNE bit in DTCCR and the CHNE and CHNS bits in MRB to 1 enables a chain transfer after transfer with transfer counter = 1 has been completed. Data area Transfer source data (1) Vector table Transfer information stored in user area Transfer destination data (1) DTC vector address Transfer information start address Transfer information CHNE = 1 Transfer information CHNE = 0 Transfer source data (2) Transfer destination data (2) Figure 8.10 Operation of Chain Transfer Rev.1.00 Jun. 07, 2006 Page 418 of 1102 REJ09B0294-0100 Section 8 Data Transfer Controller (DTC) 8.5.8 Operation Timing Figures 8.11 to 8.14 show the DTC operation timings. Clock DTC activation request DTC request Address Vector read Transfer information read R W Data transfer Transfer information write Figure 8.11 DTC Operation Timing (Example of Short Address Mode in Normal Transfer Mode or Repeat Transfer Mode) Clock DTC activation request DTC request Address Vector read Transfer information read R W R W Data transfer Transfer information write Figure 8.12 DTC Operation Timing (Example of Short Address Mode in Block Transfer Mode with Block Size of 2) Rev.1.00 Jun. 07, 2006 Page 419 of 1102 REJ09B0294-0100 Section 8 Data Transfer Controller (DTC) Clock DTC activation request DTC request Address R W R W Vector read Transfer information read Data transfer Transfer information write Transfer information read Data transfer Transfer information write Figure 8.13 DTC Operation Timing (Example of Short Address Mode in Chain Transfer) Clock DTC activation request DTC request Address R W Vector read Transfer information read Data Transfer information transfer write Figure 8.14 DTC Operation Timing (Example of Full Address Mode in Normal Transfer Mode or Repeat Transfer Mode) Rev.1.00 Jun. 07, 2006 Page 420 of 1102 REJ09B0294-0100 Section 8 Data Transfer Controller (DTC) 8.5.9 Number of DTC Execution Cycles Table 8.9 shows the execution status for a single DTC data transfer, and table 8.10 shows the number of cycles required for each execution. Table 8.9 DTC Execution Status Transfer Information Read J 1 1 1 Mode Vector Read I Transfer Information Write L Data Read L Data Write M Internal Operation N Normal 1 Repeat 1 Block 1 transfer 0* 0* 0* 4* 4* 4* 2 2 2 3* 3* 3* 3 3 3 0* 0* 0* 1 1 1 3* 3* 3* 2.3 2.3 2.3 2* 2* 2* 4 4 4 1* 1* 1* 5 5 5 3* 3* 6 6 2* 2* 7 7 1 1 3* 3* 6 6 2* 2* 7 7 1 1 1 1 0* 0* 0* 1 1 1 3*P *6 2*P*7 1*P 3*P *6 2*P*7 1*P 1 [Legend] P: Block size (CRAH and CRAL value) Note: 1. When transfer information read is skipped 2. In full address mode operation 3. In short address mode operation 4. When the SAR or DAR is in fixed mode 5. When the SAR and DAR are in fixed mode 6. When a longword is transferred while an odd address is specified in the address register 7. When a word is transferred while an odd address is specified in the address register or when a longword is transferred while address 4n + 2 is specified Rev.1.00 Jun. 07, 2006 Page 421 of 1102 REJ09B0294-0100 Section 8 Data Transfer Controller (DTC) Table 8.10 Number of Cycles Required for Each Execution State On-Chip On-Chip Object to be Accessed Bus width Access cycles Execution Vector read SI status RAM ROM On-Chip I/O Registers 8 2 16 2 32 2 2 2 2 2 2 2 1 2 8 8 8 2 4 8 2 4 8 External Devices 8 3 12 + 4m 12 + 4m 12 + 4m 3+m 4 + 2m 12 + 4m 3+m 4 + 2m 12 + 4m 2 4 4 4 2 2 4 2 2 4 16 3 6 + 2m 6 + 2m 6 + 2m 3+m 3+m 6 + 2m 3+m 3+m 6 + 2m 32 1 1 32 1 1 1 1 1 1 1 1 1 1 2 4 8 2 4 8 2 2 4 2 2 4 Transfer information read SJ 1 Transfer information write Sk 1 Byte data read SL Word data read SL Longword data read SL Byte data write SM Word data write SM Longword data write SM Internal operation SN 1 1 1 1 1 1 [Legend] m: Number of wait cycles 0 to 7 (For details, see section 6, Bus Controller (BSC).) The number of execution cycles is calculated from the formula below. Note that means the sum of all transfers activated by one activation event (the number in which the CHNE bit is set to 1, plus 1). Number of execution cycles = I * SI + (J * SJ + K * SK + L * SL + M * SM) + N * SN 8.5.10 DTC Bus Release Timing The DTC requests the bus mastership to the bus arbiter when an activation request occurs. The DTC releases the bus after a vector read, transfer information read, a single data transfer, or transfer information writeback. The DTC does not release the bus during transfer information read, single data transfer, or transfer information writeback. 8.5.11 DTC Priority Level Control to the CPU The priority of the DTC activation sources over the CPU can be controlled by the CPU priority level specified by bits CPUP2 to CPUP0 in CPUPCR and the DTC priority level specified by bits DTCP2 to DTCP0. For details, see section 5, Interrupt Controller. Rev.1.00 Jun. 07, 2006 Page 422 of 1102 REJ09B0294-0100 Section 8 Data Transfer Controller (DTC) 8.6 DTC Activation by Interrupt The procedure for using the DTC with interrupt activation is shown in figure 8.15. DTC activation by interrupt [1] Clearing the RRS bit in DTCCR to 0 clears the read skip flag of transfer information. Read skip is not performed when the DTC is activated after clearing the RRS bit. When updating transfer information, the RRS bit must be cleared. [2] Set the MRA, MRB, SAR, DAR, CRA, and CRB transfer information in the data area. For details on setting transfer information, see section 8.2, Register Descriptions. For details on location of transfer information, see section 8.4, Location of Transfer Information and DTC Vector Table. [3] Set the start address of the transfer information in the DTC vector table. For details on setting DTC vector table, see section 8.4, Location of Transfer Information and DTC Vector Table. [4] [4] Setting the RRS bit to 1 performs a read skip of second time or later transfer information when the DTC is activated consecutively by the same interrupt source. Setting the RRS bit to 1 is always allowed. However, the value set during transfer will be valid from the next transfer. [5] Set the bit in DTCER corresponding to the DTC activation interrupt source to 1. For the correspondence of interrupts and DTCER, refer to table 8.1. The bit in DTCER may be set to 1 on the second or later transfer. In this case, setting the bit is not needed. [6] Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC is activated when an interrupt used as an activation source is generated. For details on the settings of the interrupt enable bits, see the corresponding descriptions of the corresponding module. Clear activation source [7] [7] After the end of one data transfer, the DTC clears the activation source flag or clears the corresponding bit in DTCER and requests an interrupt to the CPU. The operation after transfer depends on the transfer information. For details, see section 8.2, Register Descriptions and figure 8.4. Clear RRS bit in DTCCR to 0 [1] Set transfer information (MRA, MRB, SAR, DAR, CRA, CRB) [2] Set starts address of transfer information in DTC vector table [3] Set RRS bit in DTCCR to 1 Set corresponding bit in DTCER to 1 [5] Set enable bit of interrupt request for activation source to 1 [6] Interrupt request generated DTC activated Determine clearing method of activation source Clear corresponding bit in DTCER Corresponding bit in DTCER cleared or CPU interrupt requested Transfer end Figure 8.15 DTC with Interrupt Activation Rev.1.00 Jun. 07, 2006 Page 423 of 1102 REJ09B0294-0100 Section 8 Data Transfer Controller (DTC) 8.7 8.7.1 Examples of Use of the DTC Normal Transfer Mode An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. 1. Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal transfer mode (MD1 = MD0 = 0), and byte size (Sz1 = Sz0 = 0). The DTS bit can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the RDR address of the SCI in SAR, the start address of the RAM area where the data will be received in DAR, and 128 (H'0080) in CRA. CRB can be set to any value. 2. Set the start address of the transfer information for an RXI interrupt at the DTC vector address. 3. Set the corresponding bit in DTCER to 1. 4. Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the receive end (RXI) interrupt. Since the generation of a receive error during the SCI reception operation will disable subsequent reception, the CPU should be enabled to accept receive error interrupts. 5. Each time reception of one byte of data ends on the SCI, the RDRF flag in SSR is set to 1, an RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR to RAM by the DTC. DAR is incremented and CRA is decremented. The RDRF flag is automatically cleared to 0. 6. When CRA becomes 0 after the 128 data transfers have ended, the RDRF flag is held at 1, the DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. Termination processing should be performed in the interrupt handling routine. 8.7.2 Chain Transfer An example of DTC chain transfer is shown in which pulse output is performed using the PPG. Chain transfer can be used to perform pulse output data transfer and PPG output trigger cycle updating. Repeat mode transfer to the PPG's NDR is performed in the first half of the chain transfer, and normal mode transfer to the TPU's TGR in the second half. This is because clearing of the activation source and interrupt generation at the end of the specified number of transfers are restricted to the second half of the chain transfer (transfer when CHNE = 0). Rev.1.00 Jun. 07, 2006 Page 424 of 1102 REJ09B0294-0100 Section 8 Data Transfer Controller (DTC) 1. Perform settings for transfer to the PPG's NDR. Set MRA to source address incrementing (SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), repeat mode (MD1 = 0, MD0 = 1), and word size (Sz1 = 0, Sz0 = 1). Set the source side as a repeat area (DTS = 1). Set MRB to chain transfer mode (CHNE = 1, CHNS = 0, DISEL = 0). Set the data table start address in SAR, the NDRH address in DAR, and the data table size in CRAH and CRAL. CRB can be set to any value. 2. Perform settings for transfer to the TPU's TGR. Set MRA to source address incrementing (SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), normal mode (MD1 = MD0 = 0), and word size (Sz1 = 0, Sz0 = 1). Set the data table start address in SAR, the TGRA address in DAR, and the data table size in CRA. CRB can be set to any value. 3. Locate the TPU transfer information consecutively after the NDR transfer information. 4. Set the start address of the NDR transfer information to the DTC vector address. 5. Set the bit corresponding to the TGIA interrupt in DTCER to 1. 6. Set TGRA as an output compare register (output disabled) with TIOR, and enable the TGIA interrupt with TIER. 7. Set the initial output value in PODR, and the next output value in NDR. Set bits in DDR and NDER for which output is to be performed to 1. Using PCR, select the TPU compare match to be used as the output trigger. 8. Set the CST bit in TSTR to 1, and start the TCNT count operation. 9. Each time a TGRA compare match occurs, the next output value is transferred to NDR and the set value of the next output trigger period is transferred to TGRA. The activation source TGFA flag is cleared. 10. When the specified number of transfers are completed (the TPU transfer CRA value is 0), the TGFA flag is held at 1, the DTCE bit is cleared to 0, and a TGIA interrupt request is sent to the CPU. Termination processing should be performed in the interrupt handling routine. 8.7.3 Chain Transfer when Counter = 0 By executing a second data transfer and performing re-setting of the first data transfer only when the counter value is 0, it is possible to perform 256 or more repeat transfers. An example is shown in which a 128-kbyte input buffer is configured. The input buffer is assumed to have been set to start at lower address H'0000. Figure 8.16 shows the chain transfer when the counter value is 0. Rev.1.00 Jun. 07, 2006 Page 425 of 1102 REJ09B0294-0100 Section 8 Data Transfer Controller (DTC) 1. For the first transfer, set the normal transfer mode for input data. Set the fixed transfer source address, CRA = H'0000 (65,536 times), CHNE = 1, CHNS = 1, and DISEL = 0. 2. Prepare the upper 8-bit addresses of the start addresses for 65,536-transfer units for the first data transfer in a separate area (in ROM, etc.). For example, if the input buffer is configured at addresses H'200000 to H'21FFFF, prepare H'21 and H'20. 3. For the second transfer, set repeat transfer mode (with the source side as the repeat area) for resetting the transfer destination address for the first data transfer. Use the upper eight bits of DAR in the first transfer information area as the transfer destination. Set CHNE = DISEL = 0. If the above input buffer is specified as H'200000 to H'21FFFF, set the transfer counter to 2. 4. Execute the first data transfer 65536 times by means of interrupts. When the transfer counter for the first data transfer reaches 0, the second data transfer is started. Set the upper eight bits of the transfer source address for the first data transfer to H'21. The lower 16 bits of the transfer destination address of the first data transfer and the transfer counter are H'0000. 5. Next, execute the first data transfer the 65536 times specified for the first data transfer by means of interrupts. When the transfer counter for the first data transfer reaches 0, the second data transfer is started. Set the upper eight bits of the transfer source address for the first data transfer to H'20. The lower 16 bits of the transfer destination address of the first data transfer and the transfer counter are H'0000. 6. Steps 4 and 5 are repeated endlessly. As repeat mode is specified for the second data transfer, no interrupt request is sent to the CPU. Input circuit Transfer information located on the on-chip memory Input buffer 1st data transfer information 2nd data transfer information Chain transfer (counter = 0) Upper 8 bits of DAR Figure 8.16 Chain Transfer when Counter = 0 Rev.1.00 Jun. 07, 2006 Page 426 of 1102 REJ09B0294-0100 Section 8 Data Transfer Controller (DTC) 8.8 Interrupt Sources An interrupt request is issued to the CPU when the DTC finishes the specified number of data transfers or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and priority level control in the interrupt controller. 8.9 8.9.1 Usage Notes Module Stop State Setting Operation of the DTC can be disabled or enabled using the module stop control register. The initial setting is for operation of the DTC to be enabled. Register access is disabled by setting the module stop state. The module stop state cannot be set while the DTC is activated. For details, refer to section 23, Power-Down Modes. 8.9.2 On-Chip RAM Transfer information can be located in on-chip RAM. In this case, the RAME bit in SYSCR must not be cleared to 0. 8.9.3 DMAC Transfer End Interrupt When the DTC is activated by a DMAC transfer end interrupt, the DTE bit of DMDR is not controlled by the DTC but its value is modified with the write data regardless of the transfer counter value and DISEL bit setting. Accordingly, even if the DTC transfer counter value becomes 0, no interrupt request may be sent to the CPU in some cases. 8.9.4 DTCE Bit Setting For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts are disabled, multiple activation sources can be set at one time (only at the initial setting) by writing data after executing a dummy read on the relevant register. Rev.1.00 Jun. 07, 2006 Page 427 of 1102 REJ09B0294-0100 Section 8 Data Transfer Controller (DTC) 8.9.5 Chain Transfer When chain transfer is used, clearing of the activation source or DTCER is performed when the last of the chain of data transfers is executed. At this time, SCI and A/D converter interrupt/activation sources, are cleared when the DTC reads or writes to the relevant register. Therefore, when the DTC is activated by an interrupt or activation source, if a read/write of the relevant register is not included in the last chained data transfer, the interrupt or activation source will be retained. 8.9.6 Transfer Information Start Address, Source Address, and Destination Address The transfer information start address to be specified in the vector table should be address 4n. If an address other than address 4n is specified, the lower 2 bits of the address are regarded as 0s. The source and destination addresses specified in SAR and DAR, respectively, will be transferred in the divided bus cycles depending on the address and data size. 8.9.7 Transfer Information Modification When IBCCS = 1 and the DMAC is used, clear the IBCCS bit to 0 and then set to 1 again before modifying the DTC transfer information in the CPU exception handling routine initiated by a DTC transfer end interrupt. 8.9.8 Endian Format The DTC supports big and little endian formats. The endian formats used when transfer information is written to and when transfer information is read from by the DTC must be the same. Rev.1.00 Jun. 07, 2006 Page 428 of 1102 REJ09B0294-0100 Section 9 I/O Ports Section 9 I/O Ports Table 9.1 summarizes the port functions. The pins of each port also have other functions such as input/output pins of on-chip peripheral modules or external interrupt input pins. Each I/O port includes a data direction register (DDR) that controls input/output, a data register (DR) that stores output data, a port register (PORT) used to read the pin states, and an input buffer control register (ICR) that controls input buffer on/off. Port 5 does not have a DR or a DDR register. Ports D to F, H, and I have internal input pull-up MOSs and a pull-up MOS control register (PCR) that controls the on/off state of the input pull-up MOSs. Ports 2 and F include an open-drain control register (ODR) that controls on/off of the output buffer PMOSs. All of the I/O ports can drive a single TTL load and capacitive loads up to 30 pF. All of the I/O ports can drive Darlington transistors when functioning as output ports. Port 2 and 3 are Schmitt-trigger input. Schmitt-trigger inputs for other ports are enabled when used as the IRQ, TPU, TMR, or IIC2 inputs. Table 9.1 Port Functions Function SchmittTrigger Input*1 Input Pull-up MOS Function OpenDrain Output Function Port Description Bit I/O P17/SCL0 Input IRQ7-A/ TCLKD-B IRQ6-A/ TCLKC-B IRQ5-A/ TCLKB-B/ RxD5/ IrRXD DREQ1-A/ IRQ4-A/ TCLKA-B ADTRG0/ IRQ3-A Output Port 1 General I/O port 7 also functioning as interrupt inputs, SCI I/Os, DMAC 6 I/Os, A/D converter inputs, TPU inputs, and 5 IIC2 I/Os IRQ7-A, TCLKD-B, SCL0 IRQ6-A, TCLKC-B, SDA0 IRQ5-A, TCLKB-B, SCL1 IRQ4-A, TCLKA-B, SDA1 IRQ3-A P16/SDA0 DACK1-A P15/SCL1 TEND1-A 4 P14/SDA1 TxD5/ IrTxD 3 P13 Rev.1.00 Jun. 07, 2006 Page 429 of 1102 REJ09B0294-0100 Section 9 I/O Ports Function SchmittTrigger Input *1 IRQ2-A IRQ1-A IRQ0-A Input Pull-up MOS Function OpenDrain Output Function Port Description Bit I/O P12/SCK2 P11 P10 Input IRQ2-A RxD2/ IRQ1-A DREQ0-A/ IRQ0-A Output DACK0-A TEND0-A TxD2 2 Port 1 General I/O port also functioning 1 as interrupt inputs, SCI I/Os, DMAC 0 I/Os, A/D converter inputs, TPU inputs, and IIC2 I/Os Port 2 General I/O port 7 also functioning as interrupt inputs, PPG outputs, TPU 6 I/Os, TMR I/Os, and SCI I/Os 5 P27/ TIOCB5 P26/ TIOCA5 P25/ TIOCA4 P24/ TIOCB4/ SCK1 P23/ TIOCD3 P22/ TIOCC3 P21/ TIOCA3 TIOCA5 PO7 P27, TIOCB5, TIOCA5 O TMCI1/ RxD1 TIOCA4/ TMRI1 PO6/TMO1/ All input TxD1 functions PO5 P25, TIOCA4, TMCI1 P24, TIOCB4, TIOCA4, TMRI1 P23, TIOCD3, IRQ11-A 4 PO4 3 IRQ11-A/ TIOCC3 IRQ10-A TMCI0/ RxD0/ IRQ9-A TIOCA3/ TMRI0/ IRQ8-A PO3 2 1 PO2/TMO0/ All input TxD0 functions PO1 P21, IRQ9-A, TIOCA3, TMCI0 P20, IRQ8-A, TIOCB3, TIOCA3, TMRI0 0 P20/ TIOCB3/ SCK0 PO0 Rev.1.00 Jun. 07, 2006 Page 430 of 1102 REJ09B0294-0100 Section 9 I/O Ports Function SchmittTrigger Input *1 All input functions All input functions All input functions All input functions All input functions All input functions All input functions All input functions IRQ7-B IRQ6-B IRQ5-B IRQ4-B IRQ3-B IRQ2-B IRQ1-B IRQ0-B Input Pull-up MOS Function OpenDrain Output Function Port Description Bit 7 6 5 4 3 I/O P37/ TIOCB2 P36/ TIOCA2 P35/ TIOCB1 P34/ TIOCA1 P33/ TIOCD0 P32/ TIOCC0 P31/ TIOCB0 P30/ TIOCA0 Input TIOCA2/ TCLKD-A TIOCA1/ TCLKC-A TIOCC0/ TCLKB-A/ DREQ1-B TCLKA-A TIOCA0 DREQ0-B P57/AN7/ IRQ7-B P56/AN6/ IRQ6-B P55/AN5/ IRQ5-B P54/AN4/ IRQ4-B P53/AN3/ IRQ3-B P52/AN2/ IRQ2-B P51/AN1/ IRQ1-B P50/AN0/ IRQ0-B Output PO15 PO14 PO13/ DACK1-B PO12/ TEND1-B PO11 Port 3 General I/O port also functioning as PPG outputs, DMAC I/Os, and TPU I/Os 2 1 0 Port 5 General input port 7 also functioning as interrupt inputs, 6 A/D converter inputs, and D/A converter outputs 5 4 3 2 1 0 PO10/ DACK0-B PO9/ TEND0-B PO8 DA1 DA0 Rev.1.00 Jun. 07, 2006 Page 431 of 1102 REJ09B0294-0100 Section 9 I/O Ports Function SchmittTrigger Input*1 TMCI3 TMRI3, IRQ11-B Input Pull-up MOS Function OpenDrain Output Function Port Description Bit 7 6 5 4 3 I/O P65 P64 P63 Input TCK TMCI3/TDI TMRI3/ DREQ3/ IRQ11-B/ TMS IRQ10-B/ TRST TMCI2/ RxD4/ IRQ9-B TMRI2/ DREQ2/ IRQ8-B PA7 BREQ/ WAIT Output TMO3/ DACK3 TEND3 Port 6 General I/O port also functioning as SCI inputs, DMAC I/Os, H-UDI inputs, and interrupt inputs 2 1 P62/SCK4 P61 TMO2/ DACK2 TEND2 IRQ10-B TMCI2, IRQ9-B TMRI2, IRQ8-B 0 P60 TxD4 Port A General I/O port also functioning as system clock output and bus control I/Os 7 6 5 4 3 2 1 0 PA6 PA5 PA4 PA3 PA2 PA1 PA0 B AS/AH/ BS-B RD LHWR/LUB LLWR/LLB BACK/ (RD/WR) BREQO/ BS-A Rev.1.00 Jun. 07, 2006 Page 432 of 1102 REJ09B0294-0100 Section 9 I/O Ports Function SchmittTrigger Input*1 Input Pull-up MOS Function OpenDrain Output Function Port Description Bit 7 6 5 4 3 I/O PB7 PB6 PB5 PB4 PB3 Input Output SD CS6-D (RD/WR-B) CS5-D/ OE/CKE CS4-B/WE CS3-A/ CS7-A/ CAS CS2-A/ CS6-A/ RAS CS1/ CS2-B/ CS5-A/ CS6-B/ CS7-B CS0/ CS4-A/ CS5-B LLCAS/ DQMLL LUCAS/ DQMLU Port B General I/O port also functioning as bus control outputs 2 PB2 1 PB1 0 PB0 Port C General I/O port also functioning as bus control I/Os and A/D converter inputs 7 6 5 4 3 2 1 0 PC3 PC2 Rev.1.00 Jun. 07, 2006 Page 433 of 1102 REJ09B0294-0100 Section 9 I/O Ports Function SchmittTrigger Input*1 Input Pull-up MOS Function OpenDrain Output Function Port Description Bit 7 6 5 4 3 2 1 0 I/O PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 Input Output A7 A6 A5 A4 A3 A2 A1 A0 A15 A14 A13 A12 A11 A10 A9 A8 A23 A22 A21 A20 A19 A18 A17 A16 Port D General I/O port also functioning as address outputs O Port E General I/O port also functioning as address outputs 7 6 5 4 3 2 1 0 O Port F General I/O port also functioning as address outputs 7 6 5 4 3 2 1 0 O O Rev.1.00 Jun. 07, 2006 Page 434 of 1102 REJ09B0294-0100 Section 9 I/O Ports Function SchmittTrigger Input*1 Input Pull-up MOS Function O OpenDrain Output Function Port Description Bit 7 6 5 4 3 2 1 0 I/O PH7/D7* PH6/D6* PH5/D5* PH4/D4* PH3/D3* 2 Input RxD6 Output TxD6 Port H General I/O port also functioning as bi-directional data bus 2 2 2 2 PH2/D2*2 PH1/D1* PH0/D0* 2 2 Port I General I/O port also functioning as bi-directional data bus 7 6 5 4 3 2 1 0 PI7/D15* PI6/D14* PI5/D13* PI4/D12* PI3/D11* 2 O 2 2 2 2 PI2/D10*2 PI1/D9* PI0/D8* PM4 PM3 PM2 PM1 PM0 2 2 Port M General I/O port also functioning as SCI I/Os 7 6 5 4 3 2 1 0 Notes: 1. Pins without Schmitt-trigger input buffer have CMOS input buffer. 2. Addresses are also output when accessing to the address/data multiplexed I/O space. Rev.1.00 Jun. 07, 2006 Page 435 of 1102 REJ09B0294-0100 Section 9 I/O Ports 9.1 Register Descriptions Table 9.2 lists each port registers. Table 9.2 Register Configuration in Each Port Number of Pins 8 8 8 8 6 8 4 2 8 8 8 8 8 5 Registers DDR O O O O O O O O O O O O O DR O O O O O O O O O O O O O PORT O O O O O O O O O O O O O O ICR O O O O O O O O O O O O O O PCR O O O O O ODR O O Port Port 1 Port 2 Port 3 Port 5 Port 6 Port A Port B Port C* Port D Port E Port F Port H Port I Port M [Legend] O: Register exists : No register exists Note: * The write value should always be the initial value. Rev.1.00 Jun. 07, 2006 Page 436 of 1102 REJ09B0294-0100 Section 9 I/O Ports 9.1.1 Data Direction Register (PnDDR) (n = 1, 2, 3, 6, A to F, H, I, and M) DDR is an 8-bit write-only register that specifies the port input or output for each bit. A read from the DDR is invalid and DDR is always read as an undefined value. When the general I/O port function is selected, the corresponding pin functions as an output port by setting the corresponding DDR bit to 1; the corresponding pin functions as an input port by clearing the corresponding DDR bit to 0. The initial DDR values are shown in table 9.3. Bit Bit Name Initial Value R/W Note: 7 Pn7DDR 0 W 6 Pn6DDR 0 W 5 Pn5DDR 0 W 4 Pn4DDR 0 W 3 Pn3DDR 0 W 2 Pn2DDR 0 W 1 Pn1DDR 0 W 0 Pn0DDR 0 W The lower six bits are valid and the upper two bits are reserved for port 6 registers. The lower five bits are valid and the upper three bits are reserved for port M registers. Bits 2 and 3 are valid and the other bits are reserved for port C registers. Table 9.3 Startup Mode and Initial Value Startup Mode Port Port A Other ports External Extended Mode H'80 Single-Chip Mode H'00 H'00 Rev.1.00 Jun. 07, 2006 Page 437 of 1102 REJ09B0294-0100 Section 9 I/O Ports 9.1.2 Data Register (PnDR) (n = 1, 2, 3, 6, A to F, H, I, and M) DR is an 8-bit readable/writable register that stores the output data of the pins to be used as the general output port. The initial value of DR is H'00. Bit Bit Name Initial Value R/W Note: 7 Pn7DR 0 R/W 6 Pn6DR 0 R/W 5 Pn5DR 0 R/W 4 Pn4DR 0 R/W 3 Pn3DR 0 R/W 2 Pn2DR 0 R/W 1 Pn1DR 0 R/W 0 Pn0DR 0 R/W The lower six bits are valid and the upper two bits are reserved for port 6 registers. The lower five bits are valid and the upper three bits are reserved for port M registers. Bits 2 and 3 are valid and the other bits are reserved for port C registers. 9.1.3 Port Register (PORTn) (n = 1, 2, 3, 5, 6, A to F, H, I, and M) PORT is an 8-bit read-only register that reflects the port pin state. A write to PORT is invalid. When PORT is read, the DR bits that correspond to the respective DDR bits set to 1 are read and the status of each pin whose corresponding DDR bit is cleared to 0 is also read regardless of the ICR value. The initial value of PORT is undefined and is determined based on the port pin state. Bit Bit Name Initial Value R/W Note: 7 Pn7 Undefined R 6 Pn6 Undefined R 5 Pn5 Undefined R 4 Pn4 Undefined R 3 Pn3 Undefined R 2 Pn2 Undefined R 1 Pn1 Undefined R 0 Pn0 Undefined R The lower six bits are valid and the upper two bits are reserved for port 6 registers. The lower five bits are valid and the upper three bits are reserved for port M registers. Bits 2 and 3 are valid and the other bits are reserved for port C registers. Rev.1.00 Jun. 07, 2006 Page 438 of 1102 REJ09B0294-0100 Section 9 I/O Ports 9.1.4 Input Buffer Control Register (PnICR) (n = 1, 2, 3, 5, 6, A to F, H, I, and M) ICR is an 8-bit readable/writable register that controls the port input buffers. For bits in ICR set to 1, the input buffers of the corresponding pins are valid. For bits in ICR cleared to 0, the input buffers of the corresponding pins are invalid and the input signals are fixed high. When the pin functions as an input for the peripheral modules, the corresponding bits should be set to 1. The initial value should be written to a bit whose corresponding pin is not used as an input or is used as an analog input/output pin. When PORT is read, the pin state is always read regardless of the ICR value. When the ICR value is cleared to 0 at this time, the read pin state is not reflected in a corresponding on-chip peripheral module. If ICR is modified, an internal edge may occur depending on the pin state. Accordingly, ICR should be modified when the corresponding input pins are not used. For example, an IRQ input, modify ICR while the corresponding interrupt is disabled, clear the IRQF flag in ISR of the interrupt controller to 0, and then enable the corresponding interrupt. If an edge occurs after the ICR setting, the edge should be cancelled. The initial value of ICR is H'00. Bit Bit Name Initial Value R/W Note: 7 Pn7ICR 0 R/W 6 Pn6ICR 0 R/W 5 Pn5ICR 0 R/W 4 Pn4ICR 0 R/W 3 Pn3ICR 0 R/W 2 Pn2ICR 0 R/W 1 Pn1ICR 0 R/W 0 Pn0ICR 0 R/W The lower six bits are valid and the upper two bits are reserved for port 6 registers. The lower five bits are valid and the upper three bits are reserved for port M registers. Bits 2 and 3 are valid and the other bits are reserved for port C registers. Rev.1.00 Jun. 07, 2006 Page 439 of 1102 REJ09B0294-0100 Section 9 I/O Ports 9.1.5 Pull-Up MOS Control Register (PnPCR) (n = D to F, H, and I) PCR is an 8-bit readable/writable register that controls on/off of the port input pull-up MOS. If a bit in PCR is set to 1 while the pin is in input state, the input pull-up MOS corresponding to the bit in PCR is turned on. Table 9.4 shows the input pull-up MOS status. The initial value of PCR is H'00. Bit Bit Name Initial Value R/W 7 Pn7PCR 0 R/W 6 Pn6PCR 0 R/W 5 Pn5PCR 0 R/W 4 Pn4PCR 0 R/W 3 Pn3PCR 0 R/W 2 Pn2PCR 0 R/W 1 Pn1PCR 0 R/W 0 Pn0PCR 0 R/W Table 9.4 Port Port D Input Pull-Up MOS State Pin State Address output Port output Port input OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF ON/OFF ON/OFF ON/OFF ON/OFF Reset Hardware Standby Mode Software Standby Mode OFF OFF ON/OFF Other Operation Port E Address output Port output Port input Address output Port output Port input Port F Port H Data input/output Port output Port input Data input/output Port output Port input Port I [Legend] OFF: ON/OFF: The input pull-up MOS is always off. If PCR is set to 1, the input pull-up MOS is on; if PCR is cleared to 0, the input pull-up MOS is off. Rev.1.00 Jun. 07, 2006 Page 440 of 1102 REJ09B0294-0100 Section 9 I/O Ports 9.1.6 Open-Drain Control Register (PnODR) (n = 2 and F) ODR is an 8-bit readable/writable register that selects the open-drain output function. If a bit in ODR is set to 1, the pin corresponding to that bit in ODR functions as an NMOS opendrain output. If a bit in ODR is cleared to 0, the pin corresponding to that bit in ODR functions as a CMOS output. The initial value of ODR is H'00. Bit Bit Name Initial Value R/W 7 Pn7ODR 0 R/W 6 Pn6ODR 0 R/W 5 Pn5ODR 0 R/W 4 Pn4ODR 0 R/W 3 Pn3ODR 0 R/W 2 Pn2ODR 0 R/W 1 Pn1ODR 0 R/W 0 Pn0ODR 0 R/W 9.2 Output Buffer Control This section describes the output priority of each pin. The name of each peripheral module pin is followed by "_OE". This (for example: TIOCA4_OE) indicates whether the output of the corresponding function is valid (1) or if another setting is specified (0). Table 9.5 lists each port output signal's valid setting. For details on the corresponding output signals, see the register description of each peripheral module. If the name of each peripheral module pin is followed by A or B, the pin function can be modified by the port function control register (PFCR). For details, see section 9.3, Port Function Controller. For a pin whose initial value changes according to the activation mode, "Initial value E" indicates the initial value when the LSI is started up in external extended mode and "Initial value S" indicates the initial value when the LSI is started in single-chip mode. Rev.1.00 Jun. 07, 2006 Page 441 of 1102 REJ09B0294-0100 Section 9 I/O Ports 9.2.1 (1) Port 1 P17/IRQ7-A/TCLKD-B/SCL0 The pin function is switched as shown below according to the combination of the IIC2 register setting and P17DDR bit setting. Setting IIC2 Module Name IIC2 I/O port Pin Function SCL0 input/output P17 output P17 input (initial setting) Note: * SCL0_OE* 1 0 0 I/O Port P17DDR 1 0 When pin functions as I/O: 1 (2) P16/DACK1-A/IRQ6-A/TCLKC-B/SDA0 The pin function is switched as shown below according to the combination of the DMAC and IIC2 register setting and P16DDR bit setting. Setting DMAC Module Name DMAC IIC2 I/O port Pin Function DACK1-A output SDA0 input/output P16 output P16 input (initial setting) Note: * DACK1A_OE* 1 0 0 0 IIC2 SDA0_OE* 1 0 0 I/O Port P16DDR -- 1 0 When pin functions as I/O: 1 Rev.1.00 Jun. 07, 2006 Page 442 of 1102 REJ09B0294-0100 Section 9 I/O Ports (3) P15/RxD5/IrRXD/TEND1-A/IRQ5-A/TCLKB-B/SCL1 The pin function is switched as shown below according to the combination of the DMAC and IIC2 register setting and P15DDR bit setting. Setting DMAC Module Name DMAC IIC2 I/O port Pin Function TEND1-A output SCL1 input/output P15 output P15 input (initial setting) Note: * When pin functions as I/O: 1 TEND1A_OE* 1 0 0 0 IIC2 SCL1_OE* 1 0 0 I/O Port P15DDR -- 1 0 (4) P14/TxD5/IrTXD/DREQ1-A/IRQ4-A/TCLKA-B/SDA1 The pin function is switched as shown below according to the combination of the SCI, IrDA, and IIC2 register setting and P14DDR bit setting. Setting SCI Module Name SCI IrDA IIC2 I/O port Pin Function TxD5 output IrTXD output SDA1 input/output P14 output P14 input (initial setting) Note: * When pin functions as I/O: 1 TxD5_OE 1 0 0 0 0 IrDA IrTXD_OE -- 1 0 0 0 IIC2 SDA1_OE* -- -- 1 0 0 I/O Port P14DDR -- -- -- 1 0 Rev.1.00 Jun. 07, 2006 Page 443 of 1102 REJ09B0294-0100 Section 9 I/O Ports (5) P13/ADTRG0/IRQ3-A The pin function is switched as shown below according to the P13DDR bit setting. Setting I/O Port Module Name I/O port Pin Function P13 output P13 input (initial setting) P13DDR 1 0 (6) P12/SCK2/DACK0-A/IRQ2-A The pin function is switched as shown below according to the combination of the DMAC and SCI register settings and P12DDR bit setting. Setting DMAC Module Name DMAC SCI I/O port Pin Function DACK0-A output SCK2 output P12 output P12 input (initial setting) DACK0A_OE 1 0 0 0 SCI SCK2_OE 1 0 0 I/O Port P12DDR 1 0 Rev.1.00 Jun. 07, 2006 Page 444 of 1102 REJ09B0294-0100 Section 9 I/O Ports (7) P11/RxD2/TEND0-A/IRQ1-A The pin function is switched as shown below according to the combination of the DMAC register setting and P11DDR bit setting. Setting DMAC Module Name DMAC I/O port Pin Function TEND0-A output P11 output P11 input (initial setting) TEND0A_OE 1 0 0 I/O Port P11DDR 1 0 (8) P10/TxD2/DREQ0-A/IRQ0-A: The pin function is switched as shown below according to the combination of the SCI register setting and P10DDR bit setting. Setting SCI Module Name SCI I/O port Pin Function TxD2 output P10 output P10 input (initial setting) TxD2_OE 1 0 0 I/O Port P10DDR 1 0 Rev.1.00 Jun. 07, 2006 Page 445 of 1102 REJ09B0294-0100 Section 9 I/O Ports 9.2.2 (1) Port 2 P27/PO7/TIOCA5/TIOCB5 The pin function is switched as shown below according to the combination of the TPU and PPG register settings and P27DDR bit setting. Setting TPU Module Name TPU PPG I/O port Pin Function TIOCB5 output PO7 output P27 output P27 input (initial setting) TIOCB5_OE 1 0 0 0 PPG PO7_OE -- 1 0 0 I/O Port P27DDR -- -- 1 0 (2) P26/PO6/TIOCA5/TMO1/TxD1 The pin function is switched as shown below according to the combination of the TPU, TMR, SCI, and PPG register settings and P26DDR bit setting. Setting TPU Module Name TPU TMR SCI PPG I/O port Pin Function TIOCA5 output TMO1 output TxD1 output PO6 output P26 output P26 input (initial setting) TMR 1 0 0 0 0 SCI TxD1_OE PPG PO6_OE I/O Port P26DDR TIOCA5_OE TMO1_OE 1 0 0 0 0 0 1 0 0 0 1 0 0 1 0 Rev.1.00 Jun. 07, 2006 Page 446 of 1102 REJ09B0294-0100 Section 9 I/O Ports (3) P25/PO5/TIOCA4/TMCI1/RxD1 The pin function is switched as shown below according to the combination of the TPU and PPG register settings and P25DDR bit setting. Setting TPU Module Name TPU PPG I/O port Pin Function TIOCA4 output PO5 output P25 output P25 input (initial setting) TIOCA4_OE 1 0 0 0 PPG PO5_OE 1 0 0 I/O Port P25DDR 1 0 (4) P24/PO4/TIOCA4/TIOCB4/TMRI1/SCK1 The pin function is switched as shown below according to the combination of the TPU, SCI, and PPG register settings and P24DDR bit setting. Setting TPU Module Name TPU SCI PPG I/O port Pin Function TIOCB4 output SCK1 output PO4 output P24 output P24 input (initial setting) SCI 1 0 0 0 PPG PO4_OE 1 0 0 I/O Port P24DDR 1 0 TIOCB4_OE SCK1_OE 1 0 0 0 0 Rev.1.00 Jun. 07, 2006 Page 447 of 1102 REJ09B0294-0100 Section 9 I/O Ports (5) P23/PO3/TIOCC3/TIOCD3/IRQ11-A The pin function is switched as shown below according to the combination of the TPU and PPG register settings and P23DDR bit setting. Setting TPU Module Name TPU PPG I/O port Pin Function TIOCD3 output PO3 output P23 output P23 input (initial setting) TIOCD3_OE 1 0 0 0 PPG PO3_OE -- 1 0 0 I/O Port P23DDR -- -- 1 0 (6) P22 /PO2/TIOCC3/TMO0/TxD0/IRQ10-A The pin function is switched as shown below according to the combination of the TPU, TMR, SCI, and PPG register settings and P22DDR bit setting. Setting TPU Module Name TPU TMR SCI PPG I/O port Pin Function TIOCC3 output TMO0 output TxD0 output PO2 output P22 output P22 input (initial setting) TIOCC3_OE TMR 1 0 0 0 0 SCI 1 0 0 0 PPG PO2_OE I/O Port P22DDR TMO0_OE TxD0_OE 1 0 0 0 0 0 1 0 0 1 0 Rev.1.00 Jun. 07, 2006 Page 448 of 1102 REJ09B0294-0100 Section 9 I/O Ports (7) P21/PO1/TIOCA3/TMCI0/RxD0/IRQ9-A The pin function is switched as shown below according to the combination of the TPU and PPG register settings and P21DDR bit setting. Setting TPU Module Name TPU PPG I/O port Pin Function TIOCA3 output PO1 output P21 output P21 input (initial setting) TIOCA3_OE 1 0 0 0 PPG PO1_OE 1 0 0 I/O Port P21DDR 1 0 (8) P20/PO0/TIOCA3/TIOCB3/TMRI0/SCK0/IRQ8-A The pin function is switched as shown below according to the combination of the TPU, SCI, and PPG register settings and P20DDR bit setting. Setting TPU Module Name TPU SCI PPG I/O port Pin Function TIOCB3 output SCK0 output PO0 output P20 output P20 input (initial setting) SCI 1 0 0 0 PPG PO0_OE 1 0 0 I/O Port P20DDR 1 0 TIOCB3_OE SCK0_OE 1 0 0 0 0 Rev.1.00 Jun. 07, 2006 Page 449 of 1102 REJ09B0294-0100 Section 9 I/O Ports 9.2.3 (1) Port 3 P37/PO15/TIOCA2/TIOCB2/TCLKD-A The pin function is switched as shown below according to the combination of the TPU and PPG register settings and P37DDR bit setting. Setting TPU Module Name TPU PPG I/O port Pin Function TIOCB2 output PO15 output P37 output P37 input (initial setting) TIOCB2_OE 1 0 0 0 PPG PO15_OE -- 1 0 0 I/O Port P37DDR -- -- 1 0 (2) P36/PO14/TIOCA2 The pin function is switched as shown below according to the combination of the TPU and PPG register settings and P36DDR bit setting. Setting TPU Module Name TPU PPG I/O port Pin Function TIOCA2 output PO14 output P36 output P36 input (initial setting) TIOCA2_OE 1 0 0 0 PPG PO14_OE -- 1 0 0 I/O Port P36DDR -- -- 1 0 Rev.1.00 Jun. 07, 2006 Page 450 of 1102 REJ09B0294-0100 Section 9 I/O Ports (3) P35/PO13/TIOCA1/TIOCB1/TCLKC-A/DACK1-B The pin function is switched as shown below according to the combination of the DMAC, TPU, and PPG register settings and P35DDR bit setting. Setting DMAC Module Name DMAC TPU PPG I/O port Pin Function DACK1-B output TIOCB1 output PO13 output P35 output P35 input (initial setting) DACK1B_OE 1 0 0 0 0 TPU 1 0 0 0 PPG 1 0 0 I/O Port P35DDR 1 0 TIOCB1_OE PO13_OE (4) P34/PO12/TIOCA1/TEND1-B The pin function is switched as shown below according to the combination of the DMAC, TPU, and PPG register settings and P34DDR bit setting. Setting DMAC Module Name DMAC TPU PPG I/O port Pin Function TEND1-B output TIOCA1 output PO12 output P34 output P34 input (initial setting) TPU 1 0 0 0 PPG 1 0 0 I/O Port P34DDR 1 0 TEND1B_OE TIOCA1_OE PO12_OE 1 0 0 0 0 Rev.1.00 Jun. 07, 2006 Page 451 of 1102 REJ09B0294-0100 Section 9 I/O Ports (5) P33/PO11/TIOCC0/TIOCD0/TCLKB-A/DREQ1-B The pin function is switched as shown below according to the combination of the TPU and PPG register settings and P33DDR bit setting. Setting TPU Module Name TPU PPG I/O port Pin Function TIOCD0 output PO11 output P33 output P33 input (initial setting) TIOCD0_OE 1 0 0 0 PPG PO11_OE -- 1 0 0 I/O Port P33DDR -- -- 1 0 (6) P32/PO10/TIOCC0/TCLKA-A/DACK0-B The pin function is switched as shown below according to the combination of the DMAC, TPU, and PPG register settings and P32DDR bit setting. Setting DMAC Module Name DMAC TPU PPG I/O port Pin Function DACK0-B output TIOCC0 output PO10 output P32 output P32 input (initial setting) TPU 1 0 0 0 PPG 1 0 0 I/O Port P32DDR 1 0 DACK0B_OE TIOCC0_OE PO10_OE 1 0 0 0 0 Rev.1.00 Jun. 07, 2006 Page 452 of 1102 REJ09B0294-0100 Section 9 I/O Ports (7) P31/PO9/TIOCA0/TIOCB0/TEND0-B The pin function is switched as shown below according to the combination of the DMAC, TPU, and PPG register settings and P31DDR bit setting. Setting DMAC Module Name DMAC TPU PPG I/O port Pin Function TEND0-B output TIOCB0 output PO9 output P31 output P31 input (initial setting) TPU 1 0 0 0 PPG 1 0 0 I/O Port P31DDR 1 0 TEND0B_OE TIOCB0_OE PO9_OE 1 0 0 0 0 (8) P30/PO8/TIOCA0/DREQ0-B The pin function is switched as shown below according to the combination of the TPU and PPG register settings and P33DDR bit setting. Setting TPU Module Name TPU PPG I/O port Pin Function TIOCA0 output PO8 output P30 output P30 input (initial setting) TIOCA0_OE 1 0 0 0 PPG PO8_OE 1 0 0 I/O Port P30DDR 1 0 Rev.1.00 Jun. 07, 2006 Page 453 of 1102 REJ09B0294-0100 Section 9 I/O Ports 9.2.4 (1) Port 5 P57/AN7/DA1/IRQ7-B Pin Function DA1 output Module Name D/A converter (2) P56/AN6/DA0/IRQ6-B Pin Function DA0 output Module Name D/A converter 9.2.5 (1) Port 6 P65/TMO3/DACK3/TCK The pin function is switched as shown below according to the combination of the DMAC and TMR register settings and P65DDR bit setting. Setting DMAC Module Name DMAC TMR I/O port Pin Function DACK3 output TMO3 output P65 output P65 input (initial setting) DACK3_OE 1 0 0 0 TMR TMO3_OE 1 0 0 I/O Port P65DDR 1 0 Rev.1.00 Jun. 07, 2006 Page 454 of 1102 REJ09B0294-0100 Section 9 I/O Ports (2) P64/TMCI3/TEND3/TDI The pin function is switched as shown below according to the combination of the DMAC register setting and P64DDR bit setting. Setting DMAC Module Name DMAC I/O port Pin Function TEND3 output P64 output P64 input (initial setting) TEND3_OE 1 0 0 I/O Port P64DDR 1 0 (3) P63/TMRI3/DREQ3/IRQ11-B/TMS The pin function is switched as shown below according to the P63DDR bit setting. Setting I/O Port Module Name I/O port Pin Function P63 output P63 input (initial setting) P63DDR 1 0 Rev.1.00 Jun. 07, 2006 Page 455 of 1102 REJ09B0294-0100 Section 9 I/O Ports (4) P62/TMO2/SCK4/DACK2/IRQ10-B/TRST The pin function is switched as shown below according to the combination of the DMAC, TMR, and SCI register settings and P62DDR bit setting. Setting DMAC Module Name DMAC TMR SCI I/O port Pin Function DACK2 output TMO2 output SCK4 output P62 output P62 input (initial setting) DACK2_OE TMR TMO2_OE SCI SCK4_OE I/O Port P62DDR 1 0 0 0 0 1 0 0 0 1 0 0 1 0 (5) P61/TMCI2/RxD4/TEND2/IRQ9-B The pin function is switched as shown below according to the combination of the DMAC register setting and P61DDR bit setting. Setting DMAC Module Name DMAC I/O port Pin Function TEND2 output P61 output P61 input (initial setting) TEND2_OE 1 0 0 I/O Port P61DDR 1 0 Rev.1.00 Jun. 07, 2006 Page 456 of 1102 REJ09B0294-0100 Section 9 I/O Ports (6) P60/TMRI2/TxD4/DREQ2/IRQ8-B The pin function is switched as shown below according to the combination of the SCI register setting and P60DDR bit setting. Setting SCI Module Name SCI I/O port Pin Function TxD4 output P60 output P60 input (initial setting) TxD4_OE 1 0 0 I/O Port P60DDR 1 0 9.2.6 (1) Port A PA7/B The pin function is switched as shown below according to the PA7DDR bit setting. Setting I/O Port Module Name I/O port Pin Function B output* (initial setting E) PA7 input (initial setting S) PA7DDR 1 0 [Legend] Initial setting E: Initial setting in external extended mode Initial setting S: Initial setting in single-chip mode Note: * The type of to be output switches according to the POSEL1 bit in SCKCR. For details, see section 22.1.1, System Clock Control Register (SCKCR). Rev.1.00 Jun. 07, 2006 Page 457 of 1102 REJ09B0294-0100 Section 9 I/O Ports (2) PA6/AS/AH/BS-B The pin function is switched as shown below according to the combination of operating mode, EXPE bit, bus controller register, port function control register (PFCR), and the PA6DDR bit settings. Setting Bus Controller Module Name Bus controller Pin Function AH output* BS-B output* AS output* (initial setting E) PA6 output PA6 input (initial setting S) AH_OE 1 0 0 0 0 I/O Port BSB_OE 1 0 0 0 AS_OE 1 0 0 PA6DDR 1 0 I/O port [Legend] Initial setting E: Initial setting in external extended mode Initial setting S: Initial setting in single-chip mode Note: * Valid in external extended mode (EXPE = 1) (3) PA5/RD The pin function is switched as shown below according to the combination of operating mode, the EXPE bit, and the PA5DDR bit settings. Setting MCU Operating Mode Module Name Bus controller I/O port Pin Function RD output* (Initial setting E) PA5 output PA5 input (initial setting S) EXPE 1 0 0 PA5DDR 1 0 I/O Port [Legend] Initial setting E: Initial setting in external extended mode Initial setting S: Initial setting in single-chip mode Note: * Valid in external extended mode (EXPE = 1) Rev.1.00 Jun. 07, 2006 Page 458 of 1102 REJ09B0294-0100 Section 9 I/O Ports (4) PA4/LHWR/LUB The pin function is switched as shown below according to the combination of operating mode, EXPE bit, bus controller register, port function control register (PFCR), and the PA4DDR bit settings. Setting Bus Controller Module Name Bus controller Pin Function LUB output* 1 1 I/O Port LHWR_OE* 1 0 0 2 LUB_OE* 1 0 0 2 PA4DDR 1 0 LHWR output* (initial setting E) I/O port PA4 output PA4 input (initial setting S) [Legend] Initial setting E: Initial setting in external extended mode Initial setting S: Initial setting in single-chip mode Notes: 1. Valid in external extended mode (EXPE = 1) 2. When the byte control SRAM space is accessed while the byte control SRAM space is specified or while LHWROE = 1, this pin functions as the LUB output; otherwise, the LHWR output. Rev.1.00 Jun. 07, 2006 Page 459 of 1102 REJ09B0294-0100 Section 9 I/O Ports (5) PA3/LLWR/LLB The pin function is switched as shown below according to the combination of operating mode, EXPE bit, bus controller register, and the PA3DDR bit settings. Setting Bus Controller Module Name Bus controller Pin Function LLB output* 1 1 I/O Port LLWR_OE* 1 0 0 2 LLB_OE* 1 0 0 2 PA3DDR 1 0 LLWR output* (initial setting E) I/O port PA3 output PA3 input (initial setting S) [Legend] Initial setting E: Initial setting in external extended mode Initial setting S: Initial setting in single-chip mode Notes: 1. Valid in external extended mode (EXPE = 1) 2. If the byte control SRAM space is accessed, this pin functions as the LLB output; otherwise, the LLWR. (6) PA2/BREQ/WAIT The pin function is switched as shown below according to the combination of the bus controller register setting and the PA2DDR bit setting. Setting Bus Controller Module Name Bus controller Pin Function BREQ input WAIT input I/O port PA2 output PA2 input (initial setting) BCR_BRLE 1 0 0 0 BCR_WAITE 1 0 0 I/O Port PA2DDR 1 0 Rev.1.00 Jun. 07, 2006 Page 460 of 1102 REJ09B0294-0100 Section 9 I/O Ports (7) PA1/BACK/(RD/WR) The pin function is switched as shown below according to the combination of operating mode, EXPE bit, bus controller register, port function control register (PFCR), and the PA1DDR bit settings. Setting Bus Controller Byte control SRAM Selection I/O Port Module Name Bus controller Pin Function BACK output * RD/WR output * BACK_OE (RD/WR)_OE PA1DDR 1 0 0 1 0 0 0 1 0 0 1 0 I/O port PA1 output PA1 input (initial setting) 0 0 Note: * Valid in external extended mode (EXPE = 1) (8) PA0/BREQO/BS-A The pin function is switched as shown below according to the combination of operating mode, EXPE bit, bus controller register, port function control register (PFCR), and the PA0DDR bit settings. Setting I/O Port Module Name Bus controller Pin Function BS-A output* BREQO output* I/O port PA0 output PA0 input (initial setting) Note: * BSA_OE 1 0 0 0 Bus Controller BREQO_OE 1 0 0 I/O Port PA0DDR 1 0 Valid in external extended mode (EXPE = 1) Rev.1.00 Jun. 07, 2006 Page 461 of 1102 REJ09B0294-0100 Section 9 I/O Ports 9.2.7 (1) Port B PB7/SD The pin function is switched as shown below according to the combination of operating mode, EXPE bit, port function control register (PFCR), and the PB7DDR bit settings. Setting MCU Operating Mode Module Name Clock pulse generator I/O port Pin Function SD output* PB7 output PB7 input (initial setting) Note: * Valid in SDRAM mode SDRAM Mode 1 0 0 I/O Port PB7DDR 1 0 (2) PB6/CS6-D/(RD/WR-B) The pin function is switched as shown below according to the combination of operating mode, EXPE bit, bus controller register, port function control register (PFCR), and the PB6DDR bit settings. Setting I/O Port Byte control SRAM Selection Module Name Bus controller Pin Function (RD/WR)-B_OE CS6D_OE 1 0 0 PB6DDR 1 0 RD/WR-B output* 1 0 CS6-D output* 0 0 0 1 0 0 0 I/O port PB6 output PB6 input (initial setting) Note: * Valid in external extended mode (EXPE = 1) Rev.1.00 Jun. 07, 2006 Page 462 of 1102 REJ09B0294-0100 Section 9 I/O Ports (3) PB5/CS5-D/OE/CKE The pin function is switched as shown below according to the combination of operating mode, EXPE bit, bus controller register, port function control register (PFCR), and the PB5DDR bit settings. Setting I/O Port Module Name Bus controller Pin Function CKE output* OE output* CS5-D output* I/O port PB5 output PB5 input (initial setting) Note: * CKE_OE 1 0 0 0 0 OE_OE 1 0 0 0 CS5D_OE 1 0 0 PB5DDR 1 0 Valid in external extended mode (EXPE = 1) (4) PB4/CS4-B/WE The pin function is switched as shown below according to the combination of operating mode, EXPE bit, bus controller register, port function control register (PFCR), and the PB4DDR bit settings. Setting Bus Controller Module Name Bus controller Pin Function WE output* CS4-B output* I/O port PB4 output PB4 input (initial setting) Note: * WE_OE 1 0 0 0 CS4B_OE 1 0 0 I/O Port PB4DDR 1 0 Valid in external extended mode (EXPE = 1) Rev.1.00 Jun. 07, 2006 Page 463 of 1102 REJ09B0294-0100 Section 9 I/O Ports (5) PB3/CS3-A/CS7-A/CAS The pin function is switched as shown below according to the combination of operating mode, EXPE bit, bus controller register, port function control register (PFCR), and the PB3DDR bit settings. Setting Bus Controller Module Name Bus controller Pin Function CAS output* CS3-A output* CS7-A output* I/O port PB3 output PB3 input (initial setting) Note: * CAS_OE 1 0 0 0 0 CS3A_OE 1 0 0 1 0 0 I/O Port CS7A_OE PB3DDR 1 0 Valid in external extended mode (EXPE = 1) (6) PB2/CS2-A/CS6-A/RAS The pin function is switched as shown below according to the combination of operating mode, EXPE bit, bus controller register, port function control register (PFCR), and the PB2DDR bit settings. Setting Bus Controller Module Name Bus controller Pin Function RAS output* CS2-A output* CS6-A output* I/O port PB2 output PB2 input (initial setting) Note: * RAS_OE 1 0 0 0 0 CS2A_OE 1 0 0 1 0 0 I/O Port CS6A_OE PB2DDR 1 0 Valid in external extended mode (EXPE = 1) Rev.1.00 Jun. 07, 2006 Page 464 of 1102 REJ09B0294-0100 Section 9 I/O Ports (7) PB1/CS1/CS2-B/CS5-A/CS6-B/CS7-B The pin function is switched as shown below according to the combination of operating mode, EXPE bit, port function control register (PFCR), and the PB1DDR bit settings. Setting I/O Port Module Name Bus controller Pin Function CS1 output* CS2-B output* CS5-A output* CS6-B output* CS7-B output* I/O port PB1 output PB1 input (initial setting) Note: * CS1_OE CS2B_OE CS5A_OE CS6B_OE CS7B_OE PB1DDR 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 Valid in external extended mode (EXPE = 1) (8) PB0/CS0/CS4/CS5-B The pin function is switched as shown below according to the combination of operating mode, EXPE bit, port function control register (PFCR), and the PB0DDR bit settings. Setting I/O Port Module Name Bus controller Pin Function CS0 output (initial setting E) CS4 output CS5-B output I/O port PB0 output PB0 input (initial setting S) [Legend] Initial setting E: Initial setting S: CS0_OE 1 0 0 CS4_OE 1 0 0 CS5B_OE 1 0 0 PB0DDR 1 0 Initial setting in on-chip ROM disabled external extended mode Initial setting in other modes Rev.1.00 Jun. 07, 2006 Page 465 of 1102 REJ09B0294-0100 Section 9 I/O Ports 9.2.8 (1) Port C PC3/LLCAS/DQMLL The pin function is switched as shown below according to the combination of operating mode, EXPE bit, bus controller register, and the PC3DDR bit settings. Setting Bus Controller Module Name Bus controller Pin Function LLCAS output* DQMLL output* I/O port PC3 output PC3 input (initial setting) Note: * LLCAS_OE 1 0 0 DQMLL_OE 1 0 0 I/O Port PC3DDR 1 0 Valid in external extended mode (EXPE = 1) (2) PC2/LUCAS/DQMLU The pin function is switched as shown below according to the combination of operating mode, EXPE bit, bus controller register, and the PC2DDR bit settings. Setting Bus Controller Module Name Bus controller Pin Function LUCAS output* DQMLU output* I/O port PC2 output PC2 input (initial setting) Note: * LUCAS_OE 1 0 0 DQMLU_OE 1 0 0 I/O Port PC2DDR 1 0 Valid in external extended mode (EXPE = 1) Rev.1.00 Jun. 07, 2006 Page 466 of 1102 REJ09B0294-0100 Section 9 I/O Ports 9.2.9 (1) Port D PD7/A7, PD6/A6, PD5/A5, PD4/A4, PD3/A3, PD2/A2, PD1/A1, PD0/A0 The pin function is switched as shown below according to the combination of operating mode, the EXPE bit, and the PDnDDR bit settings. Setting I/O Port Module Name Bus controller I/O port Pin Function Address output PDn output PDn input (initial setting) MCU Operating Mode On-chip ROM disabled extended mode On-chip ROM enabled extended mode Single-chip mode* Modes other than on-chip ROM disabled extended mode PDnDDR 1 1 0 [Legend] n: 0 to 7 Note: * Address output is enabled by setting PDnDDR = 1 in external extended mode (EXPE = 1) 9.2.10 (1) Port E PE7/A15, PE6/A14, PE5/A13, PE4/A12, PE3/A11, PE2/A10, PE1/A9, PE0/A8 The pin function is switched as shown below according to the combination of operating mode, the EXPE bit, and the PEnDDR bit settings. Setting I/O Port Module Name Bus controller I/O port Pin Function Address output PEn output PEn input (initial setting) MCU Operating Mode On-chip ROM disabled extended mode On-chip ROM enabled extended mode Single-chip mode* Modes other than on-chip ROM disabled extended mode PEnDDR 1 1 0 [Legend] n: 0 to 7 Note: * Address output is enabled by setting PDnDDR = 1 in external extended mode (EXPE = 1) Rev.1.00 Jun. 07, 2006 Page 467 of 1102 REJ09B0294-0100 Section 9 I/O Ports 9.2.11 (1) Port F PF7/A23 The pin function is switched as shown below according to the combination of operating mode, the EXPE bit, port function control register (PFCR), and the PF7DDR bit settings. Setting MCU Operating Mode Bus controller I/O port I/O Port Pin Function A23 output* PF7 output PF7 input (initial setting) A23_OE 1 0 0 I/O Port PF7DDR 1 0 Note: * Valid in external extended mode (EXPE = 1) (2) PF6/A22 The pin function is switched as shown below according to the combination of operating mode, the EXPE bit, port function control register (PFCR), and the PF6DDR bit settings. Setting MCU Operating Mode Bus controller I/O port I/O Port Pin Function A22 output* PF6 output PF6 input (initial setting) A22_OE 1 0 0 I/O Port PF6DDR 1 0 Note: * Valid in external extended mode (EXPE = 1) Rev.1.00 Jun. 07, 2006 Page 468 of 1102 REJ09B0294-0100 Section 9 I/O Ports (3) PF5/A21 The pin function is switched as shown below according to the combination of operating mode, the EXPE bit, port function control register (PFCR), and the PF5DDR bit settings. Setting MCU Operating Mode Bus controller I/O port I/O Port Pin Function A21 output* PF5 output PF5 input (initial setting) Note: * A21_OE 1 0 0 I/O Port PF5DDR 1 0 Valid in external extended mode (EXPE = 1) (4) PF4/A20 The pin function is switched as shown below according to the combination of operating mode, the EXPE bit, port function control register (PFCR), and the PF4DDR bit settings. Setting MCU Operating Mode On-chip ROM disabled extended mode Modes other than on-chip ROM disabled extended mode Note: * I/O Port Module Name Bus controller Pin Function A20 output A20_OE I/O Port PF4DDR Bus controller I/O port A20 output* PF4 output PF4 input (initial setting) 1 0 0 1 0 Valid in external extended mode (EXPE = 1) Rev.1.00 Jun. 07, 2006 Page 469 of 1102 REJ09B0294-0100 Section 9 I/O Ports (5) PF3/A19 The pin function is switched as shown below according to the combination of operating mode, the EXPE bit, port function control register (PFCR), and the PF3DDR bit settings. Setting MCU Operating Mode On-chip ROM disabled extended mode Modes other than on-chip ROM disabled extended mode Note: * I/O Port Module Name Bus controller Pin Function A19 output A19_OE I/O Port PF3DDR Bus controller I/O port A19 output* PF3 output PF3 input (initial setting) 1 0 0 1 0 Valid in external extended mode (EXPE = 1) (6) PF2/A18 The pin function is switched as shown below according to the combination of operating mode, the EXPE bit, port function control register (PFCR), and the PF2DDR bit settings. Setting MCU Operating Mode On-chip ROM disabled extended mode Modes other than on-chip ROM disabled extended mode Note: * I/O Port Module Name Bus controller Pin Function A18 output A18_OE I/O Port PF2DDR Bus controller I/O port A18 output* PF2 output PF2 input (initial setting) 1 0 0 1 0 Valid in external extended mode (EXPE = 1) Rev.1.00 Jun. 07, 2006 Page 470 of 1102 REJ09B0294-0100 Section 9 I/O Ports (7) PF1/A17 The pin function is switched as shown below according to the combination of operating mode, the EXPE bit, port function control register (PFCR), and the PF1DDR bit settings. Setting MCU Operating Mode On-chip ROM disabled extended mode Modes other than on-chip ROM disabled extended mode Note: * I/O Port Module Name Bus controller Pin Function A17 output A17_OE I/O Port PF1DDR Bus controller I/O port A17 output* PF1 output PF1 input (initial setting) 1 0 0 1 0 Valid in external extended mode (EXPE = 1) (8) PF0/A16 The pin function is switched as shown below according to the combination of operating mode, the EXPE bit, port function control register (PFCR), and the PF0DDR bit settings. Setting MCU Operating Mode On-chip ROM disabled extended mode Modes other than on-chip ROM disabled extended mode Note: * I/O Port Module Name Bus controller Pin Function A16 output A16_OE I/O Port PF0DDR Bus controller I/O port A16 output* PF0 output PF0 input (initial setting) 1 0 0 1 0 Valid in external extended mode (EXPE = 1) Rev.1.00 Jun. 07, 2006 Page 471 of 1102 REJ09B0294-0100 Section 9 I/O Ports 9.2.12 (1) Port H PH7/D7, PH6/D6, PH5/D5, PH4/D4, PH3/D3, PH2/D2, PH1/D1, PH0/D0 The pin function is switched as shown below according to the combination of operating mode, the EXPE bit, and the PHnDDR bit settings. Setting MCU Operating Mode Module Name Bus controller I/O port Pin Function Data I/O* (initial setting E) PHn output PHn input (initial setting S) EXPE 1 0 0 I/O Port PHnDDR 1 0 [Legend] Initial setting E: Initial setting in external extended mode Initial setting S: Initial setting in single-chip mode n: 0 to 7 Note: * Valid in external extended mode (EXPE = 1) Rev.1.00 Jun. 07, 2006 Page 472 of 1102 REJ09B0294-0100 Section 9 I/O Ports 9.2.13 (1) Port I PI7/D15, PI6/D14, PI5/D13, PI4/D12, PI3/D11, PI2/D10, PI1/D9, PI0/D8 The pin function is switched as shown below according to the combination of operating mode, bus mode, the EXPE bit, and the PInDDR bit settings. Setting Bus Controller Module Name Bus controller I/O port Pin Function Data I/O* (initial setting E) PIn output PIn input (initial setting S) 16-Bit Bus Mode 1 0 0 I/O Port PInDDR 1 0 [Legend] Initial setting E: Initial setting in external extended mode Initial setting S: Initial setting in single-chip mode n: 0 to 7 Note: * Valid in external extended mode (EXPE = 1) Rev.1.00 Jun. 07, 2006 Page 473 of 1102 REJ09B0294-0100 Section 9 I/O Ports 9.2.14 (1) Port M PM4 The pin function is switched as shown below according to the combination of the USB register setting and PM4DDR bit setting. Setting USB Module Name USB I/O port Pin Function PM4 output PM4 input (initial setting) PULLUP_E I/O Port PM4DDR -- 1 0 PULLUP control output 1 0 0 (2) PM3 The pin function is switched as shown below according to the combination of the PM3DDR bit setting. Setting I/O Port Module Name I/O port Pin Function PM3 output PM3 input (initial setting) PM3DDR 1 0 (3) PM2 The pin function is switched as shown below according to the combination of the PM2DDR bit setting. Setting I/O Port Module Name I/O port Pin Function PM2 output PM2 input (initial setting) PM2DDR 1 0 Rev.1.00 Jun. 07, 2006 Page 474 of 1102 REJ09B0294-0100 Section 9 I/O Ports (4) PM1/RxD6 The pin function is switched as shown below according to the combination of the PM1DDR bit setting. Setting I/O Port Module Name I/O port Pin Function PM1 output PM1 input (initial setting) PM1DDR 1 0 (5) PM0/TxD6 The pin function is switched as shown below according to the combination of the SCI register setting and PM0DDR bit setting. Setting SCI Module Name SCI I/O port Pin Function TxD6 output PM0 output PM0 input (initial setting) TxD6_OE 1 0 0 I/O Port PM0DDR -- 1 0 Rev.1.00 Jun. 07, 2006 Page 475 of 1102 REJ09B0294-0100 Section 9 I/O Ports Table 9.5 Available Output Signals and Settings in Each Port Output Specification Signal Name Output Signal Name SCL0 DACK1 SDA0 TEND1 SCL1 TxD5 IrTxD5 SDA1 -- DACK0 SCK2 -- Signal Selection Register Settings Port P1 7 6 Peripheral Module Settings ICCRA.ICE = 1 SCL0_OE DACK1A_OE SDA0_OE PFCR7.DMAS1[A,B] = 00 DACR.AMS = 1, DMDR.DACKE = 1 ICCRA.ICE = 1 PFCR7.DMAS1[A,B] = 00 DMDR.TENDE = 1 ICCRA.ICE = 1 SCR.TE = 1, IrCR.IrE = 0 SCR.TE = 1, IrCR.IrE = 1 ICCRA.ICE = 1 -- 5 TEND1A_OE SCL1_OE 4 TxD5_OE IrTxD5_OE SDA1_OE 3 2 -- DACK0A_OE SCK2_OE PFCR7.DMAS0[A,B] = 00 DACR.AMS = 1, DMDR.DACKE = 1 When SCMR.SMIF = 1: SCR.TE = 1 or SCR.RE = 1 while SMR.GM = 0, SCR.CKE [1, 0] = 01 or while SMR.GM = 1 When SCMR.SMIF = 0: SCR.TE = 1 or SCR.RE = 1 while SMR.C/A = 0, SCR.CKE [1, 0] = 01 or while SMR.C/A = 1, SCR.CKE 1 = 0 PFCR7.DMAS0[A,B] = 00 DMDR.TENDE = 1 SCR.TE = 1 TPU.TIOR5.IOB3 = 0, TPU.TIOR5.IOB[1,0] = 01/10/11 NDERL.NDER7 = 1 TPU.TIOR5.IOA3 = 0, TPU.TIOR5.IOA[1,0] = 01/10/11 TCSR.OS3,2 = 01/10/11 or TCSR.OS[1,0] = 01/10/11 SCR.TE = 1 NDERL.NDER6 = 1 TPU.TIOR4.IOA3 = 0, TPU.TIOR4.IOA[1,0] = 01/10/11 NDERL.NDER5 = 1 1 0 P2 7 TEND0A_OE TxD2_OE TIOCB5_OE PO7_OE TEND0 TxD2 TIOCB5 PO7 TIOCA5 TMO1 TxD1 PO6 TIOCA4 PO5 6 TIOCA5_OE TMO1_OE TxD1_OE PO6_OE 5 TIOCA4_OE PO5_OE Rev.1.00 Jun. 07, 2006 Page 476 of 1102 REJ09B0294-0100 Section 9 I/O Ports Output Specification Signal Name 4 TIOCB4_OE SCK1_OE Output Signal Name TIOCB4 SCK1 Port P2 Signal Selection Register Settings Peripheral Module Settings TPU.TIOR4.IOB3 = 0, TPU.TIOR4.IOB[1,0] = 01/10/11 When SCMR.SMIF = 1: SCR.TE = 1 or SCR.RE = 1 while SMR.GM = 0, SCR.CKE [1, 0] = 01 or while SMR.GM = 1 When SCMR.SMIF = 0: SCR.TE = 1 or SCR.RE = 1 while SMR.C/A = 0, SCR.CKE [1, 0] = 01 or while SMR.C/A = 1, SCR.CKE 1 = 0 NDERL.NDER4 = 1 TPU.TMDR.BFB = 0, TPU.TIORL3.IOD3 = 0, TPU.TIORL3.IOD[1,0] = 01/10/11 NDERL.NDER3 = 1 TPU.TMDR.BFA = 0, TPU.TIORL3.IOC3 = 0, TPU.TIORL3.IOD[1,0] = 01/10/11 TCSR.OS[3,2] = 01/10/11 or TCSR.OS[1,0] = 01/10/11 SCR.TE = 1 NDERL.NDER2 = 1 TPU.TIORH3.IOA3 = 0, TPU.TIORH3.IOA[1,0] = 01/10/11 NDERL.NDER1 = 1 TPU.TIORH3.IOB3 = 0, TPU.TIORH3.IOB[1,0] = 01/10/11 When SCMR.SMIF = 1: SCR.TE = 1 or SCR.RE = 1 while SMR.GM = 0, SCR.CKE [1, 0] = 01 or while SMR.GM = 1 When SCMR.SMIF = 0: SCR.TE = 1 or SCR.RE = 1 while SMR.C/A = 0, SCR.CKE [1, 0] = 01 or while SMR.C/A = 1, SCR.CKE 1 = 0 NDERL.NDER0 = 1 PO4_OE 3 TIOCD3_OE PO4 TIOCD3 PO3_OE 2 TIOCC3_OE PO3 TIOCC3 TMO0_OE TxD0_OE PO2_OE 1 TIOCA3_OE PO1_OE 0 TIOCB3_OE SCK0_OE TMO0 TxD0 PO2 TIOCA3 PO1 TIOCB3 SCK0 PO0_OE PO0 Rev.1.00 Jun. 07, 2006 Page 477 of 1102 REJ09B0294-0100 Section 9 I/O Ports Output Specification Signal Name 7 TIOCB2_OE PO15_OE 6 TIOCA2_OE PO14_OE 5 DACK1B_OE TIOCB1_OE PO13_OE 4 TEND1B_OE TIOCA1_OE PO12_OE 3 TIOCD0_OE Output Signal Name TIOCB2 PO15 TIOCA2 PO14 DACK1 TIOCB1 PO13 TEND1 TIOCA1 PO12 TIOCD0 Port P3 Signal Selection Register Settings Peripheral Module Settings TPU.TIOR2.IOB3 = 0, TPU.TIOR2.IOB[1,0] = 01/10/11 NDERH.NDER15 = 1 TPU.TIOR2.IOA3 = 0, TPU.TIOR2.IOA[1,0] = 01/10/11 NDERH.NDER14 = 1 PFCR7.DMAS1[A,B] = 01 DACR.AMS = 1,DMDR.DACKE = 1 TPU.TIOR1.IOB3 = 0, TPU.TIOR1.IOB[1,0] = 01/10/11 NDERH.NDER13 = 1 PFCR7.DMAS1[A,B] = 01 DMDR.TENDE = 1 TPU.TIOR1.IOA3 = 0, TPU.TIOR1.IOA[1,0] = 01/10/11 NDERH.NDER12 = 1 TPU.TMDR.BFB = 0, TPU.TIORL0.IOD3 = 0, TPU.TIORL0.IOD[1,0] = 01/10/11 NDERH.NDER11 = 1 PFCR7.DMAS0[A,B] = 01 DACR.AMS = 1,DMDR.DACKE = 1 TPU.TMDR.BFA = 0, TPU.TIORL0.IOC3 = 0, TPU.TIORL0.IOD[1,0] = 01/10/11 NDERH.NDER10 = 1 PFCR7.DMAS0[A,B] = 01 DMDR.TENDE = 1 TPU.TIORH0.IOB3 = 0, TPU.TIORH0.IOB[1,0] = 01/10/11 NDERH.NDER9 = 1 TPU.TIORH0.IOA3 = 0, TPU.TIOH0.IOA[1,0] = 01/10/11 NDERH.NDER8 = 1 PO11_OE 2 DACK0B_OE TIOCC0_OE PO11 DACK0 TIOCC0 PO10_OE 1 TEND0B_OE TIOCB0_OE PO9_OE 0 TIOCA0_OE PO8_OE PO10 TEND0 TIOCB0 PO9 TIOCA0 PO8 Rev.1.00 Jun. 07, 2006 Page 478 of 1102 REJ09B0294-0100 Section 9 I/O Ports Output Specification Signal Name 5 DACK3_OE TMO3_OE 4 2 TEND3_OE DACK2_OE TMO2_OE SCK4_OE Output Signal Name DACK3 TMO3 TEND3 DACK2 TMO2 SCK4 Port P6 Signal Selection Register Settings Peripheral Module Settings PFCR7.DMAS3[A,B] = 01 DACR.AMS = 1, DMDR.DACKE = 1 TCSR.OS[3,2] = 01/10/11 or TCSR.OS[1,0] = 01/10/11 PFCR7.DMAS3[A,B] = 01 DMDR.TENDE = 1 PFCR7.DMAS2[A,B] = 01 DACR.AMS = 1, DMDR.DACKE = 1 TCSR.OS[3,2] = 01/10/11 or TCSR.OS[1,0] = 01/10/11 When SCMR.SMIF = 1: SCR.TE = 1 or SCR.RE = 1 while SMR.GM = 0, SCR.CKE [1, 0] = 01 or while SMR.GM = 1 When SCMR.SMIF = 0: SCR.TE = 1 or SCR.RE = 1 while SMR.C/A = 0, SCR.CKE [1, 0] = 01 or while SMR.C/A = 1, SCR.CKE 1 = 0 PFCR7.DMAS2[A,B] = 01 DMDR.TENDE = 1 SCR.TE = 1 PADDR.PA7DDR = 1, SCKCR.POSEL1 = 0 SYSCR.EXPE = 1, MPXCR.MPXEn (n = 7 to 3) = 1 PFCR2.BSS = 1 SYSCR.EXPE = 1, PFCR2.BSE = 1 SYSCR.EXPE = 1, PFCR2.ASOE = 1 SYSCR.EXPE = 1 SYSCR.EXPE = 1, PFCR6.LHWROE = 1 or SRAMCR.BCSELn = 1 SYSCR.EXPE = 1, PFCR6.LHWROE = 1 SYSCR.EXPE = 1, SRAMCR.BCSELn = 1 SYSCR.EXPE = 1 SYSCR.EXPE = 1,BCR1.BRLE = 1 SYSCR.EXPE = 1, PFCR2.REWRE = 1 or SRAMCR.BCSELn = 1 PFCR2.BSS = 0 SYSCR.EXPE = 1, PFCR2.BSE = 1 SYSCR.EXPE = 1, BCR1.BRLE = 1, BCR1.BREQOE = 1 1 0 PA 7 6 TEND2_OE TxD4_OE B_OE AH_OE BSB_OE AS_OE TEND2 TxD4 B AH BS AS RD LUB LHWR LLB LLWR BACK RD/WR BS BREQO 5 4 RD_OE LUB_OE LHWR_OE 3 LLB_OE LLWR_OE 1 BACK_OE (RD/WR)_OE 0 BSA_OE BREQO_OE Rev.1.00 Jun. 07, 2006 Page 479 of 1102 REJ09B0294-0100 Section 9 I/O Ports Output Specification Signal Name 7 6 SD_OE (RD/WR)-B_OE Port PB Output Signal Name SD RD/WR CS6 CKE OE CS5 WE CS4 CAS CS3 CS7 RAS CS2 CS6 CS1 CS2 CS5 CS6 CS7 CS0 CS4 CS5 Signal Selection Register Settings Peripheral Module Settings MDCR.MDS7 = 1 PFCR2.RDWRS = 1 PFCR1.CS6S[A,B] = 11 SYSCR.EXPE=1, PFCR2.REWRE = 1 or ASRAMCR.BCSELn = 1 SYSCR.EXPE = 1, PFCR0.CS6E = 1 SYSCR.EXPE = 1, DRAMCR.DRAME = 1, DRAMCR.DTYPE = 1, DRAMCR.OEE = 1 SYSCR.EXPE = 1, DRAMCR.DRAME = 1, DRAMCR.DTYPE = 0, DRAMCR.OEE = 1 CS6D_OE 5 CKE_OE OE_OE CS5D_OE 4 WE_OE CS4B_OE 3 CAS_OE CS3A_OE CS7A_OE 2 RAS_OE CS2A_OE CS6A_OE 1 CS1_OE CS2B_OE CS5A_OE CS6B_OE CS7B_OE 0 CS0_OE CS4_OE CS5B_OE PFCR1.CS5S[A,B] = 11 SYSCR.EXPE = 1, PFCR0.CS5E = 1 SYSCR.EXPE = 1, DRAMCR.DRAME = 1 PFCR1.CS4S[A,B] = 01 SYSCR.EXPE = 1, PFCR0.CS4E = 1 SYSCR.EXPE = 1, DRAMCR.DRAME = 1, DRAMCR.DTYPE = 1 PFCR2.CS3S = 0 PFCR1.CS7S[A,B] = 00 SYSCR.EXPE = 1, PFCR0.CS3E = 1 SYSCR.EXPE = 1, PFCR0.CS7E = 1 SYSCR.EXPE = 1, DRAMCR.DRAME = 1 PFCR2.CS2S = 0 PFCR1.CS6S[A,B] = 00 SYSCR.EXPE = 1, PFCR0.CS2E = 1 SYSCR.EXPE = 1, PFCR0.CS6E = 1 SYSCR.EXPE = 1, PFCR0.CS1E = 1 PFCR2.CS2S = 1 PFCR1.CS5S[A,B] = 00 PFCR1.CS6S[A,B] = 01 PFCR1.CS7S[A,B] = 01 SYSCR.EXPE = 1, PFCR0.CS2E = 1 SYSCR.EXPE = 1, PFCR0.CS5E = 1 SYSCR.EXPE = 1, PFCR0.CS6E = 1 SYSCR.EXPE = 1, PFCR0.CS7E = 1 SYSCR.EXPE = 1, PFCR0.CS0E = 1 SYSCR.EXPE = 1, PFCR0.CS4E = 1 PFCR1.CS5S[A,B] = 01 SYSCR.EXPE = 1, PFCR0.CS5E = 1 Rev.1.00 Jun. 07, 2006 Page 480 of 1102 REJ09B0294-0100 Section 9 I/O Ports Output Specification Signal Name 3 LLCAS_OE DQMLL_OE 2 LUCAS_OE Output Signal Name LLCAS DQMLL LUCAS Port PC Signal Selection Register Settings Peripheral Module Settings SYSCR.EXPE = 1, DRAMCR.DRAME = 1, DRAMCR.DTYPE = 0 SYSCR.EXPE = 1, DRAMCR.DRAME = 1, DRAMCR.DTYPE = 1 SYSCR.EXPE = 1, ABWCR.[ABWH2,ABWL2] = x0/01, DRAMCR.DRAME = 1, DRAMCR.DTYPE = 0 SYSCR.EXPE = 1, ABWCR.[ABWH2,ABWL2] = x0/01, DRAMCR.DRAME = 1, DRAMCR.DTYPE = 1 SYSCR.EXPE = 1, PDDDR.PD7DDR = 1 SYSCR.EXPE = 1, PDDDR.PD6DDR = 1 SYSCR.EXPE = 1, PDDDR.PD5DDR = 1 SYSCR.EXPE = 1, PDDDR.PD4DDR = 1 SYSCR.EXPE = 1, PDDDR.PD3DDR = 1 SYSCR.EXPE = 1, PDDDR.PD2DDR = 1 SYSCR.EXPE = 1, PDDDR.PD1DDR = 1 SYSCR.EXPE = 1, PDDDR.PD0DDR = 1 SYSCR.EXPE = 1, PDDDR.PE7DDR = 1 SYSCR.EXPE = 1, PDDDR.PE6DDR = 1 SYSCR.EXPE = 1, PDDDR.PE5DDR = 1 SYSCR.EXPE = 1, PDDDR.PE4DDR = 1 SYSCR.EXPE = 1, PDDDR.PE3DDR = 1 SYSCR.EXPE = 1, PDDDR.PE2DDR = 1 SYSCR.EXPE = 1, PDDDR.PE1DDR = 1 SYSCR.EXPE = 1, PDDDR.PE0DDR = 1 DQMLU_OE DQMLU PD 7 6 5 4 3 2 1 0 A7_OE A6_OE A5_OE A4_OE A3_OE A2_OE A1_OE A0_OE A15_OE A14_OE A13_OE A12_OE A11_OE A10_OE A9_OE A8_OE A7 A6 A5 A4 A3 A2 A1 A0 A15 A14 A13 A12 A11 A10 A9 A8 PE 7 6 5 4 3 2 1 0 Rev.1.00 Jun. 07, 2006 Page 481 of 1102 REJ09B0294-0100 Section 9 I/O Ports Output Specification Signal Name 7 6 5 4 3 2 1 0 PH 7 6 5 4 3 2 1 0 PI 7 6 5 4 3 2 1 0 PM 4 3 2 1 0 A23_OE A22_OE A21_OE A20_OE A19_OE A18_OE A17_OE A16_OE D7_E D6_E D5_E D4_E D3_E D2_E D1_E D0_E D15_E D14_E D13_E D12_E D11_E D10_E D9_E D8_E -- -- -- -- TxD6_OE Output Signal Name A23 A22 A21 A20 A19 A18 A17 A16 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 -- -- -- -- TxD6 -- -- -- -- Port PF Signal Selection Register Settings Peripheral Module Settings SYSCR.EXPE = 1, PFCR4.A23E = 1 SYSCR.EXPE = 1, PFCR4.A22E = 1 SYSCR.EXPE = 1, PFCR4.A21E = 1 SYSCR.EXPE = 1, PFCR4.A20E = 1 SYSCR.EXPE = 1, PFCR4.A19E = 1 SYSCR.EXPE = 1, PFCR4.A18E = 1 SYSCR.EXPE = 1, PFCR4.A17E = 1 SYSCR.EXPE = 1, PFCR4.A16E = 1 SYSCR.EXPE = 1 SYSCR.EXPE = 1 SYSCR.EXPE = 1 SYSCR.EXPE = 1 SYSCR.EXPE = 1 SYSCR.EXPE = 1 SYSCR.EXPE = 1 SYSCR.EXPE = 1 SYSCR.EXPE = 1, ABWCR.ABW[H,L]n = 01 SYSCR.EXPE = 1, ABWCR.ABW[H,L]n = 01 SYSCR.EXPE = 1, ABWCR.ABW[H,L]n = 01 SYSCR.EXPE = 1, ABWCR.ABW[H,L]n = 01 SYSCR.EXPE = 1, ABWCR.ABW[H,L]n = 01 SYSCR.EXPE = 1, ABWCR.ABW[H,L]n = 01 SYSCR.EXPE = 1, ABWCR.ABW[H,L]n = 01 SYSCR.EXPE = 1, ABWCR.ABW[H,L]n = 01 -- -- -- -- SCR.TE = 1 Rev.1.00 Jun. 07, 2006 Page 482 of 1102 REJ09B0294-0100 Section 9 I/O Ports 9.3 Port Function Controller The port function controller controls the I/O ports. The port function controller incorporates the following registers. * Port function control register 0 (PFCR0) * Port function control register 1 (PFCR1) * Port function control register 2 (PFCR2) * Port function control register 4 (PFCR4) * Port function control register 6 (PFCR6) * Port function control register 7 (PFCR7) * Port function control register 9 (PFCR9) * Port function control register B (PFCRB) * Port function control register C (PFCRC) 9.3.1 Port Function Control Register 0 (PFCR0) PFCR0 enables/disables the CS output. Bit Bit Name Initial Value R/W 7 CS7E 0 R/W 6 CS6E 0 R/W 5 CS5E 0 R/W 4 CS4E 0 R/W 3 CS3E 0 R/W 2 CS2E 0 R/W 1 CS1E 0 R/W 0 CS0E Undefined* R/W Note: * 1 in external extended mode; 0 in other modes. Bit 7 6 5 4 3 2 1 0 Note: * Bit Name CS7E CS6E CS5E CS4E CS3E CS2E CS1E CS0E Initial Value 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W Description CS7 to CS0 Enable These bits enable/disable the corresponding CSn output. 0: Pin functions as I/O port 1: Pin functions as CSn output pin (n = 7 to 0) 0 R/W Undefined* R/W 1 in external extended mode, 0 in other modes. Rev.1.00 Jun. 07, 2006 Page 483 of 1102 REJ09B0294-0100 Section 9 I/O Ports 9.3.2 Port Function Control Register 1 (PFCR1) PFCR1 selects the CS output pins. Bit Bit Name Initial Value R/W 7 CS7SA 0 R/W 6 CS7SB 0 R/W 5 CS6SA 0 R/W 4 CS6SB 0 R/W 3 CS5SA 0 R/W 2 CS5SB 0 R/W 1 CS4SA 0 R/W 0 CS4SB 0 R/W Bit 7 6 Bit Name CS7SA* CS7SB* Initial Value 0 0 R/W R/W R/W Description CS7 Output Pin Select Selects the output pin for CS7 when CS7 output is enabled (CS7E = 1) 00: Specifies pin PB3 as CS7-A output 01: Specifies pin PB1 as CS7-B output 10: Setting prohibited 11: Setting prohibited 5 4 CS6SA* CS6SB* 0 0 R/W R/W CS6 Output Pin Select Selects the output pin for CS6 when CS6 output is enabled (CS6E = 1) 00: Specifies pin PB2 as CS6-A output 01: Specifies pin PB1 as CS6-B output 10: Setting prohibited 11: Specifies pin PB6 as CS6-D output 3 2 CS5SA* CS5SB* 0 0 R/W R/W CS5 Output Pin Select Selects the output pin for CS5 when CS5 output is enabled (CS5E = 1) 00: Specifies pin PB1 as CS5-A output 01: Specifies pin PB0 as CS5-B output 10: Setting prohibited 11: Specifies pin PB5 as CS5-D output Rev.1.00 Jun. 07, 2006 Page 484 of 1102 REJ09B0294-0100 Section 9 I/O Ports Bit 1 0 Bit Name CS4SA* CS4SB* Initial Value 0 0 R/W R/W R/W Description CS4 Output Pin Select Selects the output pin for CS4 when CS4 output is enabled (CS4E = 1) 00: Specifies pin PB1 as CS4-A output 01: Specifies pin PB0 as CS4-B output 10: Setting prohibited 11: Setting prohibited Note: * If multiple CS outputs are specified to a single pin according to the CSn output pin select bits (n = 4 to 7), multiple CS signals are output from the pin. For details, see section 6.5.3, Chip Select Signals. 9.3.3 Port Function Control Register 2 (PFCR2) PFCR2 selects the CS output pin, enables/disables bus control I/O, and selects the bus control I/O pins. Bit Bit Name Initial Value R/W 7 0 R 6 CS2S 0 R/W 5 BSS 0 R/W 4 BSE 0 R/W 3 RDWRS 0 R/W 2 RDWRE 0 R/W 1 ASOE 1 R/W 0 0 R Bit 7 Bit Name Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 6 CS2S* 1 0 R/W CS2 Output Pin Select Selects the output pin for CS2 when CS2 output is enabled (CS2E = 1) 0: Specifies pin PB2 as CS2-A output pin 1: Specifies pin PB1 as CS2-B output pin Rev.1.00 Jun. 07, 2006 Page 485 of 1102 REJ09B0294-0100 Section 9 I/O Ports Bit 5 Bit Name BSS Initial Value 0 R/W R/W Description BS Output Pin Select Selects the BS output pin 0: Specifies pin PA0 as BS-A output pin 1: Specifies pin PA6 as BS-B output pin 4 BSE 0 R/W BS Output Enable Enables/disables the BS output 0: Disables the BS output 1: Enables the BS output 3 RDWRS* 2 0 R/W RD/WR Output Pin Select Selects the output pin for RD/WR 0: Specifies pin PA1 as RD/WR-A output pin 1: Specifies pin PB6 as RD/WR-B output pin 2 RDWRE* 2 0 R/W RD/WR Output Enable Enables/disables the RD/WR output 0: Disables the RD/WR output 1: Enables the RD/WR output 1 ASOE 1 R/W AS Output Enable Enables/disables the AS output 0: Specifies pin PA6 as I/O port 1: Specifies pin PA6 as AS output pin 0 0 R Reserved This bit is always read as 0. The write value should always be 0. Notes: 1. If multiple CS outputs are specified to a single pin according to the CSn output pin select bit (n = 2), multiple CS signals are output from the pin. For details, see section 6.5.3, Chip Select Signals. 2. If an area is specified as a byte control SDRAM space, the pin functions as RD/WR output regardless of the RDWRE bit value. Rev.1.00 Jun. 07, 2006 Page 486 of 1102 REJ09B0294-0100 Section 9 I/O Ports 9.3.4 Port Function Control Register 4 (PFCR4) PFCR4 enables/disables the address output. Bit Bit Name Initial Value R/W 7 A23E 0 R/W 6 A22E 0 R/W 5 A21E 0 R/W 4 A20E 0/1* R/W 3 A19E 0/1* R/W 2 A18E 0/1* R/W 1 A17E 0/1* R/W 0 A16E 0/1* R/W Bit 7 Bit Name A23E Initial Value 0 R/W R/W Description Address A23 Enable Enables/disables the address output (A23) 0: Disables the A23 output 1: Enables the A23 output 6 A22E 0 R/W Address A22 Enable Enables/disables the address output (A22) 0: Disables the A22 output 1: Enables the A22 output 5 A21E 0 R/W Address A21 Enable Enables/disables the address output (A21) 0: Disables the A21 output 1: Enables the A21 output 4 A20E 0/1* R/W Address A20 Enable Enables/disables the address output (A20) 0: Disables the A20 output 1: Enables the A20 output 3 A19E 0/1* R/W Address A19 Enable Enables/disables the address output (A19) 0: Disables the A19 output 1: Enables the A19 output Rev.1.00 Jun. 07, 2006 Page 487 of 1102 REJ09B0294-0100 Section 9 I/O Ports Bit 2 Bit Name A18E Initial Value 0/1* R/W R/W Description Address A18 Enable Enables/disables the address output (A18) 0: Disables the A18 output 1: Enables the A18 output 1 A17E 0/1* R/W Address A17 Enable Enables/disables the address output (A17) 0: Disables the A17 output 1: Enables the A17 output 0 A16E 0/1* R/W Address A16 Enable Enables/disables the address output (A16) 0: Disables the A16 output 1: Enables the A16 output Note: * When external extended mode: When other modes: Initial value is 1, reserved. This bit is always read as 1. The write value should always be 1. Initial value is 1, enable setting. Rev.1.00 Jun. 07, 2006 Page 488 of 1102 REJ09B0294-0100 Section 9 I/O Ports 9.3.5 Port Function Control Register 6 (PFCR6) PFCR6 selects the TPU clock input pin. Bit Bit Name Initial Value R/W 7 1 R/W 6 LHWROE 1 R/W 5 1 R/W 4 0 R 3 TCLKS 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Bit 7 Bit Name Initial Value 1 R/W R/W Description Reserved This bit is always read as 1. The write value should always be 1. 6 LHWROE 1 R/W LHWR Output Enable Enables/disables LHWR output (valid in external extended mode). 0: Specifies pin PA4 as I/O port 1: Specifies pin PA4 as LHWR output pin 5 1 R/W Reserved This bit is always read as 1. The write value should always be 1. 4 3 TCLKS 0 0 R R/W Reserved This is a read-only bit and cannot be modified. TPU External Clock Input Pin Select Selects the TPU external clock input pins. 0: Specifies pins P32, P33, P35, and P37 as external clock input pins. 1: Specifies pins P14 to P17 as external clock input pins. 2 to 0 All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. Rev.1.00 Jun. 07, 2006 Page 489 of 1102 REJ09B0294-0100 Section 9 I/O Ports 9.3.6 Port Function Control Register 7 (PFCR7) PFCR7 selects the DMAC I/O pins (DREQ, DACK, and TEND). Bit Bit Name Initial Value R/W 7 DMAS3A 0 R/W 6 DMAS3B 0 R/W 5 DMAS2A 0 R/W 4 DMAS2B 0 R/W 3 DMAS1A 0 R/W 2 DMAS1B 0 R/W 1 DMAS0A 0 R/W 0 DMAS0B 0 R/W Bit 7 6 Bit Name DMAS3A DMAS3B Initial Value 0 0 R/W R/W R/W Description DMAC control pin select Selects the I/O port to control DMAC_3. 00: Setting prohibited 01: Specifies pins P63 to P65 as DMAC control pins 10: Setting prohibited 11: Setting prohibited 5 4 DMAS2A DMAS2B 0 0 R/W R/W DMAC control pin select Selects the I/O port to control DMAC_2. 00: Setting prohibited 01: Specifies pins P60 to P62 as DMAC control pins 10: Setting prohibited 11: Setting prohibited 3 2 DMAS1A DMAS1B 0 0 R/W R/W DMAC control pin select Selects the I/O port to control DMAC_1. 00: Specifies pins P14 to P16 as DMAC control pins 01: Specifies pins P33 to P35 as DMAC control pins 10: Setting prohibited 11: Setting prohibited 1 0 DMAS0A DMAS0B 0 0 R/W R/W DMAC control pin select Selects the I/O port to control DMAC_0. 00: Specifies pins P10 to P12 as DMAC control pins 01: Specifies pins P30 to P32 as DMAC control pins 10: Setting prohibited 11: Setting prohibited Rev.1.00 Jun. 07, 2006 Page 490 of 1102 REJ09B0294-0100 Section 9 I/O Ports 9.3.7 Port Function Control Register 9 (PFCR9) PFCR9 selects the multiple functions for the TPU I/O pins. Bit Bit Name Initial Value R/W 7 TPUMS5 0 R/W 6 TPUMS4 0 R/W 5 TPUMS3A 0 R/W 4 TPUMS3B 0 R/W 3 TPUMS2 0 R/W 2 TPUMS1 0 R/W 1 TPUMS0A 0 R/W 0 TPUMS0B 0 R/W Bit 7 Bit Name TPUMS5 Initial Value 0 R/W R/W Description TPU I/O Pin Multiplex Function Select Selects TIOCA5 function 0: Specifies pin P26 as output compare output and input capture 1: Specifies P27 as input capture input and P26 as output compare 6 TPUMS4 0 R/W TPU I/O Pin Multiplex Function Select Selects TIOCA4 function 0: Specifies P25 as output compare output and input capture 1: Specifies P24 as input capture input and P25 as output compare 5 TPUMS3A 0 R/W TPU I/O Pin Multiplex Function Select Selects TIOCA3 function 0: Specifies P21 as output compare output and input capture 1: Specifies P20 as input capture input and P21 as output compare 4 TPUMS3B 0 R/W TPU I/O Pin Multiplex Function Select Selects TIOCC3 function 0: Specifies P22 as output compare output and input capture 1: Specifies P23 as input capture input and P22 as output compare Rev.1.00 Jun. 07, 2006 Page 491 of 1102 REJ09B0294-0100 Section 9 I/O Ports Bit 3 Bit Name TPUMS2 Initial Value 0 R/W R/W Description TPU I/O Pin Multiplex Function Select Selects TIOCA2 function 0: Specifies P36 as output compare output and input capture 1: Specifies P37 as input capture input and P36 as output compare 2 TPUMS1 0 R/W TPU I/O Pin Multiplex Function Select Selects TIOCA1 function 0: Specifies P34 as output compare output and input capture 1: Specifies P35 as input capture input and P34 as output compare 1 TPUMS0A 0 R/W TPU I/O Pin Multiplex Function Select Selects TIOCA0 function 0: Specifies P30 as output compare output and input capture 1: Specifies P31 as input capture input and P30 as output compare 0 TPUMS0B 0 R/W TPU I/O Pin Multiplex Function Select Selects TIOCC0 function 0: Specifies P32 as output compare output and input capture 1: Specifies P33 as input capture input and P32 as output compare Rev.1.00 Jun. 07, 2006 Page 492 of 1102 REJ09B0294-0100 Section 9 I/O Ports 9.3.8 Port Function Control Register B (PFCRB) PFCRB selects the input pins for IRQ11 to IRQ8. Bit Bit Name Initial Value R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 ITS11 0 R/W 2 ITS10 0 R/W 1 ITS9 0 R/W 0 ITS8 0 R/W Bit 7 to 4 Bit Name Initial Value All 0 R/W R/W Description Reserved These bits are always read as 0. The write value should always be 0. 3 ITS11 0 R/W IRQ11 Pin Select Selects an input pin for IRQ11. 0: Selects pin P23 as IRQ11-A input 1: Selects pin P63 as IRQ11-B input 2 ITS10 0 R/W IRQ10 Pin Select Selects an input pin for IRQ10. 0: Selects pin P22 as IRQ10-A input 1: Selects pin P62 as IRQ10-B input 1 ITS9 0 R/W IRQ9 Pin Select Selects an input pin for IRQ9. 0: Selects pin P21 as IRQ9-A input 1: Selects pin P61 as IRQ9-B input 0 ITS8 0 R/W IRQ8 Pin Select Selects an input pin for IRQ8. 0: Selects pin P20 as IRQ8-A input 1: Selects pin P60 as IRQ8-B input Rev.1.00 Jun. 07, 2006 Page 493 of 1102 REJ09B0294-0100 Section 9 I/O Ports 9.3.9 Port Function Control Register C (PFCRC) PFCRC selects input pins for IRQ7 to IRQ0. Bit Bit Name Initial Value R/W 7 ITS7 0 R/W 6 ITS6 0 R/W 5 ITS5 0 R/W 4 ITS4 0 R/W 3 ITS3 0 R/W 2 ITS2 0 R/W 1 ITS1 0 R/W 0 ITS0 0 R/W Bit 7 Bit Name ITS7 Initial Value 0 R/W R/W Description IRQ7 Pin Select Selects an input pin for IRQ7. 0: Selects pin P17 as IRQ7-A input 1: Selects pin P57 as IRQ7-B input 6 ITS6 0 R/W IRQ6 Pin Select Selects an input pin for IRQ6. 0: Selects pin P16 as IRQ6-A input 1: Selects pin P56 as IRQ6-B input 5 ITS5 0 R/W IRQ5 Pin Select Selects an input pin for IRQ5. 0: Selects pin P15 as IRQ5-A input 1: Selects pin P55 as IRQ5-B input 4 ITS4 0 R/W IRQ4 Pin Select Selects an input pin for IRQ4. 0: Selects pin P14 as IRQ4-A input 1: Selects pin P54 as IRQ4-B input 3 ITS3 0 R/W IRQ3 Pin Select Selects an input pin for IRQ3. 0: Selects pin P13 as IRQ3-A input 1: Selects pin P53 as IRQ3-B input Rev.1.00 Jun. 07, 2006 Page 494 of 1102 REJ09B0294-0100 Section 9 I/O Ports Bit 2 Bit Name ITS2 Initial Value 0 R/W R/W Description IRQ2 Pin Select Selects an input pin for IRQ2. 0: Selects pin P12 as IRQ2-A input 1: Selects pin P52 as IRQ2-B input 1 ITS1 0 R/W IRQ1 Pin Select Selects an input pin for IRQ1. 0: Selects pin P11 as IRQ1-A input 1: Selects pin P51 as IRQ1-B input 0 ITS0 0 R/W IRQ0 Pin Select Selects an input pin for IRQ0. 0: Selects pin P10 as IRQ0-A input 1: Selects pin P50 as IRQ0-B input Rev.1.00 Jun. 07, 2006 Page 495 of 1102 REJ09B0294-0100 Section 9 I/O Ports 9.4 9.4.1 Usage Notes Notes on Input Buffer Control Register (ICR) Setting 1. When the ICR setting is changed, the LSI may malfunction due to an edge occurred internally according to the pin state. Before changing the ICR setting, fix the pin state high or disable the input function corresponding to the pin by the on-chip peripheral module settings. 2. If an input is enabled by setting ICR while multiple input functions are assigned to the pin, the pin state is reflected in all the inputs. Care must be taken for each module settings for unused input functions. 3. When a pin is used as an output, data to be output from the pin will be latched as the pin state if the input function corresponding to the pin is enabled. To use the pin as an output, disable the input function for the pin by setting ICR. 9.4.2 Notes on Port Function Control Register (PFCR) Settings 1. Port function controller controls the I/O port. Before enabling a port function, select the input/output destination. 2. When changing input pins, this LSI may malfunction due to the internal edge generated by the pin level difference before and after the change. * To change input pins, the following procedure must be performed. A. Disable the input function by the corresponding on-chip peripheral module settings B. Select another input pin by PFCR C. Enable its input function by the corresponding on-chip peripheral module settings 3. If a pin function has both a select bit that modifies the input/output destination and an enable bit that enables the pin function, first specify the input/output destination by the selection bit and then enable the pin function by the enable bit. Rev.1.00 Jun. 07, 2006 Page 496 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Section 10 16-Bit Timer Pulse Unit (TPU) This LSI has an on-chip 16-bit timer pulse unit (TPU) that comprises six 16-bit timer channels. Tables 10.1 lists the 16-bit timer unit functions and figure 10.1 is a block diagram. 10.1 Features * Maximum 16-pulse input/output * Selection of eight counter input clocks for each channel * The following operations can be set for each channel: Waveform output at compare match Input capture function Counter clear operation Synchronous operations: * Multiple timer counters (TCNT) can be written to simultaneously * Simultaneous clearing by compare match and input capture possible * Simultaneous input/output for registers possible by counter synchronous operation * Maximum of 15-phase PWM output possible by combination with synchronous operation * Buffer operation settable for channels 0 and 3 * Phase counting mode settable independently for each of channels 1, 2, 4, and 5 * Cascaded operation * Fast access via internal 16-bit bus * 26 interrupt sources * Automatic transfer of register data * Programmable pulse generator (PPG) output trigger can be generated * Conversion start trigger for the A/D converter can be generated * Module stop state specifiable Rev.1.00 Jun. 07, 2006 Page 497 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.1 TPU Functions Item Count clock Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 P/1 P/4 P/16 P/64 TCLKA TCLKB TCLKC TCLKD TGRA_0 TGRB_0 TGRC_0 TGRD_0 TIOCA0 TIOCB0 TIOCC0 TIOCD0 P/1 P/4 P/16 P/64 P/256 TCLKA TCLKB TCNT2 TGRA_1 TGRB_1 TIOCA1 TIOCB1 P/1 P/4 P/16 P/64 P/1024 TCLKA TCLKB TCLKC TGRA_2 TGRB_2 TIOCA2 TIOCB2 P/1 P/4 P/16 P/64 P/256 P/1024 P/4096 TCLKA TGRA_3 TGRB_3 TGRC_3 TGRD_3 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TGR compare match or input capture O O O O O O O TGR compare match or input capture P/1 P/4 P/16 P/64 P/1024 TCLKA TCLKC TCNT5 TGRA_4 TGRB_4 TIOCA4 TIOCB4 P/1 P/4 P/16 P/64 P/256 TCLKA TCLKC TCLKD TGRA_5 TGRB_5 TIOCA5 TIOCB5 General registers (TGR) General registers/ buffer registers I/O pins Counter clear function TGR compare match or input capture Compare 0 output match 1 output output Toggle output O O O TGR compare match or input capture O O O O O O O TGR compare match or input capture TGR compare match or input capture O O O O O O O TGR compare match or input capture TGR compare match or input capture O O O O O O O TGR compare match or input capture TGR compare match or input capture O O O O O O O TGR compare match or input capture Input capture function O Synchronous operation PWM mode O O Phase counting mode Buffer operation DTC activation O TGR compare match or input capture Rev.1.00 Jun. 07, 2006 Page 498 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Item DMAC activation Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 TGRA_0 compare match or input capture TGRA_0 compare match or input capture TGRA_0/ TGRB_0 compare match or input capture 5 sources Compare match or input capture 0A Compare match or input capture 0B TGRA_1 compare match or input capture TGRA_1 compare match or input capture TGRA_1/ TGRB_1 compare match or input capture 4 sources Compare match or input capture 1A Compare match or input capture 1B TGRA_2 compare match or input capture TGRA_2 compare match or input capture TGRA_2/ TGRB_2 compare match or input capture 4 sources Compare match or input capture 2A Compare match or input capture 2B Overflow Underflow TGRA_3 compare match or input capture TGRA_3 compare match or input capture TGRA_3/ TGRB_3 compare match or input capture 5 sources Compare match or input capture 3A Compare match or input capture 3B TGRA_4 compare match or input capture TGRA_4 compare match or input capture TGRA_5 compare match or input capture TGRA_5 compare match or input capture A/D converter trigger PPG trigger Interrupt sources 4 sources Compare match or input capture 4A Compare match or input capture 4B 4 sources Compare match or input capture 5A Compare match or input capture 5B Overflow Underflow Compare Overflow match or Underflow input capture 0C Compare match or input capture 0D Overflow [Legend] O : Possible : Not possible Compare Overflow match or Underflow input capture 3C Compare match or input capture 3D Overflow Rev.1.00 Jun. 07, 2006 Page 499 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) TIORH TIORL TMDR Channel 3 TSR TGRC TGRD TGRA TGRB TCNT Control logic for channels 3 to 5 Input/output pins TIOCA3 Channel 3: TIOCB3 TIOCC3 TIOCD3 TIOCA4 Channel 4: TIOCB4 TIOCA5 Channel 5: TIOCB5 Channel 5 TIOR TMDR Channel 2 TSR Clock input Internal clock: P/1 P/4 P/16 P/64 P/256 P/1024 P/4096 External clock: TCLKA TCLKB TCLKC TCLKD TIER TCR Module data bus TSTR TSYR TGRA Bus interface TGRB TCNT Interrupt request signals Channel 3: TGI3A TGI3B TGI3C TGI3D TCI3V Channel 4: TGI4A TGI4B TCI4V TCI4U Channel 5: TGI5A TGI5B TCI5V TCI5U TMDR Channel 4 TSR TIER TCR TGRA TIOR TMDR TSR TIER TCR TGRB TCNT Common Control logic Internal data bus A/D conversion start request signal PPG output trigger signal TIOR TIER TCR TGRA TGRB TCNT Control logic for channels 0 to 2 TIORH TIORL TMDR Input/output pins TIOCA0 Channel 0: TIOCB0 TIOCC0 TIOCD0 TIOCA1 Channel 1: TIOCB1 TIOCA2 Channel 2: TIOCB2 Interrupt request signals Channel 0: TGI0A TGI0B TGI0C TGI0D TCI0V Channel 1: TGI1A TGI1B TCI1V TCI1U Channel 2: TGI2A TGI2B TCI2V TCI2U TMDR Channel 1 TSR TIOR Channel 0 TSR TIER TCR TGRA TGRB TGRC TGRD TGRB TCNT TCNT [Legend] TSTR: TSYR: TCR: TMDR: TIOR (H, L): Timer start register Timer synchronous register Timer control register Timer mode register Timer I/O control registers (H, L) TIER: TSR: TGR (A, B, C, D): TCNT: TIER TCR Timer interrupt enable register Timer status register Timer general registers (A, B, C, D) Timer counter Figure 10.1 Block Diagram of TPU Rev.1.00 Jun. 07, 2006 Page 500 of 1102 REJ09B0294-0100 TGRA Section 10 16-Bit Timer Pulse Unit (TPU) 10.2 Input/Output Pins Table 10.2 shows TPU pin configurations. Table 10.2 Pin Configuration Channel Symbol All TCLKA TCLKB TCLKC TCLKD 0 TIOCA0 TIOCB0 TIOCC0 TIOCD0 1 TIOCA1 TIOCB1 2 TIOCA2 TIOCB2 3 TIOCA3 TIOCB3 TIOCC3 TIOCD3 4 TIOCA4 TIOCB4 5 TIOCA5 TIOCB5 I/O Function Input External clock A input pin (Channel 1 and 5 phase counting mode A phase input) Input External clock B input pin (Channel 1 and 5 phase counting mode B phase input) Input External clock C input pin (Channel 2 and 4 phase counting mode A phase input) Input External clock D input pin (Channel 2 and 4 phase counting mode B phase input) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TGRA_0 input capture input/output compare output/PWM output pin TGRB_0 input capture input/output compare output/PWM output pin TGRC_0 input capture input/output compare output/PWM output pin TGRD_0 input capture input/output compare output/PWM output pin TGRA_1 input capture input/output compare output/PWM output pin TGRB_1 input capture input/output compare output/PWM output pin TGRA_2 input capture input/output compare output/PWM output pin TGRB_2 input capture input/output compare output/PWM output pin TGRA_3 input capture input/output compare output/PWM output pin TGRB_3 input capture input/output compare output/PWM output pin TGRC_3 input capture input/output compare output/PWM output pin TGRD_3 input capture input/output compare output/PWM output pin TGRA_4 input capture input/output compare output/PWM output pin TGRB_4 input capture input/output compare output/PWM output pin TGRA_5 input capture input/output compare output/PWM output pin TGRB_5 input capture input/output compare output/PWM output pin Rev.1.00 Jun. 07, 2006 Page 501 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.3 Register Descriptions The TPU has the following registers in each channel. * Channel 0 Timer control register_0 (TCR_0) Timer mode register_0 (TMDR_0) Timer I/O control register H_0 (TIORH_0) Timer I/O control register L_0 (TIORL_0) Timer interrupt enable register_0 (TIER_0) Timer status register_0 (TSR_0) Timer counter_0 (TCNT_0) Timer general register A_0 (TGRA_0) Timer general register B_0 (TGRB_0) Timer general register C_0 (TGRC_0) Timer general register D_0 (TGRD_0) * Channel 1 Timer control register_1 (TCR_1) Timer mode register_1 (TMDR_1) Timer I/O control register _1 (TIOR_1) Timer interrupt enable register_1 (TIER_1) Timer status register_1 (TSR_1) Timer counter_1 (TCNT_1) Timer general register A_1 (TGRA_1) Timer general register B_1 (TGRB_1) * Channel 2 Timer control register_2 (TCR_2) Timer mode register_2 (TMDR_2) Timer I/O control register_2 (TIOR_2) Timer interrupt enable register_2 (TIER_2) Timer status register_2 (TSR_2) Timer counter_2 (TCNT_2) Timer general register A_2 (TGRA_2) Timer general register B_2 (TGRB_2) Rev.1.00 Jun. 07, 2006 Page 502 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) * Channel 3 Timer control register_3 (TCR_3) Timer mode register_3 (TMDR_3) Timer I/O control register H_3 (TIORH_3) Timer I/O control register L_3 (TIORL_3) Timer interrupt enable register_3 (TIER_3) Timer status register_3 (TSR_3) Timer counter_3 (TCNT_3) Timer general register A_3 (TGRA_3) Timer general register B_3 (TGRB_3) Timer general register C_3 (TGRC_3) Timer general register D_3 (TGRD_3) * Channel 4 Timer control register_4 (TCR_4) Timer mode register_4 (TMDR_4) Timer I/O control register _4 (TIOR_4) Timer interrupt enable register_4 (TIER_4) Timer status register_4 (TSR_4) Timer counter_4 (TCNT_4) Timer general register A_4 (TGRA_4) Timer general register B_4 (TGRB_4) * Channel 5 Timer control register_5 (TCR_5) Timer mode register_5 (TMDR_5) Timer I/O control register_5 (TIOR_5) Timer interrupt enable register_5 (TIER_5) Timer status register_5 (TSR_5) Timer counter_5 (TCNT_5) Timer general register A_5 (TGRA_5) Timer general register B_5 (TGRB_5) * Common Registers Timer start register (TSTR) Timer synchronous register (TSYR) Rev.1.00 Jun. 07, 2006 Page 503 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.1 Timer Control Register (TCR) TCR controls the TCNT operation for each channel. The TPU has a total of six TCR registers, one for each channel. TCR register settings should be made only while TCNT operation is stopped. Bit Bit Name Initial Value R/W 7 CCLR2 0 R/W 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 CKEG1 0 R/W 3 CKEG0 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W Bit 7 6 5 4 3 Bit Name CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 Initial Value 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Description Counter Clear 2 to 0 These bits select the TCNT counter clearing source. See tables 10.3 and 10.4 for details. Clock Edge 1 and 0 These bits select the input clock edge. For details, see table 10.5. When the input clock is counted using both edges, the input clock period is halved (e.g. P/4 both edges = P/2 rising edge). If phase counting mode is used on channels 1, 2, 4, and 5, this setting is ignored and the phase counting mode setting has priority. Internal clock edge selection is valid when the input clock is P/4 or slower. This setting is ignored if the input clock is P/1, or when overflow/underflow of another channel is selected. Timer Prescaler 2 to 0 These bits select the TCNT counter clock. The clock source can be selected independently for each channel. See tables 10.6 to 10.11 for details. To select the external clock as the clock source, the DDR bit and ICR bit for the corresponding pin should be set to 0 and 1, respectively. For details, see section 9, I/O Ports. 2 1 0 TPSC2 TPSC1 TPSC0 0 0 0 R/W R/W R/W Rev.1.00 Jun. 07, 2006 Page 504 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.3 CCLR2 to CCLR0 (Channels 0 and 3) Channel 0, 3 Bit 7 CCLR2 0 0 0 0 Bit 6 CCLR1 0 0 1 1 Bit 5 CCLR0 0 1 0 1 Description TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* TCNT clearing disabled TCNT cleared by TGRC compare match/input 2 capture* TCNT cleared by TGRD compare match/input 2 capture* TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* 1 1 1 1 0 0 1 1 0 1 0 1 Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. Table 10.4 CCLR2 to CCLR0 (Channels 1, 2, 4, and 5) Channel 1, 2, 4, 5 Bit 7 2 Reserved* 0 0 0 0 Bit 6 CCLR1 0 0 1 1 Bit 5 CCLR0 0 1 0 1 Description TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1. 2. Bit 7 is reserved in channels 1, 2, 4, and 5. It is always read as 0 and cannot be modified. Rev.1.00 Jun. 07, 2006 Page 505 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.5 Input Clock Edge Selection Clock Edge Selection CKEG1 0 0 1 [Legend] X: Don't care CKEG0 0 1 X Internal Clock Counted at falling edge Counted at rising edge Counted at both edges Input Clock External Clock Counted at rising edge Counted at falling edge Counted at both edges Table 10.6 TPSC2 to TPSC0 (Channel 0) Channel 0 Bit 2 TPSC2 0 0 0 0 1 1 1 1 Bit 1 TPSC1 0 0 1 1 0 0 1 1 Bit 0 TPSC0 0 1 0 1 0 1 0 1 Description Internal clock: counts on P/1 Internal clock: counts on P/4 Internal clock: counts on P/16 Internal clock: counts on P/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input External clock: counts on TCLKD pin input Table 10.7 TPSC2 to TPSC0 (Channel 1) Channel 1 Bit 2 TPSC2 0 0 0 0 1 1 1 1 Bit 1 TPSC1 0 0 1 1 0 0 1 1 Bit 0 TPSC0 0 1 0 1 0 1 0 1 Description Internal clock: counts on P/1 Internal clock: counts on P/4 Internal clock: counts on P/16 Internal clock: counts on P/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Internal clock: counts on P/256 Counts on TCNT2 overflow/underflow Note: This setting is ignored when channel 1 is in phase counting mode. Rev.1.00 Jun. 07, 2006 Page 506 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.8 TPSC2 to TPSC0 (Channel 2) Channel 2 Bit 2 TPSC2 0 0 0 0 1 1 1 1 Bit 1 TPSC1 0 0 1 1 0 0 1 1 Bit 0 TPSC0 0 1 0 1 0 1 0 1 Description Internal clock: counts on P/1 Internal clock: counts on P/4 Internal clock: counts on P/16 Internal clock: counts on P/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input Internal clock: counts on P/1024 Note: This setting is ignored when channel 2 is in phase counting mode. Table 10.9 TPSC2 to TPSC0 (Channel 3) Channel 3 Bit 2 TPSC2 0 0 0 0 1 1 1 1 Bit 1 TPSC1 0 0 1 1 0 0 1 1 Bit 0 TPSC0 0 1 0 1 0 1 0 1 Description Internal clock: counts on P/1 Internal clock: counts on P/4 Internal clock: counts on P/16 Internal clock: counts on P/64 External clock: counts on TCLKA pin input Internal clock: counts on P/1024 Internal clock: counts on P/256 Internal clock: counts on P/4096 Rev.1.00 Jun. 07, 2006 Page 507 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.10 TPSC2 to TPSC0 (Channel 4) Channel 4 Bit 2 TPSC2 0 0 0 0 1 1 1 1 Bit 1 TPSC1 0 0 1 1 0 0 1 1 Bit 0 TPSC0 0 1 0 1 0 1 0 1 Description Internal clock: counts on P/1 Internal clock: counts on P/4 Internal clock: counts on P/16 Internal clock: counts on P/64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on P/1024 Counts on TCNT5 overflow/underflow Note: This setting is ignored when channel 4 is in phase counting mode. Table 10.11 TPSC2 to TPSC0 (Channel 5) Channel 5 Bit 2 TPSC2 0 0 0 0 1 1 1 1 Bit 1 TPSC1 0 0 1 1 0 0 1 1 Bit 0 TPSC0 0 1 0 1 0 1 0 1 Description Internal clock: counts on P/1 Internal clock: counts on P/4 Internal clock: counts on P/16 Internal clock: counts on P/64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on P/256 External clock: counts on TCLKD pin input Note: This setting is ignored when channel 5 is in phase counting mode. Rev.1.00 Jun. 07, 2006 Page 508 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.2 Timer Mode Register (TMDR) TMDR sets the operating mode for each channel. The TPU has six TMDR registers, one for each channel. TMDR register settings should be made only while TCNT operation is stopped. Bit Bit Name Initial Value R/W 7 1 R 6 1 R 5 BFB 0 R/W 4 BFA 0 R/W 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W Bit 7, 6 5 Bit Name Initial Value All 1 0 R/W R R/W Description Reserved These are read-only bits and cannot be modified. Buffer Operation B Specifies whether TGRB is to normally operate, or TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer register, TGRD input capture/output compare is not generated. In channels 1, 2, 4, and 5, which have no TGRD, bit 5 is reserved. It is always read as 0 and cannot be modified. 0: TGRB operates normally 1: TGRB and TGRD used together for buffer operation BFB 4 BFA 0 R/W Buffer Operation A Specifies whether TGRA is to normally operate, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not generated. In channels 1, 2, 4, and 5, which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot be modified. 0: TGRA operates normally 1: TGRA and TGRC used together for buffer operation 3 2 1 0 MD3 MD2 MD1 MD0 0 0 0 0 R/W R/W R/W R/W Modes 3 to 0 Set the timer operating mode. MD3 is a reserved bit. The write value should always be 0. See table 10.12 for details. Rev.1.00 Jun. 07, 2006 Page 509 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.12 MD3 to MD0 Bit 3 1 MD3* 0 0 0 0 0 0 0 0 1 Bit 2 2 MD2* 0 0 0 0 1 1 1 1 X Bit 1 MD1 0 0 1 1 0 0 1 1 X Bit 0 MD0 0 1 0 1 0 1 0 1 X Description Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 [Legend] X: Don't care Notes: 1. MD3 is a reserved bit. The write value should always be 0. 2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always be written to MD2. 10.3.3 Timer I/O Control Register (TIOR) TIOR controls TGR. The TPU has eight TIOR registers, two each for channels 0 and 3, and one each for channels 1, 2, 4, and 5. Care is required since TIOR is affected by the TMDR setting. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is cleared to 0 is specified. When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. To designate the input capture pin in TIOR, the DDR bit and ICR bit for the corresponding pin should be set to 0 and 1, respectively. For details, see section 9, I/O Ports. Rev.1.00 Jun. 07, 2006 Page 510 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) * TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIOR_4, TIOR_5 Bit Bit Name Initial Value R/W 7 IOB3 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2 IOA2 0 R/W 1 IOA1 0 R/W 0 IOA0 0 R/W * TIORL_0, TIORL_3 Bit Bit Name Initial Value R/W 7 IOD3 0 R/W 6 IOD2 0 R/W 5 IOD1 0 R/W 4 IOD0 0 R/W 3 IOC3 0 R/W 2 IOC2 0 R/W 1 IOC1 0 R/W 0 IOC0 0 R/W * TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIOR_4, TIOR_5 Bit 7 6 5 4 3 2 1 0 Bit Name IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description I/O Control B3 to B0 Specify the function of TGRB. For details, see tables 10.13, 10.15, 10.16, 10.17, 10.19, and 10.20. I/O Control A3 to A0 Specify the function of TGRA. For details, see tables 10.21, 10.23, 10.24, 10.25, 10.27, and 10.28. * TIORL_0, TIORL_3: Bit 7 6 5 4 3 2 1 0 Bit Name IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W I/O Control C3 to C0 Specify the function of TGRC. For details, see tables 10.22 and 10.26. Description I/O Control D3 to D0 Specify the function of TGRD. For details, see tables 10.14 and 10.18. Rev.1.00 Jun. 07, 2006 Page 511 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.13 TIORH_0 Description Bit 7 IOB3 0 0 0 0 0 0 0 0 1 1 1 1 Bit 6 IOB2 0 0 0 0 1 1 1 1 0 0 0 1 Bit 5 IOB1 0 0 1 1 0 0 1 1 0 0 1 x Bit 4 IOB0 0 1 0 1 0 1 0 1 0 1 x x Input capture register TGRB_0 Function Output compare register TIOCB0 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCB0 pin Input capture at rising edge Capture input source is TIOCB0 pin Input capture at falling edge Capture input source is TIOCB0 pin Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down* [Legend] X: Don't care Note: When bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and P/1 is used as the TCNT_1 count clock, this setting is invalid and input capture is not generated. Rev.1.00 Jun. 07, 2006 Page 512 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.14 TIORL_0 Description Bit 7 IOD3 0 0 0 0 0 0 0 0 1 1 1 1 Bit 6 IOD2 0 0 0 0 1 1 1 1 0 0 0 1 Bit 5 IOD1 0 0 1 1 0 0 1 1 0 0 1 X Bit 4 IOD0 0 1 0 1 0 1 0 1 0 1 X X Input capture 2 register* TGRD_0 Function Output compare 2 register* TIOCD0 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCD0 pin Input capture at rising edge Capture input source is TIOCD0 pin Input capture at falling edge Capture input source is TIOCD0 pin Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down* 1 [Legend] X: Don't care Notes: 1. When bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and P/1 is used as the TCNT_1 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev.1.00 Jun. 07, 2006 Page 513 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.15 TIOR_1 Description Bit 7 IOB3 0 0 0 0 0 0 0 0 1 1 1 1 Bit 6 IOB2 0 0 0 0 1 1 1 1 0 0 0 1 Bit 5 IOB1 0 0 1 1 0 0 1 1 0 0 1 X Bit 4 IOB0 0 1 0 1 0 1 0 1 0 1 X X Input capture register TGRB_1 Function Output compare register TIOCB1 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCB1 pin Input capture at rising edge Capture input source is TIOCB1 pin Input capture at falling edge Capture input source is TIOCB1 pin Input capture at both edges TGRC_0 compare match/input capture Input capture at generation of TGRC_0 compare match/input capture [Legend] X: Don't care Rev.1.00 Jun. 07, 2006 Page 514 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.16 TIOR_2 Description Bit 7 IOB3 0 0 0 0 0 0 0 0 1 1 1 Bit 6 IOB2 0 0 0 0 1 1 1 1 X X X Bit 5 IOB1 0 0 1 1 0 0 1 1 0 0 1 Bit 4 IOB0 0 1 0 1 0 1 0 1 0 1 X Input capture register TGRB_2 Function Output compare register TIOCB2 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCB2 pin Input capture at rising edge Capture input source is TIOCB2 pin Input capture at falling edge Capture input source is TIOCB2 pin Input capture at both edges [Legend] X: Don't care Rev.1.00 Jun. 07, 2006 Page 515 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.17 TIORH_3 Description Bit 7 IOB3 0 0 0 0 0 0 0 0 1 1 1 1 Bit 6 IOB2 0 0 0 0 1 1 1 1 0 0 0 1 Bit 5 IOB1 0 0 1 1 0 0 1 1 0 0 1 x Bit 4 IOB0 0 1 0 1 0 1 0 1 0 1 x x Input capture register TGRB_3 Function Output compare register TIOCB3 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCB3 pin Input capture at rising edge Capture input source is TIOCB3 pin Input capture at falling edge Capture input source is TIOCB3 pin Input capture at both edges Capture input source is channel 4/count clock Input capture at TCNT_4 count-up/count-down* [Legend] X: Don't care Note: When bits TPSC2 to TPSC0 in TCR_4 are set to B'000 and P/1 is used as the TCNT_4 count clock, this setting is invalid and input capture is not generated. Rev.1.00 Jun. 07, 2006 Page 516 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.18 TIORL_3 Description Bit 7 IOD3 0 0 0 0 0 0 0 0 1 1 1 1 Bit 6 IOD2 0 0 0 0 1 1 1 1 0 0 0 1 Bit 5 IOD1 0 0 1 1 0 0 1 1 0 0 1 x Bit 4 IOD0 0 1 0 1 0 1 0 1 0 1 x x Input capture 2 register* TGRD_3 Function Output compare 2 register* TIOCD3 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCD3 pin Input capture at rising edge Capture input source is TIOCD3 pin Input capture at falling edge Capture input source is TIOCD3 pin Input capture at both edges Capture input source is channel 4/count clock Input capture at TCNT_4 count-up/count-down* 1 [Legend] X: Don't care Notes: 1. When bits TPSC2 to TPSC0 in TCR_4 are set to B'000 and P/1 is used as the TCNT_4 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR_3 is set to 1 and TGRD_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev.1.00 Jun. 07, 2006 Page 517 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.19 TIOR_4 Description Bit 7 IOB3 0 0 0 0 0 0 0 0 1 1 1 1 Bit 6 IOB2 0 0 0 0 1 1 1 1 0 0 0 1 Bit 5 IOB1 0 0 1 1 0 0 1 1 0 0 1 x Bit 4 IOB0 0 1 0 1 0 1 0 1 0 1 x x Input capture register TGRB_4 Function Output compare register TIOCB4 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCB4 pin Input capture at rising edge Capture input source is TIOCB4 pin Input capture at falling edge Capture input source is TIOCB4 pin Input capture at both edges Capture input source is TGRC_3 compare match/input capture Input capture at generation of TGRC_3 compare match/input capture [Legend] X: Don't care Rev.1.00 Jun. 07, 2006 Page 518 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.20 TIOR_5 Description Bit 7 IOB3 0 0 0 0 0 0 0 0 1 1 1 Bit 6 IOB2 0 0 0 0 1 1 1 1 x x x Bit 5 IOB1 0 0 1 1 0 0 1 1 0 0 1 Bit 4 IOB0 0 1 0 1 0 1 0 1 0 1 x Input capture register TGRB_5 Function Output compare register TIOCB5 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCB5 pin Input capture at rising edge Capture input source is TIOCB5 pin Input capture at falling edge Capture input source is TIOCB5 pin Input capture at both edges [Legend] X: Don't care Rev.1.00 Jun. 07, 2006 Page 519 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.21 TIORH_0 Description Bit 3 IOA3 0 0 0 0 0 0 0 0 1 1 1 1 Bit 2 IOA2 0 0 0 0 1 1 1 1 0 0 0 1 Bit 1 IOA1 0 0 1 1 0 0 1 1 0 0 1 X Bit 0 IOA0 0 1 0 1 0 1 0 1 0 1 X X Input capture register TGRA_0 Function Output compare register TIOCA0 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCA0 pin Input capture at rising edge Capture input source is TIOCA0 pin Input capture at falling edge Capture input source is TIOCA0 pin Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] X: Don't care Rev.1.00 Jun. 07, 2006 Page 520 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.22 TIORL_0 Description Bit 3 IOC3 0 0 0 0 0 0 0 0 1 1 1 1 Bit 2 IOC2 0 0 0 0 1 1 1 1 0 0 0 1 Bit 1 IOC1 0 0 1 1 0 0 1 1 0 0 1 X Bit 0 IOC0 0 1 0 1 0 1 0 1 0 1 X X Input capture register* TGRC_0 Function Output compare register* TIOCC0 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCC0 pin Input capture at rising edge Capture input source is TIOCC0 pin Input capture at falling edge Capture input source is TIOCC0 pin Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] X: Don't care Note: 1. When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev.1.00 Jun. 07, 2006 Page 521 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.23 TIOR_1 Description Bit 3 IOA3 0 0 0 0 0 0 0 0 1 1 1 1 Bit 2 IOA2 0 0 0 0 1 1 1 1 0 0 0 1 Bit 1 IOA1 0 0 1 1 0 0 1 1 0 0 1 X Bit 0 IOA0 0 1 0 1 0 1 0 1 0 1 X X Input capture register TGRA_1 Function Output compare register TIOCA1 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCA1 pin Input capture at rising edge Capture input source is TIOCA1 pin Input capture at falling edge Capture input source is TIOCA1 pin Input capture at both edges Capture input source is TGRA_0 compare match/input capture Input capture at generation of channel 0/TGRA_0 compare match/input capture [Legend] X: Don't care Rev.1.00 Jun. 07, 2006 Page 522 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.24 TIOR_2 Description Bit 3 IOA3 0 0 0 0 0 0 0 0 1 1 1 Bit 2 IOA2 0 0 0 0 1 1 1 1 X X X Bit 1 IOA1 0 0 1 1 0 0 1 1 0 0 1 Bit 0 IOA0 0 1 0 1 0 1 0 1 0 1 X Input capture register TGRA_2 Function Output compare register TIOCA2 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCA2 pin Input capture at rising edge Capture input source is TIOCA2 pin Input capture at falling edge Capture input source is TIOCA2 pin Input capture at both edges [Legend] X: Don't care Rev.1.00 Jun. 07, 2006 Page 523 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.25 TIORH_3 Description Bit 3 IOA3 0 0 0 0 0 0 0 0 1 1 1 1 Bit 2 IOA2 0 0 0 0 1 1 1 1 0 0 0 1 Bit 1 IOA1 0 0 1 1 0 0 1 1 0 0 1 X Bit 0 IOA0 0 1 0 1 0 1 0 1 0 1 X X Input capture register TGRA_3 Function Output compare register TIOCA3 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCA3 pin Input capture at rising edge Capture input source is TIOCA3 pin Input capture at falling edge Capture input source is TIOCA3 pin Input capture at both edges Capture input source is channel 4/count clock Input capture at TCNT_4 count-up/count-down [Legend] X: Don't care Rev.1.00 Jun. 07, 2006 Page 524 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.26 TIORL_3 Description Bit 3 IOC3 0 0 0 0 0 0 0 0 1 1 1 1 Bit 2 IOC2 0 0 0 0 1 1 1 1 0 0 0 1 Bit 1 IOC1 0 0 1 1 0 0 1 1 0 0 1 X Bit 0 IOC0 0 1 0 1 0 1 0 1 0 1 X X Input capture register* TGRC_3 Function Output compare register* TIOCC3 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCC3 pin Input capture at rising edge Capture input source is TIOCC3 pin Input capture at falling edge Capture input source is TIOCC3 pin Input capture at both edges Capture input source is channel 4/count clock Input capture at TCNT_4 count-up/count-down [Legend] X: Don't care Note: * When the BFA bit in TMDR_3 is set to 1 and TGRC_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev.1.00 Jun. 07, 2006 Page 525 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.27 TIOR_4 Description Bit 3 IOA3 0 0 0 0 0 0 0 0 1 1 1 1 Bit 2 IOA2 0 0 0 0 1 1 1 1 0 0 0 1 Bit 1 IOA1 0 0 1 1 0 0 1 1 0 0 1 X Bit 0 IOA0 0 1 0 1 0 1 0 1 0 1 X X Input capture register TGRA_4 Function Output compare register TIOCA4 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCA4 pin Input capture at rising edge Capture input source is TIOCA4 pin Input capture at falling edge Capture input source is TIOCA4 pin Input capture at both edges Capture input source is TGRA_3 compare match/input capture Input capture at generation of TGRA_3 compare match/input capture [Legend] X: Don't care Rev.1.00 Jun. 07, 2006 Page 526 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.28 TIOR_5 Description Bit 3 IOA3 0 0 0 0 0 0 0 0 1 1 1 Bit 2 IOA2 0 0 0 0 1 1 1 1 X X X Bit 1 IOA1 0 0 1 1 0 0 1 1 0 0 1 Bit 0 IOA0 0 1 0 1 0 1 0 1 0 1 X Input capture register TGRA_5 Function Output compare register TIOCA5 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Input capture source is TIOCA5 pin Input capture at rising edge Input capture source is TIOCA5 pin Input capture at falling edge Input capture source is TIOCA5 pin Input capture at both edges [Legend] X: Don't care Rev.1.00 Jun. 07, 2006 Page 527 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.4 Timer Interrupt Enable Register (TIER) TIER controls enabling or disabling of interrupt requests for each channel. The TPU has six TIER registers, one for each channel. Bit Bit Name Initial Value R/W 7 TTGE 0 R/W 6 1 R 5 TCIEU 0 R/W 4 TCIEV 0 R/W 3 TGIED 0 R/W 2 TGIEC 0 R/W 1 TGIEB 0 R/W 0 TGIEA 0 R/W Bit 7 Bit Name TTGE Initial value 0 R/W R/W Description A/D Conversion Start Request Enable Enables/disables generation of A/D conversion start requests by TGRA input capture/compare match. 0: A/D conversion start request generation disabled 1: A/D conversion start request generation enabled 6 5 TCIEU 1 0 R R/W Reserved This is a read-only bit and cannot be modified. Underflow Interrupt Enable Enables/disables interrupt requests (TCIU) by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1, 2, 4, and 5. In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified. 0: Interrupt requests (TCIU) by TCFU disabled 1: Interrupt requests (TCIU) by TCFU enabled 4 TCIEV 0 R/W Overflow Interrupt Enable Enables/disables interrupt requests (TCIV) by the TCFV flag when the TCFV flag in TSR is set to 1. 0: Interrupt requests (TCIV) by TCFV disabled 1: Interrupt requests (TCIV) by TCFV enabled Rev.1.00 Jun. 07, 2006 Page 528 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Bit 3 Bit Name TGIED Initial value 0 R/W R/W Description TGR Interrupt Enable D Enables/disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified. 0: Interrupt requests (TGID) by TGFD bit disabled 1: Interrupt requests (TGID) by TGFD bit enabled 2 TGIEC 0 R/W TGR Interrupt Enable C Enables/disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified. 0: Interrupt requests (TGIC) by TGFC bit disabled 1: Interrupt requests (TGIC) by TGFC bit enabled 1 TGIEB 0 R/W TGR Interrupt Enable B Enables/disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1. 0: Interrupt requests (TGIB) by TGFB bit disabled 1: Interrupt requests (TGIB) by TGFB bit enabled 0 TGIEA 0 R/W TGR Interrupt Enable A Enables/disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1. 0: Interrupt requests (TGIA) by TGFA bit disabled 1: Interrupt requests (TGIA) by TGFA bit enabled Rev.1.00 Jun. 07, 2006 Page 529 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.5 Timer Status Register (TSR) TSR indicates the status of each channel. The TPU has six TSR registers, one for each channel. Bit Bit Name Initial Value R/W Note: 7 TCFD 1 R 6 1 R 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* 3 TGFD 0 R/(W)* 2 TGFC 0 R/(W)* 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* * Only 0 can be written to bits 5 to 0, to clear flags. Bit 7 Bit Name TCFD Initial value 1 R/W R Description Count Direction Flag Status flag that shows the direction in which TCNT counts in channels 1, 2, 4, and 5. In channels 0 and 3, bit 7 is reserved. It is always read as 1 and cannot be modified. 0: TCNT counts down 1: TCNT counts up Reserved This is a read-only bit and cannot be modified. 6 5 TCFU 1 0 R R/(W)* Underflow Flag Status flag that indicates that a TCNT underflow has occurred when channels 1, 2, 4, and 5 are set to phase counting mode. In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified. [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) [Clearing condition] When a 0 is written to TCFU after reading TCFU = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) Rev.1.00 Jun. 07, 2006 Page 530 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Bit 4 Bit Name TCFV Initial value 0 R/W Description R/(W)* Overflow Flag Status flag that indicates that a TCNT overflow has occurred. [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000) [Clearing condition] When a 0 is written to TCFV after reading TCFV = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) R/(W)* Input Capture/Output Compare Flag D Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified. [Setting conditions] * * When TCNT = TGRD while TGRD is functioning as output compare register When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register When DTC is activated by a TGID interrupt while the DISEL bit in MRB of DTC is 0 When 0 is written to TGFD after reading TGFD = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) 3 TGFD 0 [Clearing conditions] * * Rev.1.00 Jun. 07, 2006 Page 531 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Bit 2 Bit Name TGFC Initial value 0 R/W Description Status flag that indicates the occurrence of TGRC input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified. [Setting conditions] * * When TCNT = TGRC while TGRC is functioning as output compare register When TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register When DTC is activated by a TGIC interrupt while the DISEL bit in MRB of DTC is 0 When 0 is written to TGFC after reading TGFC = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) R/(W)* Input Capture/Output Compare Flag C [Clearing conditions] * * 1 TGFB 0 R/(W)* Input Capture/Output Compare Flag B Status flag that indicates the occurrence of TGRB input capture or compare match. [Setting conditions] * * When TCNT = TGRB while TGRB is functioning as output compare register When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register When DTC is activated by a TGIB interrupt while the DISEL bit in MRB of DTC is 0 When 0 is written to TGFB after reading TGFB = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) [Clearing conditions] * * Rev.1.00 Jun. 07, 2006 Page 532 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Bit 0 Bit Name TGFA Initial value 0 R/W Description Status flag that indicates the occurrence of TGRA input capture or compare match. [Setting conditions] * * When TCNT = TGRA while TGRA is functioning as output compare register When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register When DTC is activated by a TGIA interrupt while the DISEL bit in MRB of DTC is 0 When DMAC is activated by a TGIA interrupt while the DTA bit in DMDR of DMAC is 1 When 0 is written to TGFA after reading TGFA = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) R/(W)* Input Capture/Output Compare Flag A [Clearing conditions] * * * Note: * Only 0 can be written to clear the flag. Rev.1.00 Jun. 07, 2006 Page 533 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.6 Timer Counter (TCNT) TCNT is a 16-bit readable/writable counter. The TPU has six TCNT counters, one for each channel. TCNT is initialized to H'0000 by a reset or in hardware standby mode. TCNT cannot be accessed in 8-bit units. TCNT must always be accessed in 16-bit units. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 15 14 13 12 11 10 9 8 10.3.7 Timer General Register (TGR) TGR is a 16-bit readable/writable register with a dual function as output compare and input capture registers. The TPU has 16 TGR registers, four each for channels 0 and 3 and two each for channels 1, 2, 4, and 5. TGRC and TGRD for channels 0 and 3 can also be designated for operation as buffer registers. The TGR registers cannot be accessed in 8-bit units; they must always be accessed in 16-bit units. TGR and buffer register combinations during buffer operations are TGRA-TGRC and TGRB-TGRD. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 15 14 13 12 11 10 9 8 Rev.1.00 Jun. 07, 2006 Page 534 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.8 Timer Start Register (TSTR) TSTR starts or stops operation for channels 0 to 5. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter. Bit Bit Name Initial Value R/W 7 0 R/W 6 0 R/W 5 CST5 0 R/W 4 CST4 0 R/W 3 CST3 0 R/W 2 CST2 0 R/W 1 CST1 0 R/W 0 CST0 0 R/W Bit 7, 6 Bit Name Initial value All 0 R/W R/W Description Reserved These bits are always read as 0. The write value should always be 0. 5 4 3 2 1 0 CST5 CST4 CST3 CST2 CST1 CST0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Counter Start 5 to 0 These bits select operation or stoppage for TCNT. If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_5 to TCNT_0 count operation is stopped 1: TCNT_5 to TCNT_0 performs count operation Rev.1.00 Jun. 07, 2006 Page 535 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.9 Timer Synchronous Register (TSYR) TSYR selects independent operation or synchronous operation for the TCNT counters of channels 0 to 5. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. Bit Bit Name Initial Value R/W 7 0 R/W 6 0 R/W 5 SYNC5 0 R/W 4 SYNC4 0 R/W 3 SYNC3 0 R/W 2 SYNC2 0 R/W 1 SYNC1 0 R/W 0 SYNC0 0 R/W Bit 7, 6 Bit Name Initial value All 0 R/W R/W Description Reserved These bits are always read as 0. The write value should always be 0. 5 4 3 2 1 0 SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Timer Synchronization 5 to 0 These bits select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, synchronous presetting of multiple channels, and synchronous clearing through counter clearing on another channel are possible. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source must also be set by means of bits CCLR2 to CCLR0 in TCR. 0: TCNT_5 to TCNT_0 operate independently (TCNT presetting/clearing is unrelated to other channels) 1: TCNT_5 to TCNT_0 perform synchronous operation (TCNT synchronous presetting/synchronous clearing is possible) Rev.1.00 Jun. 07, 2006 Page 536 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.4 10.4.1 Operation Basic Functions Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, periodic counting, and external event counting. Each TGR can be used as an input capture register or output compare register. (1) Counter Operation When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting. TCNT can operate as a free-running counter, periodic counter, and so on. (a) Example of count operation setting procedure Figure 10.2 shows an example of the count operation setting procedure. [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] For periodic counter operation, select the TGR to be used as the TCNT clearing source with bits CCLR2 to CCLR0 in TCR. [3] Designate the TGR selected in [2] as an output compare register by means of TIOR. [4] Set the periodic counter cycle in the TGR selected in [2]. [5] Set the CST bit in TSTR to 1 to start the counter operation. Start count Operation selection Select counter clock [1] Periodic counter Free-running counter Select counter clearing source [2] Select output compare register [3] Set period [4] Start count [5] Figure 10.2 Example of Counter Operation Setting Procedure Rev.1.00 Jun. 07, 2006 Page 537 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) (b) Free-running count operation and periodic count operation Immediately after a reset, the TPU's TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts up-count operation as a free-running counter. When TCNT overflows (changes from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this point, the TPU requests an interrupt. After overflow, TCNT starts counting up again from H'0000. Figure 10.3 illustrates free-running counter operation. TCNT value H'FFFF H'0000 Time CST bit TCFV Figure 10.3 Free-Running Counter Operation When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant channel performs periodic count operation. The TGR register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits CCLR2 to CCLR0 in TCR. After the settings have been made, TCNT starts count-up operation as a periodic counter when the corresponding bit in TSTR is set to 1. When the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared to H'0000. If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an interrupt. After a compare match, TCNT starts counting up again from H'0000. Rev.1.00 Jun. 07, 2006 Page 538 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Figure 10.4 illustrates periodic counter operation. TCNT value TGR Counter cleared by TGR compare match H'0000 Time CST bit Flag cleared by software or DTC activation TGF Figure 10.4 Periodic Counter Operation (2) Waveform Output by Compare Match The TPU can perform 0, 1, or toggle output from the corresponding output pin using a compare match. (a) Example of setting procedure for waveform output by compare match Figure 10.5 shows an example of the setting procedure for waveform output by a compare match. Output selection [1] Select initial value from 0-output or 1-output, and compare match output value from 0-output, 1-output, or toggle-output, by means of TIOR. [1] The set initial value is output on the TIOC pin until the first compare match occurs. [2] Set the timing for compare match generation in TGR. [3] Set the CST bit in TSTR to 1 to start the count operation. Select waveform output mode Set output timing [2] Start count [3] Figure 10.5 Example of Setting Procedure for Waveform Output by Compare Match Rev.1.00 Jun. 07, 2006 Page 539 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) (b) Examples of waveform output operation Figure 10.6 shows an example of 0-output and 1-output. In this example, TCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level match, the pin level does not change. TCNT value H'FFFF TGRA TGRB H'0000 No change TIOCA TIOCB No change No change No change 1-output 0-output Time Figure 10.6 Example of 0-Output/1-Output Operation Figure 10.7 shows an example of toggle output. In this example, TCNT has been designated as a periodic counter (with counter clearing performed by compare match B), and settings have been made so that output is toggled by both compare match A and compare match B. TCNT value Counter cleared by TGRB compare match H'FFFF TGRB TGRA H'0000 Time Toggle-output Toggle-output TIOCB TIOCA Figure 10.7 Example of Toggle Output Operation Rev.1.00 Jun. 07, 2006 Page 540 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) (3) Input Capture Function The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detection edge. For channels 0, 1, 3, and 4, it is also possible to specify another channel's counter input clock or compare match signal as the input capture source. Note: When another channel's counter input clock is used as the input capture input for channels 0 and 3, P/1 should not be selected as the counter input clock used for input capture input. Input capture will not be generated if P/1 is selected. (a) Example of setting procedure for input capture operation Figure 10.8 shows an example of the setting procedure for input capture operation. Input selection [1] Designate TGR as an input capture register by means of TIOR, and select the input capture source and input signal edge (rising edge, falling edge, or both edges). [2] Set the CST bit in TSTR to 1 to start the count operation. Select input capture input [1] Start count [2] Figure 10.8 Example of Setting Procedure for Input Capture Operation Rev.1.00 Jun. 07, 2006 Page 541 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) (b) Example of input capture operation Figure 10.9 shows an example of input capture operation. In this example, both rising and falling edges have been selected as the TIOCA pin input capture input edge, falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT. Counter cleared by TIOCB input (falling edge) TCNT value H'0180 H'0160 H'0010 H'0005 H'0000 Time TIOCA TGRA H'0005 H'0160 H'0010 TIOCB TGRB H'0180 Figure 10.9 Example of Input Capture Operation Rev.1.00 Jun. 07, 2006 Page 542 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.4.2 Synchronous Operation In synchronous operation, the values in multiple TCNT counters can be rewritten simultaneously (synchronous presetting). Also, multiple TCNT counters can be cleared simultaneously (synchronous clearing) by making the appropriate setting in TCR. Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 5 can all be designated for synchronous operation. (1) Example of Synchronous Operation Setting Procedure Figure 10.10 shows an example of the synchronous operation setting procedure. Synchronous operation selection Set synchronous operation [1] Synchronous presetting Synchronous clearing Set TCNT [2] Clearing source generation channel? Yes Select counter clearing source No [3] Set synchronous counter clearing [4] Start count [5] Start count [5] [1] Set the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation to 1. [2] When the TCNT counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other TCNT counters. [3] Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc. [4] Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source. [5] Set the CST bits in TSTR for the relevant channels to 1, to start the count operation. Figure 10.10 Example of Synchronous Operation Setting Procedure Rev.1.00 Jun. 07, 2006 Page 543 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) (2) Example of Synchronous Operation Figure 10.11 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. Three-phase PWM waveforms are output from pins TIOCA0, TIOCA1, and TIOCA2. At this time, synchronous presetting and synchronous clearing by TGRB_0 compare match are performed for channel 0 to 2 TCNT counters, and the data set in TGRB_0 is used as the PWM cycle. For details on PWM modes, see section 10.4.5, PWM Modes. Synchronous clearing by TGRB_0 compare match TCNT_0 to TCNT_2 values TGRB_0 TGRB_1 TGRA_0 TGRB_2 TGRA_1 TGRA_2 H'0000 Time TIOCA_0 TIOCA_1 TIOCA_2 Figure 10.11 Example of Synchronous Operation Rev.1.00 Jun. 07, 2006 Page 544 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.4.3 Buffer Operation Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or a compare match register. Table 10.29 shows the register combinations used in buffer operation. Table 10.29 Register Combinations in Buffer Operation Channel 0 Timer General Register TGRA_0 TGRB_0 3 TGRA_3 TGRB_3 Buffer Register TGRC_0 TGRD_0 TGRC_3 TGRD_3 * When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 10.12. Compare match signal Buffer register Timer general register Comparator TCNT Figure 10.12 Compare Match Buffer Operation Rev.1.00 Jun. 07, 2006 Page 545 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) * When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in TGR is transferred to the buffer register. This operation is illustrated in figure 10.13. Input capture signal Timer general register Buffer register TCNT Figure 10.13 Input Capture Buffer Operation (1) Example of Buffer Operation Setting Procedure Figure 10.14 shows an example of the buffer operation setting procedure. Buffer operation [1] Designate TGR as an input capture register or output compare register by means of TIOR. [1] Select TGR function [2] Designate TGR for buffer operation with bits BFA and BFB in TMDR. [3] Set the CST bit in TSTR to 1 to start the count operation. Set buffer operation [2] Start count [3] Figure 10.14 Example of Buffer Operation Setting Procedure Rev.1.00 Jun. 07, 2006 Page 546 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) (2) (a) Examples of Buffer Operation When TGR is an output compare register Figure 10.15 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B. As buffer operation has been set, when compare match A occurs, the output changes and the value in buffer register TGRC is simultaneously transferred to timer general register TGRA. This operation is repeated each time compare match A occurs. For details on PWM modes, see section 10.4.5, PWM Modes. TCNT value TGRB_0 H'0200 TGRA_0 H'0000 TGRC_0 H'0200 Transfer TGRA_0 H'0200 H'0450 H'0450 H'0520 Time H'0520 H'0450 TIOCA Figure 10.15 Example of Buffer Operation (1) Rev.1.00 Jun. 07, 2006 Page 547 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) (b) When TGR is an input capture register Figure 10.16 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge. As buffer operation has been set, when the TCNT value is stored in TGRA upon occurrence of input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC. TCNT value H'0F07 H'09FB H'0532 H'0000 Time TIOCA TGRA H'0532 H'0F07 H'09FB TGRC H'0532 H'0F07 Figure 10.16 Example of Buffer Operation (2) Rev.1.00 Jun. 07, 2006 Page 548 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.4.4 Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 (channel 4) counter clock at overflow/underflow of TCNT_2 (TCNT_5) as set in bits TPSC2 to TPSC0 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode. Table 10.30 shows the register combinations used in cascaded operation. Note: When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid and the counter operates independently in phase counting mode. Table 10.30 Cascaded Combinations Combination Channels 1 and 2 Channels 4 and 5 Upper 16 Bits TCNT_1 TCNT_4 Lower 16 Bits TCNT_2 TCNT_5 (1) Example of Cascaded Operation Setting Procedure Figure 10.17 shows an example of the setting procedure for cascaded operation. Cascaded operation Set cascading [1] [1] Set bits TPSC2 to TPSC0 in the channel 1 (channel 4) TCR to B'1111 to select TCNT_2 (TCNT_5) overflow/underflow counting. [2] Set the CST bit in TSTR for the upper and lower channels to 1 to start the count operation. Start count [2] Figure 10.17 Example of Cascaded Operation Setting Procedure Rev.1.00 Jun. 07, 2006 Page 549 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) (2) Examples of Cascaded Operation Figure 10.18 illustrates the operation when counting upon TCNT_2 overflow/underflow has been set for TCNT_1, TGRA_1 and TGRA_2 have been designated as input capture registers, and the TIOC pin rising edge has been selected. When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of the 32-bit data are transferred to TGRA_1, and the lower 16 bits to TGRA_2. TCNT_1 clock TCNT_1 TCNT_2 clock TCNT_2 TIOCA1, TIOCA2 TGRA_1 H'03A2 H'FFFF H'0000 H'0001 H'03A1 H'03A2 TGRA_2 H'0000 Figure 10.18 Example of Cascaded Operation (1) Figure 10.19 illustrates the operation when counting upon TCNT_2 overflow/underflow has been set for TCNT_1, and phase counting mode has been designated for channel 2. TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow. TCLKC TCLKD TCNT_2 FFFD FFFE FFFF 0000 0001 0002 0001 0000 FFFF TCNT_1 0000 0001 0000 Figure 10.19 Example of Cascaded Operation (2) Rev.1.00 Jun. 07, 2006 Page 550 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.4.5 PWM Modes In PWM mode, PWM waveforms are output from the output pins. 0-, 1-, or toggle-output can be selected as the output level in response to compare match of each TGR. Settings of TGR registers can output a PWM waveform in the range of 0% to 100% duty cycle. Designating TGR compare match as the counter clearing source enables the cycle to be set in that register. All channels can be designated for PWM mode independently. Synchronous operation is also possible. There are two PWM modes, as described below. 1. PWM mode 1 PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD. The outputs specified by bits IOA3 to IOA0 and IOC3 to IOC0 in TIOR are output from the TIOCA and TIOCC pins at compare matches A and C, respectively. The outputs specified by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR are output at compare matches B and D, respectively. The initial output value is the value set in TGRA or TGRC. If the set values of paired TGRs are identical, the output value does not change when a compare match occurs. In PWM mode 1, a maximum 8-phase PWM output is possible. 2. PWM mode 2 PWM output is generated using one TGR as the cycle register and the others as duty cycle registers. The output specified in TIOR is performed by means of compare matches. Upon counter clearing by a cycle register compare match, the output value of each pin is the initial value set in TIOR. If the set values of the cycle and duty cycle registers are identical, the output value does not change when a compare match occurs. In PWM mode 2, a maximum 15-phase PWM output is possible by combined use with synchronous operation. Rev.1.00 Jun. 07, 2006 Page 551 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) The correspondence between PWM output pins and registers is shown in table 10.31. Table 10.31 PWM Output Registers and Output Pins Output Pins Channel 0 Registers TGRA_0 TGRB_0 TGRC_0 TGRD_0 1 TGRA_1 TGRB_1 2 TGRA_2 TGRB_2 3 TGRA_3 TGRB_3 TGRC_3 TGRD_3 4 TGRA_4 TGRB_4 5 TGRA_5 TGRB_5 TIOCA5 TIOCA4 TIOCC3 TIOCA3 TIOCA2 TIOCA1 TIOCC0 PWM Mode 1 TIOCA0 PWM Mode 2 TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 TIOCB4 TIOCA5 TIOCB5 Note: In PWM mode 2, PWM output is not possible for the TGR register in which the cycle is set. Rev.1.00 Jun. 07, 2006 Page 552 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) (1) Example of PWM Mode Setting Procedure Figure 10.20 shows an example of the PWM mode setting procedure. PWM mode [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] Use bits CCLR2 to CCLR0 in TCR to select the TGR to be used as the TCNT clearing source. [3] Use TIOR to designate TGR as an output compare register, and select the initial value and output value. [4] Set the cycle in TGR selected in [2], and set the duty in the other TGRs. [5] Select the PWM mode with bits MD3 to MD0 in TMDR. Start count [6] [6] Set the CST bit in TSTR to 1 to start the count operation. Select counter clock Select counter clearing source Select waveform output level Set TGR Set PWM mode [1] [2] [3] [4] [5] Figure 10.20 Example of PWM Mode Setting Procedure (2) Examples of PWM Mode Operation Figure 10.21 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TGRB output value. In this case, the value set in TGRA is used as the cycle, and the value set in TGRB register as the duty cycle. TCNT value TGRA Counter cleared by TGRA compare match TGRB H'0000 TIOCA Time Figure 10.21 Example of PWM Mode Operation (1) Rev.1.00 Jun. 07, 2006 Page 553 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Figure 10.22 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), to output a 5-phase PWM waveform. In this case, the value set in TGRB_1 is used as the cycle, and the values set in the other TGRs as the duty cycle. TCNT value TGRB_1 TGRA_1 TGRD_0 TGRC_0 TGRB_0 TGRA_0 H'0000 Time TIOCA0 Counter cleared by TGRB_1 compare match TIOCB0 TIOCC0 TIOCD0 TIOCA1 Figure 10.22 Example of PWM Mode Operation (2) Rev.1.00 Jun. 07, 2006 Page 554 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Figure 10.23 shows examples of PWM waveform output with 0% duty cycle and 100% duty cycle in PWM mode. TCNT value TGRB changed TGRA TGRB H'0000 TGRB changed TGRB changed Time TIOCA 0% duty TCNT value TGRB changed TGRA Output does not change when compare matches in cycle register and duty register occur simultaneously TGRB changed TGRB H'0000 100% duty TGRB changed Time TIOCA TCNT value TGRB changed TGRA Output does not change when compare matches in cycle register and duty register occur simultaneously TGRB changed TGRB H'0000 100% duty 0% duty TGRB changed Time TIOCA Figure 10.23 Example of PWM Mode Operation (3) Rev.1.00 Jun. 07, 2006 Page 555 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.4.6 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR. However, the functions of bits CCLR1 and CCLR0 in TCR, and of TIOR, TIER, and TGR are valid, and input capture/compare match and interrupt functions can be used. This can be used for two-phase encoder pulse input. When overflow occurs while TCNT is counting up, the TCFV flag in TSR is set; when underflow occurs while TCNT is counting down, the TCFU flag is set. The TCFD bit in TSR is the count direction flag. Reading the TCFD flag provides an indication of whether TCNT is counting up or down. Table 10.32 shows the correspondence between external clock pins and channels. Table 10.32 Clock Input Pins in Phase Counting Mode External Clock Pins Channels When channel 1 or 5 is set to phase counting mode When channel 2 or 4 is set to phase counting mode A-Phase TCLKA TCLKC B-Phase TCLKB TCLKD Rev.1.00 Jun. 07, 2006 Page 556 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) (1) Example of Phase Counting Mode Setting Procedure Figure 10.24 shows an example of the phase counting mode setting procedure. Phase counting mode Select phase counting mode [1] [1] Select phase counting mode with bits MD3 to MD0 in TMDR. [2] Set the CST bit in TSTR to 1 to start the count operation. Start count [2] Figure 10.24 Example of Phase Counting Mode Setting Procedure (2) Examples of Phase Counting Mode Operation In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. Rev.1.00 Jun. 07, 2006 Page 557 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) (a) Phase counting mode 1 Figure 10.25 shows an example of phase counting mode 1 operation, and table 10.33 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count Time Figure 10.25 Example of Phase Counting Mode 1 Operation Table 10.33 Up/Down-Count Conditions in Phase Counting Mode 1 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level Low level High level High level Low level High level Low level [Legend] : Rising edge : Falling edge Down-count TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Up-count Rev.1.00 Jun. 07, 2006 Page 558 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) (b) Phase counting mode 2 Figure 10.26 shows an example of phase counting mode 2 operation, and table 10.34 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count Time Figure 10.26 Example of Phase Counting Mode 2 Operation Table 10.34 Up/Down-Count Conditions in Phase Counting Mode 2 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level Low level High level High level Low level High level Low level [Legend] : Rising edge : Falling edge TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Don't care Don't care Don't care Up-count Don't care Don't care Don't care Down-count Rev.1.00 Jun. 07, 2006 Page 559 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) (c) Phase counting mode 3 Figure 10.27 shows an example of phase counting mode 3 operation, and table 10.35 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count Time Figure 10.27 Example of Phase Counting Mode 3 Operation Table 10.35 Up/Down-Count Conditions in Phase Counting Mode 3 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level Low level High level High level Low level High level Low level [Legend] : Rising edge : Falling edge TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Don't care Don't care Don't care Up-count Down-count Don't care Don't care Don't care Rev.1.00 Jun. 07, 2006 Page 560 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) (d) Phase counting mode 4 Figure 10.28 shows an example of phase counting mode 4 operation, and table 10.36 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Down-count Up-count Time Figure 10.28 Example of Phase Counting Mode 4 Operation Table 10.36 Up/Down-Count Conditions in Phase Counting Mode 4 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level Low level High level High level Low level High level Low level [Legend] : Rising edge : Falling edge Don't care Down-count Don't care TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Up-count Rev.1.00 Jun. 07, 2006 Page 561 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) (3) Phase Counting Mode Application Example Figure 10.29 shows an example in which phase counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect the position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB. Channel 0 operates with TCNT counter clearing by TGRC_0 compare match; TGRA_0 and TGRC_0 are used for the compare match function and are set with the speed control cycle and position control cycle. TGRB_0 is used for input capture, with TGRB_0 and TGRD_0 operating in buffer mode. The channel 1 counter input clock is designated as the TGRB_0 input capture source, and the pulse width of 2-phase encoder 4-multiplication pulses is detected. TGRA_1 and TGRB_1 for channel 1 are designated for input capture, channel 0 TGRA_0 and TGRC_0 compare matches are selected as the input capture source, and the up/down-counter values for the control cycles are stored. This procedure enables accurate position/speed detection to be achieved. Channel 1 TCLKA TCLKB Edge detection circuit TCNT_1 TGRA_1 (speed cycle capture) TGRB_1 (position cycle capture) TCNT_0 + + - TGRA_0 (speed control cycle) TGRC_0 (position control cycle) TGRB_0 (pulse width capture) TGRD_0 (buffer operation) Channel 0 Figure 10.29 Phase Counting Mode Application Example Rev.1.00 Jun. 07, 2006 Page 562 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.5 Interrupt Sources There are three kinds of TPU interrupt sources: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disable bit, allowing generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The interrupt request is cleared by clearing the status flag to 0. Relative channel priority levels can be changed by the interrupt controller, but the priority within a channel is fixed. For details, see section 5, Interrupt Controller. Table 10.37 lists the TPU interrupt sources. Table 10.37 TPU Interrupts DTC DMAC Activa- Activation tion O O O O O O O O O O O O O O O O Channel Name 0 TGI0A TGI0B TGI0C TGI0D TCI0V 1 TGI1A TGI1B TCI1V TCI1U 2 TGI2A TGI2B TCI2V TCI2U 3 TGI3A TGI3B TGI3C TGI3D TCI3V Interrupt Source TGRA_0 input capture/compare match TGRB_0 input capture/compare match TGRC_0 input capture/compare match TGRD_0 input capture/compare match TCNT_0 overflow TGRA_1 input capture/compare match TGRB_1 input capture/compare match TCNT_1 overflow TCNT_1 underflow TGRA_2 input capture/compare match TGRB_2 input capture/compare match TCNT_2 overflow TCNT_2 underflow TGRA_3 input capture/compare match TGRB_3 input capture/compare match TGRC_3 input capture/compare match TGRD_3 input capture/compare match TCNT_3 overflow Interrupt Flag TGFA_0 TGFB_0 TGFC_0 TGFD_0 TCFV_0 TGFA_1 TGFB_1 TCFV_1 TCFU_1 TGFA_2 TGFB_2 TCFV_2 TCFU_2 TGFA_3 TGFB_3 TGFC_3 TGFD_3 TCFV_3 Rev.1.00 Jun. 07, 2006 Page 563 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Channel Name 4 TGI4A TGI4B TCI4V TCI4U 5 TGI5A TGI5B TCI5V TCI5U Interrupt Source TGRA_4 input capture/compare match TGRB_4 input capture/compare match TCNT_4 overflow TCNT_4 underflow TGRA_5 input capture/compare match TGRB_5 input capture/compare match TCNT_5 overflow TCNT_5 underflow Interrupt Flag TGFA_4 TGFB_4 TCFV_4 TCFU_4 TGFA_5 TGFB_5 TCFV_5 TCFU_5 DMAC DTC Activa- Activation tion O O O O O O [Legend] O : Possible : Not possible Note: This table shows the initial state immediately after a reset. The relative channel priority levels can be changed by the interrupt controller. (1) Input Capture/Compare Match Interrupt An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5. (2) Overflow Interrupt An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to 1 by the occurrence of a TCNT overflow on a channel. The interrupt request is cleared by clearing the TCFV flag to 0. The TPU has six overflow interrupts, one for each channel. (3) Underflow Interrupt An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to 1 by the occurrence of a TCNT underflow on a channel. The interrupt request is cleared by clearing the TCFU flag to 0. The TPU has four underflow interrupts, one each for channels 1, 2, 4, and 5. Rev.1.00 Jun. 07, 2006 Page 564 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.6 DTC Activation The DTC can be activated by the TGR input capture/compare match interrupt for a channel. For details, see section 8, Data Transfer Controller (DTC). A total of 16 TPU input capture/compare match interrupts can be used as DTC activation sources, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5. 10.7 DMAC Activation The DMAC can be activated by the TGRA input capture/compare match interrupt for a channel. For details, see section 7, DMA Controller (DMAC). A total of six TPU input capture/compare match interrupts can be used as DMAC activation sources, one for each channel. 10.8 A/D Converter Activation The TGRA input capture/compare match for each channel can activate the A/D converter. If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a TGRA input capture/compare match on a particular channel, a request to start A/D conversion is sent to the A/D converter. If the TPU conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is started. In the TPU, a total of six TGRA input capture/compare match interrupts can be used as A/D converter conversion start sources, one for each channel. Rev.1.00 Jun. 07, 2006 Page 565 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.9 10.9.1 (1) Operation Timing Input/Output Timing TCNT Count Timing Figure 10.30 shows TCNT count timing in internal clock operation, and figure 10.31 shows TCNT count timing in external clock operation. P Internal clock Falling edge Rising edge Falling edge TCNT input clock TCNT N-1 N N+1 N+2 Figure 10.30 Count Timing in Internal Clock Operation P External clock Falling edge Rising edge Falling edge TCNT input clock TCNT N-1 N N+1 N+2 Figure 10.31 Count Timing in External Clock Operation Rev.1.00 Jun. 07, 2006 Page 566 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) (2) Output Compare Output Timing A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin (TIOC pin). After a match between TCNT and TGR, the compare match signal is not generated until the TCNT input clock is generated. Figure 10.32 shows output compare output timing. P TCNT input clock N+1 TCNT N TGR N Compare match signal TIOC pin Figure 10.32 Output Compare Output Timing (3) Input Capture Signal Timing Figure 10.33 shows input capture signal timing. P Input capture input Input capture signal N N+1 N+2 N+2 TCNT TGR N Figure 10.33 Input Capture Input Signal Timing Rev.1.00 Jun. 07, 2006 Page 567 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) (4) Timing for Counter Clearing by Compare Match/Input Capture Figure 10.34 shows the timing when counter clearing by compare match occurrence is specified, and figure 10.35 shows the timing when counter clearing by input capture occurrence is specified. P Compare match signal Counter clear signal N H'0000 TCNT TGR N Figure 10.34 Counter Clear Timing (Compare Match) P Input capture signal Counter clear signal TCNT N H'0000 TGR N Figure 10.35 Counter Clear Timing (Input Capture) Rev.1.00 Jun. 07, 2006 Page 568 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) (5) Buffer Operation Timing Figures 10.36 and 10.37 show the timings in buffer operation. P TCNT Compare match signal TGRA, TGRB TGRC, TGRD n N N n n+1 Figure 10.36 Buffer Operation Timing (Compare Match) P Input capture signal TCNT N N+1 TGRA, TGRB n N N+1 TGRC, TGRD n N Figure 10.37 Buffer Operation Timing (Input Capture) Rev.1.00 Jun. 07, 2006 Page 569 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.9.2 (1) Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match Figure 10.38 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and the TGI interrupt request signal timing. P TCNT input clock TCNT N N+1 TGR Compare match signal TGF flag N TGI interrupt Figure 10.38 TGI Interrupt Timing (Compare Match) (2) TGF Flag Setting Timing in Case of Input Capture Figure 10.39 shows the timing for setting of the TGF flag in TSR by input capture occurrence, and the TGI interrupt request signal timing. P Input capture signal TCNT N TGR N TGF flag TGI interrupt Figure 10.39 TGI Interrupt Timing (Input Capture) Rev.1.00 Jun. 07, 2006 Page 570 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) (3) TCFV Flag/TCFU Flag Setting Timing Figure 10.40 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and the TCIV interrupt request signal timing. Figure 10.41 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and the TCIU interrupt request signal timing. P TCNT input clock TCNT (overflow) Overflow signal TCFV flag TCIV interrupt H'FFFF H'0000 Figure 10.40 TCIV Interrupt Setting Timing P TCNT input clock TCNT (underflow) H'0000 H'FFFF Underflow signal TCFU flag TCIU interrupt Figure 10.41 TCIU Interrupt Setting Timing Rev.1.00 Jun. 07, 2006 Page 571 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) (4) Status Flag Clearing Timing After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC or DMAC is activated, the flag is cleared automatically. Figure 10.42 shows the timing for status flag clearing by the CPU, and figures 10.43 and 10.44 show the timing for status flag clearing by the DTC or DMAC. TSR write cycle T1 T2 P TSR address Address Write Status flag Interrupt request signal Figure 10.42 Timing for Status Flag Clearing by CPU The status flag and interrupt request signal are cleared in synchronization with P after the DTC or DMAC transfer has started, as shown in figure 10.43. If conflict occurs for clearing the status flag and interrupt request signal due to activation of multiple DTC or DMAC transfers, it will take up to five clock cycles (P) for clearing them, as shown in figure 10.44. The next transfer request is masked for a longer period of either a period until the current transfer ends or a period for five clock cycles (P) from the beginning of the transfer. Note that in the DTC transfer, the status flag may be cleared during outputting the destination address. Rev.1.00 Jun. 07, 2006 Page 572 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) DTC/DMAC read cycle T2 T1 P DTC/DMAC write cycle T2 T1 Address Source address Destination address Status flag Period in which the next transfer request is masked Interrupt request signal Figure 10.43 Timing for Status Flag Clearing by DTC or DMAC Activation (1) DTC/DMAC read cycle P Address DTC/DMAC write cycle Source address Period in which the next transfer request is masked Destination address Status flag Period of flag clearing Interrupt request signal Period of interrupt request signal clearing Figure 10.44 Timing for Status Flag Clearing by DTC or DMAC Activation (2) Rev.1.00 Jun. 07, 2006 Page 573 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.10 Usage Notes 10.10.1 Module Stop State Setting Operation of the TPU can be disabled or enabled using the module stop control register. The initial setting is for operation of the TPU to be halted. Register access is enabled by clearing module stop state. For details, refer to section 23, Power-Down Modes. 10.10.2 Input Clock Restrictions The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a narrower pulse width. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure 10.45 shows the input clock conditions in phase counting mode. Phase Phase difference difference Overlap Overlap TCLKA (TCLKC) TCLKB (TCLKD) Pulse width Pulse width Pulse width Pulse width Note: Phase difference, Overlap 1.5 states Pulse width 2.5 states Figure 10.45 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode Rev.1.00 Jun. 07, 2006 Page 574 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.10.3 Caution on Cycle Setting When counter clearing by compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: f= P (N + 1) f: Counter frequency P: Operating frequency N: TGR set value 10.10.4 Conflict between TCNT Write and Clear Operations If the counter clearing signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 10.46 shows the timing in this case. TCNT write cycle T2 T1 P Address Write Counter clear signal TCNT N H'0000 TCNT address Figure 10.46 Conflict between TCNT Write and Clear Operations Rev.1.00 Jun. 07, 2006 Page 575 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.10.5 Conflict between TCNT Write and Increment Operations If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 10.47 shows the timing in this case. TCNT write cycle T2 T1 P Address Write TCNT input clock TCNT N TCNT write data M TCNT address Figure 10.47 Conflict between TCNT Write and Increment Operations 10.10.6 Conflict between TGR Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence and the compare match signal is disabled. A compare match also does not occur when the same value as before is written. Figure 10.48 shows the timing in this case. TGR write cycle T1 T2 P Address Write Compare match signal TCNT TGR N N TGR write data Disabled N+1 M TGR address Figure 10.48 Conflict between TGR Write and Compare Match Rev.1.00 Jun. 07, 2006 Page 576 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.10.7 Conflict between Buffer Register Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the write data. Figure 10.49 shows the timing in this case. TGR write cycle T1 T2 P Address Write Compare match signal Buffer register TGR N Data written to buffer register Buffer register address M M Figure 10.49 Conflict between Buffer Register Write and Compare Match Rev.1.00 Jun. 07, 2006 Page 577 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.10.8 Conflict between TGR Read and Input Capture If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data after input capture transfer. Figure 10.50 shows the timing in this case. TGR read cycle T1 T2 P Address Read Input capture signal TGR Internal data bus X TGR address M M Figure 10.50 Conflict between TGR Read and Input Capture Rev.1.00 Jun. 07, 2006 Page 578 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.10.9 Conflict between TGR Write and Input Capture If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 10.51 shows the timing in this case. TGR write cycle T2 T1 P Address Write Input capture signal TCNT TGR M M TGR address Figure 10.51 Conflict between TGR Write and Input Capture Rev.1.00 Jun. 07, 2006 Page 579 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.10.10 Conflict between Buffer Register Write and Input Capture If the input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 10.52 shows the timing in this case. Buffer register write cycle T2 T1 P Address Write Input capture signal TCNT TGR Buffer register N Buffer register address M N M Figure 10.52 Conflict between Buffer Register Write and Input Capture Rev.1.00 Jun. 07, 2006 Page 580 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.10.11 Conflict between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 10.53 shows the operation timing when a TGR compare match is specified as the clearing source, and H'FFFF is set in TGR. P TCNT input clock TCNT Counter clear signal TGF flag Disabled TCFV flag H'FFFF H'0000 Figure 10.53 Conflict between Overflow and Counter Clearing Rev.1.00 Jun. 07, 2006 Page 581 of 1102 REJ09B0294-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.10.12 Conflict between TCNT Write and Overflow/Underflow If an overflow/underflow occurs due to increment/decrement in the T2 state of a TCNT write cycle, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 10.54 shows the operation timing when there is conflict between TCNT write and overflow. TGR write cycle T2 T1 P Address TCNT address Write TCNT write data H'FFFF M TCNT TCFV flag Figure 10.54 Conflict between TCNT Write and Overflow 10.10.13 Multiplexing of I/O Pins In this LSI, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input pin with the TIOCB2 I/O pin. When an external clock is input, compare match output should not be performed from a multiplexed pin. 10.10.14 Interrupts and Module Stop Mode If module stop state is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DMAC or DTC activation source. Interrupts should therefore be disabled before entering module stop state. Rev.1.00 Jun. 07, 2006 Page 582 of 1102 REJ09B0294-0100 Section 11 Programmable Pulse Generator (PPG) Section 11 Programmable Pulse Generator (PPG) The programmable pulse generator (PPG) provides pulse outputs by using the 16-bit timer pulse unit (TPU) as a time base. The PPG pulse outputs are divided into 4-bit groups (groups 3 to 0) that can operate both simultaneously and independently. Figure 11.1 shows a block diagram of the PPG. 11.1 Features * 16-bit output data * Four output groups * Selectable output trigger signals * Non-overlapping mode * Can operate together with the data transfer controller (DTC) and DMA controller (DMAC) * Inverted output can be set * Module stop state specifiable Compare match signals NDERH Control logic PMR NDERL PCR PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 PO7 PO6 PO5 PO4 PO3 PO2 PO1 PO0 [Legend] PMR: PCR: NDERH: NDERL: Pulse output pins, group 3 PODRH Pulse output pins, group 2 Pulse output pins, group 1 PODRL Pulse output pins, group 0 NDRL NDRH Internal data bus PPG output mode register PPG output control register Next data enable register H Next data enable register L NDRH: NDRL: PODRH: PODRL: Next data register H Next data register L Output data register H Output data register L Figure 11.1 Block Diagram of PPG Rev.1.00 Jun. 07, 2006 Page 583 of 1102 REJ09B0294-0100 Section 11 Programmable Pulse Generator (PPG) 11.2 Input/Output Pins Table 11.1 shows the PPG pin configuration. Table 11.1 Pin Configuration Pin Name PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 PO7 PO6 PO5 PO4 PO3 PO2 PO1 PO0 I/O Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Group 0 pulse output Group 1 pulse output Group 2 pulse output Function Group 3 pulse output Rev.1.00 Jun. 07, 2006 Page 584 of 1102 REJ09B0294-0100 Section 11 Programmable Pulse Generator (PPG) 11.3 Register Descriptions The PPG has the following registers. * Next data enable register H (NDERH) * Next data enable register L (NDERL) * Output data register H (PODRH) * Output data register L (PODRL) * Next data register H (NDRH) * Next data register L (NDRL) * PPG output control register (PCR) * PPG output mode register (PMR) 11.3.1 Next Data Enable Registers H, L (NDERH, NDERL) NDERH and NDERL enable/disable pulse output on a bit-by-bit basis. * NDERH Bit Bit Name Initial Value R/W 7 NDER15 0 R/W 6 NDER14 0 R/W 5 NDER13 0 R/W 4 NDER12 0 R/W 3 NDER11 0 R/W 2 NDER10 0 R/W 1 NDER9 0 R/W 0 NDER8 0 R/W * NDERL Bit Bit Name Initial Value R/W 7 NDER7 0 R/W 6 NDER6 0 R/W 5 NDER5 0 R/W 4 NDER4 0 R/W 3 NDER3 0 R/W 2 NDER2 0 R/W 1 NDER1 0 R/W 0 NDER0 0 R/W Rev.1.00 Jun. 07, 2006 Page 585 of 1102 REJ09B0294-0100 Section 11 Programmable Pulse Generator (PPG) * NDERH Bit 7 6 5 4 3 2 1 0 Bit Name NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Next Data Enable 15 to 8 When a bit is set to 1, the value in the corresponding NDRH bit is transferred to the PODRH bit by the selected output trigger. Values are not transferred from NDRH to PODRH for cleared bits. * NDERL Bit 7 6 5 4 3 2 1 0 Bit Name NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Next Data Enable 7 to 0 When a bit is set to 1, the value in the corresponding NDRL bit is transferred to the PODRL bit by the selected output trigger. Values are not transferred from NDRL to PODRL for cleared bits. Rev.1.00 Jun. 07, 2006 Page 586 of 1102 REJ09B0294-0100 Section 11 Programmable Pulse Generator (PPG) 11.3.2 Output Data Registers H, L (PODRH, PODRL) PODRH and PODRL store output data for use in pulse output. A bit that has been set for pulse output by NDER is read-only and cannot be modified. * PODRH Bit Bit Name Initial Value R/W 7 POD15 0 R/W 6 POD14 0 R/W 5 POD13 0 R/W 4 POD12 0 R/W 3 POD11 0 R/W 2 POD10 0 R/W 1 POD9 0 R/W 0 POD8 0 R/W * PODRL Bit Bit Name Initial Value R/W 7 POD7 0 R/W 6 POD6 0 R/W 5 POD5 0 R/W 4 POD4 0 R/W 3 POD3 0 R/W 2 POD2 0 R/W 1 POD1 0 R/W 0 POD0 0 R/W * PODRH Bit 7 6 5 4 3 2 1 0 Bit Name POD15 POD14 POD13 POD12 POD11 POD10 POD9 POD8 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output Data Register 15 to 8 For bits which have been set to pulse output by NDERH, the output trigger transfers NDRH values to this register during PPG operation. While NDERH is set to 1, the CPU cannot write to this register. While NDERH is cleared, the initial output value of the pulse can be set. Rev.1.00 Jun. 07, 2006 Page 587 of 1102 REJ09B0294-0100 Section 11 Programmable Pulse Generator (PPG) * PODRL Bit 7 6 5 4 3 2 1 0 Bit Name POD7 POD6 POD5 POD4 POD3 POD2 POD1 POD0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output Data Register 7 to 0 For bits which have been set to pulse output by NDERL, the output trigger transfers NDRL values to this register during PPG operation. While NDERL is set to 1, the CPU cannot write to this register. While NDERL is cleared, the initial output value of the pulse can be set. 11.3.3 Next Data Registers H, L (NDRH, NDRL) NDRH and NDRL store the next data for pulse output. The NDR addresses differ depending on whether pulse output groups have the same output trigger or different output triggers. * NDRH Bit Bit Name Initial Value R/W 7 NDR15 0 R/W 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W 3 NDR11 0 R/W 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W * NDRL Bit Bit Name Initial Value R/W 7 NDR7 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W 3 NDR3 0 R/W 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W Rev.1.00 Jun. 07, 2006 Page 588 of 1102 REJ09B0294-0100 Section 11 Programmable Pulse Generator (PPG) * NDRH If pulse output groups 2 and 3 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below. Bit 7 6 5 4 3 2 1 0 Bit Name NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Next Data Register 15 to 8 The register contents are transferred to the corresponding PODRH bits by the output trigger specified with PCR. If pulse output groups 2 and 3 have different output triggers, the upper four bits and lower four bits are mapped to different addresses as shown below. Bit 7 6 5 4 3 to 0 Bit Name NDR15 NDR14 NDR13 NDR12 Initial Value 0 0 0 0 All 1 R/W R/W R/W R/W R/W Description Next Data Register 15 to 12 The register contents are transferred to the corresponding PODRH bits by the output trigger specified with PCR. Reserved These bits are always read as 1 and cannot be modified. Bit 7 to 4 3 2 1 0 Bit Name NDR11 NDR10 NDR9 NDR8 Initial Value All 1 0 0 0 0 R/W R/W R/W R/W R/W Description Reserved These bits are always read as 1 and cannot be modified. Next Data Register 11 to 8 The register contents are transferred to the corresponding PODRH bits by the output trigger specified with PCR. Rev.1.00 Jun. 07, 2006 Page 589 of 1102 REJ09B0294-0100 Section 11 Programmable Pulse Generator (PPG) * NDRL If pulse output groups 0 and 1 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below. Bit 7 6 5 4 3 2 1 0 Bit Name NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Next Data Register 7 to 0 The register contents are transferred to the corresponding PODRL bits by the output trigger specified with PCR. If pulse output groups 0 and 1 have different output triggers, the upper four bits and lower four bits are mapped to different addresses as shown below. Bit 7 6 5 4 3 to 0 Bit Name NDR7 NDR6 NDR5 NDR4 Initial Value 0 0 0 0 All 1 R/W R/W R/W R/W R/W Description Next Data Register 7 to 4 The register contents are transferred to the corresponding PODRL bits by the output trigger specified with PCR. Reserved These bits are always read as 1 and cannot be modified. Bit 7 to 4 3 2 1 0 Bit Name NDR3 NDR2 NDR1 NDR0 Initial Value All 1 0 0 0 0 R/W R/W R/W R/W R/W Description Reserved These bits are always read as 1 and cannot be modified. Next Data Register 3 to 0 The register contents are transferred to the corresponding PODRL bits by the output trigger specified with PCR. Rev.1.00 Jun. 07, 2006 Page 590 of 1102 REJ09B0294-0100 Section 11 Programmable Pulse Generator (PPG) 11.3.4 PPG Output Control Register (PCR) PCR selects output trigger signals on a group-by-group basis. For details on output trigger selection, refer to section 11.3.5, PPG Output Mode Register (PMR). Bit Bit Name Initial Value R/W 7 G3CMS1 1 R/W 6 G3CMS0 1 R/W 5 G2CMS1 1 R/W 4 G2CMS0 1 R/W 3 G1CMS1 1 R/W 2 G1CMS0 1 R/W 1 G0CMS1 1 R/W 0 G0CMS0 1 R/W Bit 7 6 Bit Name G3CMS1 G3CMS0 Initial Value 1 1 R/W R/W R/W Description Group 3 Compare Match Select 1 and 0 These bits select output trigger of pulse output group 3. 00: Compare match in TPU channel 0 01: Compare match in TPU channel 1 10: Compare match in TPU channel 2 11: Compare match in TPU channel 3 5 4 G2CMS1 G2CMS0 1 1 R/W R/W Group 2 Compare Match Select 1 and 0 These bits select output trigger of pulse output group 2. 00: Compare match in TPU channel 0 01: Compare match in TPU channel 1 10: Compare match in TPU channel 2 11: Compare match in TPU channel 3 3 2 G1CMS1 G1CMS0 1 1 R/W R/W Group 1 Compare Match Select 1 and 0 These bits select output trigger of pulse output group 1. 00: Compare match in TPU channel 0 01: Compare match in TPU channel 1 10: Compare match in TPU channel 2 11: Compare match in TPU channel 3 1 0 G0CMS1 G0CMS0 1 1 R/W R/W Group 0 Compare Match Select 1 and 0 These bits select output trigger of pulse output group 0. 00: Compare match in TPU channel 0 01: Compare match in TPU channel 1 10: Compare match in TPU channel 2 11: Compare match in TPU channel 3 Rev.1.00 Jun. 07, 2006 Page 591 of 1102 REJ09B0294-0100 Section 11 Programmable Pulse Generator (PPG) 11.3.5 PPG Output Mode Register (PMR) PMR selects the pulse output mode of the PPG for each group. If inverted output is selected, a low-level pulse is output when PODRH is 1 and a high-level pulse is output when PODRH is 0. If non-overlapping operation is selected, PPG updates its output values at compare match A or B of the TPU that becomes the output trigger. For details, refer to section 11.4.4, Non-Overlapping Pulse Output. Bit Bit Name Initial Value R/W 7 G3INV 1 R/W 6 G2INV 1 R/W 5 G1INV 1 R/W 4 G0INV 1 R/W 3 G3NOV 0 R/W 2 G2NOV 0 R/W 1 G1NOV 0 R/W 0 G0NOV 0 R/W Bit 7 Bit Name G3INV Initial Value 1 R/W R/W Description Group 3 Inversion Selects direct output or inverted output for pulse output group 3. 0: Inverted output 1: Direct output 6 G2INV 1 R/W Group 2 Inversion Selects direct output or inverted output for pulse output group 2. 0: Inverted output 1: Direct output 5 G1INV 1 R/W Group 1 Inversion Selects direct output or inverted output for pulse output group 1. 0: Inverted output 1: Direct output 4 G0INV 1 R/W Group 0 Inversion Selects direct output or inverted output for pulse output group 0. 0: Inverted output 1: Direct output Rev.1.00 Jun. 07, 2006 Page 592 of 1102 REJ09B0294-0100 Section 11 Programmable Pulse Generator (PPG) Bit 3 Bit Name G3NOV Initial Value 0 R/W R/W Description Group 3 Non-Overlap Selects normal or non-overlapping operation for pulse output group 3. 0: Normal operation (output values updated at compare match A in the selected TPU channel) 1: Non-overlapping operation (output values updated at compare match A or B in the selected TPU channel) 2 G2NOV 0 R/W Group 2 Non-Overlap Selects normal or non-overlapping operation for pulse output group 2. 0: Normal operation (output values updated at compare match A in the selected TPU channel) 1: Non-overlapping operation (output values updated at compare match A or B in the selected TPU channel) 1 G1NOV 0 R/W Group 1 Non-Overlap Selects normal or non-overlapping operation for pulse output group 1. 0: Normal operation (output values updated at compare match A in the selected TPU channel) 1: Non-overlapping operation (output values updated at compare match A or B in the selected TPU channel) 0 G0NOV 0 R/W Group 0 Non-Overlap Selects normal or non-overlapping operation for pulse output group 0. 0: Normal operation (output values updated at compare match A in the selected TPU channel) 1: Non-overlapping operation (output values updated at compare match A or B in the selected TPU channel) Rev.1.00 Jun. 07, 2006 Page 593 of 1102 REJ09B0294-0100 Section 11 Programmable Pulse Generator (PPG) 11.4 Operation Figure 11.2 shows a schematic diagram of the PPG. PPG pulse output is enabled when the corresponding bits in NDER are set to 1. An initial output value is determined by its corresponding PODR initial setting. When the compare match event specified by PCR occurs, the corresponding NDR bit contents are transferred to PODR to update the output values. Sequential output of data of up to 16 bits is possible by writing new output data to NDR before the next compare match. NDER Q Output trigger signal C Q PODR D Pulse output pin Normal output/inverted output Q NDR D Internal data bus Figure 11.2 Schematic Diagram of PPG 11.4.1 Output Timing If pulse output is enabled, the NDR contents are transferred to PODR and output when the specified compare match event occurs. Figure 11.3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match A. P TCNT TGRA Compare match A signal NDRH PODRH PO8 to PO15 m m n n n N N N+1 Figure 11.3 Timing of Transfer and Output of NDR Contents (Example) Rev.1.00 Jun. 07, 2006 Page 594 of 1102 REJ09B0294-0100 Section 11 Programmable Pulse Generator (PPG) 11.4.2 Sample Setup Procedure for Normal Pulse Output Figure 11.4 shows a sample procedure for setting up normal pulse output. [1] [2] [3] Set TGRA value TPU setup Set counting operation Select interrupt request Set initial output data Enable pulse output PPG setup Select output trigger Set next pulse output data TPU setup Start counter Compare match? Yes Set next pulse output data [10] [7] [3] [4] [4] [5] [6] [5] [6] [7] [8] [9] [9] No [2] Set TIOR to make TGRA an output compare register (with output disabled). Set the PPG output trigger cycle. Select the counter clock source with bits TPSC2 to TPSC0 in TCR. Select the counter clear source with bits CCLR1 and CCLR0. Enable the TGIA interrupt in TIER. The DTC or DMAC can also be set up to transfer data to NDR. Set the initial output values in PODR. Set the bits in NDER for the pins to be used for pulse output to 1. Select the TPU compare match event to be used as the output trigger in PCR. Set the next pulse output values in NDR. Set the CST bit in TSTR to 1 to start the TCNT counter. Normal PPG output Select TGR functions [1] [8] [10] At each TGIA interrupt, set the next output values in NDR. Figure 11.4 Setup Procedure for Normal Pulse Output (Example) Rev.1.00 Jun. 07, 2006 Page 595 of 1102 REJ09B0294-0100 Section 11 Programmable Pulse Generator (PPG) 11.4.3 Example of Normal Pulse Output (Example of 5-Phase Pulse Output) Figure 11.5 shows an example in which pulse output is used for cyclic 5-phase pulse output. TCNT value TGRA TCNT Compare match H'0000 NDRH 80 C0 40 60 20 30 10 18 08 88 80 C0 40 Time PODRH 00 80 C0 40 60 20 30 10 18 08 88 80 C0 PO15 PO14 PO13 PO12 PO11 Figure 11.5 Normal Pulse Output Example (5-Phase Pulse Output) 1. Set up TGRA in TPU which is used as the output trigger to be an output compare register. Set a cycle in TGRA so the counter will be cleared by compare match A. Set the TGIEA bit in TIER to 1 to enable the compare match/input capture A (TGIA) interrupt. 2. Write H'F8 to NDERH, and set bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 in PCR to select compare match in the TPU channel set up in the previous step to be the output trigger. Write output data H'80 in NDRH. 3. The timer counter in the TPU channel starts. When compare match A occurs, the NDRH contents are transferred to PODRH and output. The TGIA interrupt handling routine writes the next output data (H'C0) in NDRH. 4. 5-phase pulse output (one or two phases active at a time) can be obtained subsequently by writing H'40, H'60, H'20, H'30, H'10, H'18, H'08, H'88... at successive TGIA interrupts. If the DTC or DMAC is set for activation by the TGIA interrupt, pulse output can be obtained without imposing a load on the CPU. Rev.1.00 Jun. 07, 2006 Page 596 of 1102 REJ09B0294-0100 Section 11 Programmable Pulse Generator (PPG) 11.4.4 Non-Overlapping Pulse Output During non-overlapping operation, transfer from NDR to PODR is performed as follows: * At compare match A, the NDR bits are always transferred to PODR. * At compare match B, the NDR bits are transferred only if their value is 0. The NDR bits are not transferred if their value is 1. Figure 11.6 illustrates the non-overlapping pulse output operation. NDER Q Compare match A Compare match B Pulse output pin C Q PODR D Q NDR D Internal data bus Normal output/inverted output Figure 11.6 Non-Overlapping Pulse Output Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before compare match A. The NDR contents should not be altered during the interval from compare match B to compare match A (the non-overlapping margin). This can be accomplished by having the TGIA interrupt handling routine write the next data in NDR, or by having the TGIA interrupt activate the DTC or DMAC. Note, however, that the next data must be written before the next compare match B occurs. Rev.1.00 Jun. 07, 2006 Page 597 of 1102 REJ09B0294-0100 Section 11 Programmable Pulse Generator (PPG) Figure 11.7 shows the timing of this operation. Compare match A Compare match B Write to NDR NDR Write to NDR PODR 0 output 0/1 output 0 output 0/1 output Write to NDR here Write to NDR Do not write here to NDR here Do not write to NDR here Figure 11.7 Non-Overlapping Operation and NDR Write Timing Rev.1.00 Jun. 07, 2006 Page 598 of 1102 REJ09B0294-0100 Section 11 Programmable Pulse Generator (PPG) 11.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output Figure 11.8 shows a sample procedure for setting up non-overlapping pulse output. Non-overlapping pulse output Select TGR functions Set TGR values TPU setup Set counting operation Select interrupt request Set initial output data Enable pulse output Select output trigger Set non-overlapping groups Set next pulse output data TPU setup Start counter Compare match A? Yes Set next pulse output data [11] [3] [4] [4] [5] [6] [7] [8] [7] [5] [6] PPG setup [1] [2] [3] [1] Set TIOR to make TGRA and TGRB output compare registers (with output disabled). Set the pulse output trigger cycle in TGRB and the non-overlapping margin in TGRA. Select the counter clock source with bits TPSC2 to TPSC0 in TCR. Select the counter clear source with bits CCLR1 and CCLR0. Enable the TGIA interrupt in TIER. The DTC or DMAC can also be set up to transfer data to NDR. Set the initial output values in PODR. Set the bits in NDER for the pins to be used for pulse output to 1. Select the TPU compare match event to be used as the pulse output trigger in PCR. In PMR, select the groups that will operate in non-overlapping mode. Set the next pulse output values in NDR. [2] [9] [8] [9] [10] No [10] Set the CST bit in TSTR to 1 to start the TCNT counter. [11] At each TGIA interrupt, set the next output values in NDR. Figure 11.8 Setup Procedure for Non-Overlapping Pulse Output (Example) Rev.1.00 Jun. 07, 2006 Page 599 of 1102 REJ09B0294-0100 Section 11 Programmable Pulse Generator (PPG) 11.4.6 Example of Non-Overlapping Pulse Output (Example of 4-Phase Complementary Non-Overlapping Pulse Output) Figure 11.9 shows an example in which pulse output is used for 4-phase complementary nonoverlapping pulse output. TCNT value TGRB TGRA H'0000 NDRH 95 65 59 56 95 65 Time TCNT PODRH 00 95 05 65 41 59 50 56 14 95 05 65 Non-overlapping margin PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Figure 11.9 Non-Overlapping Pulse Output Example (4-Phase Complementary) Rev.1.00 Jun. 07, 2006 Page 600 of 1102 REJ09B0294-0100 Section 11 Programmable Pulse Generator (PPG) 1. Set up the TPU channel to be used as the output trigger channel so that TGRA and TGRB are output compare registers. Set the cycle in TGRB and the non-overlapping margin in TGRA, and set the counter to be cleared by compare match B. Set the TGIEA bit in TIER to 1 to enable the TGIA interrupt. 2. Write H'FF to NDERH, and set bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 in PCR to select compare match in the TPU channel set up in the previous step to be the output trigger. Set bits G3NOV and G2NOV in PMR to 1 to select non-overlapping pulse output. Write output data H'95 to NDRH. 3. The timer counter in the TPU channel starts. When a compare match with TGRB occurs, outputs change from 1 to 0. When a compare match with TGRA occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed by the value set in TGRA). The TGIA interrupt handling routine writes the next output data (H'65) to NDRH. 4. 4-phase complementary non-overlapping pulse output can be obtained subsequently by writing H'59, H'56, H'95... at successive TGIA interrupts. If the DTC or DMAC is set for activation by a TGIA interrupt, pulse can be output without imposing a load on the CPU. Rev.1.00 Jun. 07, 2006 Page 601 of 1102 REJ09B0294-0100 Section 11 Programmable Pulse Generator (PPG) 11.4.7 Inverted Pulse Output If the G3INV, G2INV, G1INV, and G0INV bits in PMR are cleared to 0, values that are the inverse of the PODR contents can be output. Figure 11.10 shows the outputs when the G3INV and G2INV bits are cleared to 0, in addition to the settings of figure 11.9. TCNT value TGRB TCNT TGRA H'0000 NDRH 95 65 59 56 95 65 Time PODRL 00 95 05 65 41 59 50 56 14 95 05 65 PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Figure 11.10 Inverted Pulse Output (Example) Rev.1.00 Jun. 07, 2006 Page 602 of 1102 REJ09B0294-0100 Section 11 Programmable Pulse Generator (PPG) 11.4.8 Pulse Output Triggered by Input Capture Pulse output can be triggered by TPU input capture as well as by compare match. If TGRA functions as an input capture register in the TPU channel selected by PCR, pulse output will be triggered by the input capture signal. Figure 11.11 shows the timing of this output. P TIOC pin Input capture signal NDR N PODR M N PO M N Figure 11.11 Pulse Output Triggered by Input Capture (Example) Rev.1.00 Jun. 07, 2006 Page 603 of 1102 REJ09B0294-0100 Section 11 Programmable Pulse Generator (PPG) 11.5 11.5.1 Usage Notes Module Stop State Setting PPG operation can be disabled or enabled using the module stop control register. The initial value is for PPG operation to be halted. Register access is enabled by clearing the module stop state. For details, refer to section 23, Power-Down Modes. 11.5.2 Operation of Pulse Output Pins Pins PO0 to PO15 are also used for other peripheral functions such as the TPU. When output by another peripheral function is enabled, the corresponding pins cannot be used for pulse output. Note, however, that data transfer from NDR bits to PODR bits takes place, regardless of the usage of the pins. Pin functions should be changed only under conditions in which the output trigger event will not occur. Rev.1.00 Jun. 07, 2006 Page 604 of 1102 REJ09B0294-0100 Section 12 8-Bit Timers (TMR) Section 12 8-Bit Timers (TMR) This LSI has four units (unit 0 to unit 3) of an on-chip 8-bit timer module that comprise two 8-bit counter channels, totaling eight channels. The 8-bit timer module can be used to count external events and also be used as a multifunction timer in a variety of applications, such as generation of counter reset, interrupt requests, and pulse output with a desired duty cycle using a compare-match signal with two registers. Figures 12.1 to 12.4 show block diagrams of the 8-bit timer module (unit 0 to unit 3). This section describes unit 0 (channels 0 and 1) and unit 2 (channels 4 and 5), both of which have the same functions. Unit2 and unit 3 can generate baud rate clock for SCI and have the same functions. 12.1 Features * Selection of seven clock sources The counters can be driven by one of six internal clock signals (P/2, P/8, P/32, P/64, P/1024, or P/8192) or an external clock input (only internal clock available in units 2 and 3: P, P/2, P/8, P/32, P/64, P/1024, and P/8192). * Selection of three ways to clear the counters The counters can be cleared on compare match A or B, or by an external reset signal. (This is available only in unit 0 and unit 1.) * Timer output control by a combination of two compare match signals The timer output signal in each channel is controlled by a combination of two independent compare match signals, enabling the timer to output pulses with a desired duty cycle or PWM output. * Cascading of two channels Operation as a 16-bit timer is possible, using TMR_0 for the upper 8 bits and TMR_1 for the lower 8 bits (16-bit count mode). TMR_1 can be used to count TMR_0 compare matches (compare match count mode). * Three interrupt sources Compare match A, compare match B, and overflow interrupts can be requested independently. (This is available only in unit 0 and unit 1.) * Generation of trigger to start A/D converter conversion (available in unit 0 and unit 1 only) * Capable of generating baud rate clock for SCI_5 and SCI_6. (This is available only in unit 2 and unit 3). For details, see section 15, Serial Communication Interface (SCI, IrDA, CRC). * Module stop state specifiable Rev.1.00 Jun. 07, 2006 Page 605 of 1102 REJ09B0294-0100 Section 12 8-Bit Timers (TMR) Internal clocks P/2 P/8 P/32 P/64 P/1024 P/8192 External clocks TMCI0 TMCI1 Clock select TCORA_0 Compare match A1 Compare match A0 Comparator A_0 TCORA_1 Counter clock 1 Counter clock 0 Comparator A_1 TMO0 TMO1 Overflow 1 Overflow 0 Counter clear 0 Counter clear 1 Compare match B1 Compare match B0 Control logic TCNT_0 TCNT_1 Internal bus Comparator B_0 Comparator B_1 TMRI0 TMRI1 A/D conversion start request signal TCORB_0 TCORB_1 TCSR_0 TCR_0 TCSR_1 TCR_1 TCCR_0 CMIA0 CMIA1 CMIB0 CMIB1 OVI0 OVI1 Interrupt signals [Legend] TCORA_0: TCNT_0: TCORB_0: TCSR_0: TCR_0: TCCR_0: Channel 0 (TMR_0) TCCR_1 Channel 1 (TMR_1) Time constant register A_0 Timer counter_0 Time constant register B_0 Timer control/status register_0 Timer control register_0 Timer counter control register_0 TCORA_1: TCNT_1: TCORB_1: TCSR_1: TCR_1: TCCR_1: Time constant register A_1 Timer counter_1 Time constant register B_1 Timer control/status register_1 Timer control register_1 Timer counter control register_1 Figure 12.1 Block Diagram of 8-Bit Timer Module (Unit 0) Rev.1.00 Jun. 07, 2006 Page 606 of 1102 REJ09B0294-0100 Section 12 8-Bit Timers (TMR) Internal clocks P/2 P/8 P/32 P/64 P/1024 P/8192 External clocks TMCI2 TMCI3 Clock select TCORA_2 Compare match A3 Compare match A2 Comparator A_2 TCORA_3 Counter clock 3 Counter clock 2 Comparator A_3 TMO2 TMO3 Overflow 3 Overflow 2 Counter clear 2 Counter clear 3 Compare match B3 Compare match B2 Control logic TCNT_2 TCNT_3 Internal bus Comparator B_2 Comparator B_3 TMRI2 TMRI3 A/D conversion start request signal TCORB_2 TCORB_3 TCSR_2 TCR_2 TCSR_3 TCR_3 TCCR_2 CMIA2 CMIA3 CMIB2 CMIB3 OVI2 OVI3 Interrupt signals [Legend] TCORA_2: TCNT_2: TCORB_2: TCSR_2: TCR_2: TCCR_2: Time constant register A_2 Timer counter_2 Time constant register B_2 Timer control/status register_2 Timer control register_2 Timer counter control register_2 TCORA_3: TCNT_3: TCORB_3: TCSR_3: TCR_3: TCCR_3: Channel 2 (TMR_2) TCCR_3 Channel 3 (TMR_3) Time constant register A_3 Timer counter_3 Time constant register B_3 Timer control/status register_3 Timer control register_3 Timer counter control register_3 Figure 12.2 Block Diagram of 8-Bit Timer Module (Unit 1) Rev.1.00 Jun. 07, 2006 Page 607 of 1102 REJ09B0294-0100 Section 12 8-Bit Timers (TMR) Internal clocks P P/2 P/8 P/32 P/64 P/1024 P/8192 Counter clock 5 Counter clock 4 Clock select TCORA_4 Compare match A5 Compare match A4 Comparator A_4 TCORA_5 Comparator A_5 Overflow 5 Overflow 4 Counter clear 4 Counter clear5 Compare match B5 Compare match B4 Control logic TCNT_4 TCNT_5 Internal bus To SCI_5 TMO4 TMO5 Comparator B_4 Comparator B_5 TCORB_4 TCORB_5 TCSR_4 TCR_4 TCSR_5 TCR_5 TCCR_4 Channel 4 (TMR_4) CMIA4 CMIB4 CMIA5 CMIB5 Interrupt signals [Legend] TCORA_4: TCNT_4: TCORB_4: TCSR_4: TCR_4: TCCR_4: Time constant register A_4 Timer counter_4 Time constant register B_4 Timer control/status register_4 Timer control register_4 Timer counter control register_4 TCORA_5: TCNT_5: TCORB_5: TCSR_5: TCR_5: TCCR_5: CMI4 CMI5 TCCR_5 Channel 5 (TMR_5) Time constant register A_5 Timer counter_5 Time constant register B_5 Timer control/status register_5 Timer control register_5 Timer counter control register_5 Figure 12.3 Block Diagram of 8-Bit Timer Module (Unit 2) Rev.1.00 Jun. 07, 2006 Page 608 of 1102 REJ09B0294-0100 Section 12 8-Bit Timers (TMR) Internal clocks P P/2 P/8 P/32 P/64 P/1024 P/8192 Counter clock 7 Counter clock 6 Clock select TCORA_6 Compare match A7 Compare match A6 Comparator A_6 TCORA_7 Comparator A_7 Overflow 7 Overflow 6 Counter clear 6 Counter clear 7 Compare match B7 Compare match B6 Control logic TCNT_6 TCNT_7 Internal bus To SCI_6 TMO6 TMO7 Comparator B_6 Comparator B_7 TCORB_6 TCORB_7 TCSR_6 TCR_6 TCSR_7 TCR_7 TCCR_6 Channel 6 (TMR_6) CMIA6 CMIB6 CMIA7 CMIB7 Interrupt signals [Legend] TCORA_6: TCNT_6: TCORB_6: TCSR_6: TCR_6: TCCR_6: Time constant register A_6 Timer counter_6 Time constant register B_6 Timer control/status register_6 Timer control register_6 Timer counter control register_6 TCORA_7: TCNT_7: TCORB_7: TCSR_7: TCR_7: TCCR_7: CMI6 CMI7 TCCR_7 Channel 7 (TMR_7) Time constant register A_7 Timer counter_7 Time constant register B_7 Timer control/status register_7 Timer control register_7 Timer counter control register_7 Figure 12.4 Block Diagram of 8-Bit Timer Module (Unit 3) Rev.1.00 Jun. 07, 2006 Page 609 of 1102 REJ09B0294-0100 Section 12 8-Bit Timers (TMR) 12.2 Input/Output Pins Table 12.1 shows the pin configuration of the TMR. Table 12.1 Pin Configuration Unit 0 Channel Name 0 Timer output pin Timer clock input pin Timer reset input pin 1 Timer output pin Timer clock input pin Timer reset input pin 1 2 Timer output pin Timer clock input pin Timer reset input pin 3 Timer output pin Timer clock input pin Timer reset input pin 2 4 5 3 6 7 Symbol TMO0 TMCI0 TMRI0 TMO1 TMCI1 TMRI1 TMO2 TMCI2 TMRI2 TMO3 TMCI3 TMRI3 I/O Function Output Outputs compare match Input Input Inputs external clock for counter Inputs external reset to counter Output Outputs compare match Input Input Inputs external clock for counter Inputs external reset to counter Output Outputs compare match Input Input Inputs external clock for counter Inputs external reset to counter Output Outputs compare match Input Input Inputs external clock for counter Inputs external reset to counter Rev.1.00 Jun. 07, 2006 Page 610 of 1102 REJ09B0294-0100 Section 12 8-Bit Timers (TMR) 12.3 Register Descriptions The TMR has the following registers. Unit 0: * Channel 0 (TMR_0): Timer counter_0 (TCNT_0) Time constant register A_0 (TCORA_0) Time constant register B_0 (TCORB_0) Timer control register_0 (TCR_0) Timer counter control register_0 (TCCR_0) Timer control/status register_0 (TCSR_0) * Channel 1 (TMR_1): Timer counter_1 (TCNT_1) Time constant register A_1 (TCORA_1) Time constant register B_1 (TCORB_1) Timer control register_1 (TCR_1) Timer counter control register_1 (TCCR_1) Timer control/status register_1 (TCSR_1) Unit 1: * Channel 2 (TMR_2): Timer counter_2 (TCNT_2) Time constant register A_2 (TCORA_2) Time constant register B_2 (TCORB_2) Timer control register_2 (TCR_2) Timer counter control register_2 (TCCR_2) Timer control/status register_2 (TCSR_2) * Channel 3 (TMR_3): Timer counter_3 (TCNT_3) Time constant register A_3 (TCORA_3) Time constant register B_3 (TCORB_3) Timer control register_3 (TCR_3) Timer counter control register_3 (TCCR_3) Timer control/status register_3 (TCSR_3) Rev.1.00 Jun. 07, 2006 Page 611 of 1102 REJ09B0294-0100 Section 12 8-Bit Timers (TMR) Unit 2: * Channel 4 (TMR_4): Timer counter_4 (TCNT_4) Time constant register A_4 (TCORA_4) Time constant register B_4 (TCORB_4) Timer control register_4 (TCR_4) Timer counter control register_4 (TCCR_4) Timer control/status register_4 (TCSR_4) * Channel 5 (TMR_5): Timer counter_5 (TCNT_5) Time constant register A_5 (TCORA_5) Time constant register B_5 (TCORB_5) Timer control register_5 (TCR_5) Timer counter control register_5 (TCCR_5) Timer control/status register_5 (TCSR_5) Unit 3: * Channel 6 (TMR_6): Timer counter_6 (TCNT_6) Time constant register A_6 (TCORA_6) Time constant register B_6 (TCORB_6) Timer control register_6 (TCR_6) Timer counter control register_6 (TCCR_6) Timer control/status register_6 (TCSR_6) * Channel 7 (TMR_7): Timer counter_7 (TCNT_7) Time constant register A_7 (TCORA_7) Time constant register B_7 (TCORB_7) Timer control register_7 (TCR_7) Timer counter control register_7 (TCCR_7) Timer control/status register_7 (TCSR_7) Rev.1.00 Jun. 07, 2006 Page 612 of 1102 REJ09B0294-0100 Section 12 8-Bit Timers (TMR) 12.3.1 Timer Counter (TCNT) TCNT is an 8-bit readable/writable up-counter. TCNT_0 and TCNT_1 comprise a single 16-bit register so they can be accessed together by a word transfer instruction. Bits CKS2 to CKS0 in TCR and bits ICKS1 and ICKS0 in TCCR are used to select a clock. TCNT can be cleared by an external reset input signal, compare match A signal, or compare match B signal. Which signal to be used for clearing is selected by bits CCLR1 and CCLR0 in TCR. When TCNT overflows from H'FF to H'00, bit OVF in TCSR is set to 1. TCNT is initialized to H'00. TCNT_0 4 3 TCNT_1 4 3 Bit Bit Name Initial Value R/W 7 6 5 2 1 0 7 6 5 2 1 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 12.3.2 Time Constant Register A (TCORA) TCORA is an 8-bit readable/writable register. TCORA_0 and TCORA_1 comprise a single 16-bit register so they can be accessed together by a word transfer instruction. The value in TCORA is continually compared with the value in TCNT. When a match is detected, the corresponding CMFA flag in TCSR is set to 1. Note however that comparison is disabled during the T2 state of a TCORA write cycle. The timer output from the TMO pin can be freely controlled by this compare match signal (compare match A) and the settings of bits OS1 and OS0 in TCSR. TCORA is initialized to H'FF. TCORA_0 4 3 TCORA_1 4 3 Bit Bit Name Initial Value R/W 7 6 5 2 1 0 7 6 5 2 1 0 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Rev.1.00 Jun. 07, 2006 Page 613 of 1102 REJ09B0294-0100 Section 12 8-Bit Timers (TMR) 12.3.3 Time Constant Register B (TCORB) TCORB is an 8-bit readable/writable register. TCORB_0 and TCORB_1 comprise a single 16-bit register so they can be accessed together by a word transfer instruction. TCORB is continually compared with the value in TCNT. When a match is detected, the corresponding CMFB flag in TCSR is set to 1. Note however that comparison is disabled during the T2 state of a TCORB write cycle. The timer output from the TMO pin can be freely controlled by this compare match signal (compare match B) and the settings of bits OS3 and OS2 in TCSR. TCORB is initialized to H'FF. TCORB_0 4 3 TCORB_1 4 3 Bit Bit Name Initial Value R/W 7 6 5 2 1 0 7 6 5 2 1 0 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 12.3.4 Timer Control Register (TCR) TCR selects the TCNT clock source and the condition for clearing TCNT, and enables/disables interrupt requests. Bit Bit Name Initial Value R/W 7 CMIEB 0 R/W 6 CMIEA 0 R/W 5 OVIE 0 R/W 4 CCLR1 0 R/W 3 CCLR0 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Bit 7 Bit Name CMIEB Initial Value 0 R/W R/W Description Compare Match Interrupt Enable B Selects whether CMFB interrupt requests (CMIB) are enabled or disabled when the CMFB flag in TCSR is set 2 to 1. * 0: CMFB interrupt requests (CMIB) are disabled 1: CMFB interrupt requests (CMIB) are enabled Rev.1.00 Jun. 07, 2006 Page 614 of 1102 REJ09B0294-0100 Section 12 8-Bit Timers (TMR) Bit 6 Bit Name CMIEA Initial Value 0 R/W R/W Description Compare Match Interrupt Enable A Selects whether CMFA interrupt requests (CMIA) are enabled or disabled when the CMFA flag in TCSR is set 2 to 1. * 0: CMFA interrupt requests (CMIA) are disabled 1: CMFA interrupt requests (CMIA) are enabled Timer Overflow Interrupt Enable* 3 5 OVIE 0 R/W Selects whether OVF interrupt requests (OVI) are enabled or disabled when the OVF flag in TCSR is set to 1. 0: OVF interrupt requests (OVI) are disabled 1: OVF interrupt requests (OVI) are enabled 4 3 CCLR1 CCLR0 0 0 R/W R/W Counter Clear 1 and 0* 1 These bits select the method by which TCNT is cleared. 00: Clearing is disabled 01: Cleared by compare match A 10: Cleared by compare match B 11: Cleared at rising edge (TMRIS in TCCR is cleared to 0) of the external reset input or when the external 3 reset input is high (TMRIS in TCCR is set to 1) * 2 1 0 CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W Clock Select 2 to 0* 1 These bits select the clock input to TCNT and count condition. See table 12.2. Notes: 1. To use an external reset or external clock, the DDR and ICR bits in the corresponding pin should be set to 0 and 1, respectively. For details, see section 9, I/O Ports. 2. In unit 2 and unit 3, one interrupt signal is used for CMIEB or CMIEA. For details, see section 12.7, Interrupt Sources. 3. Available only in unit 0 and unit 1 Rev.1.00 Jun. 07, 2006 Page 615 of 1102 REJ09B0294-0100 Section 12 8-Bit Timers (TMR) 12.3.5 Timer Counter Control Register (TCCR) TCCR selects the TCNT internal clock source and controls external reset input. Bit Bit Name Initial Value R/W 7 0 R 6 0 R 5 0 R 4 0 R 3 TMRIS 0 R/W 2 0 R 1 ICKS1 0 R/W 0 ICKS0 0 R/W Bit 7 to 4 3 Bit Name TMRIS Initial Value All 0 0 R/W R R/W Description Reserved These bits are always read as 0. It should not be set to 0. Timer Reset Input Select* Selects an external reset input when the CCLR1 and CCLR0 bits in TCR are B'11. 0: Cleared at rising edge of the external reset 1: Cleared when the external reset is high 2 1 0 Note: * ICKS1 ICKS0 0 0 0 R R/W R/W Reserved This bit is always read as 0. It should not be set to 0. Internal Clock Select 1 and 0 These bits in combination with bits CKS2 to CKS0 in TCR select the internal clock. See table 12.2. Available only in unit 0 and unit 1. The write value should always be 0 in unit 2 and unit 3. Rev.1.00 Jun. 07, 2006 Page 616 of 1102 REJ09B0294-0100 Section 12 8-Bit Timers (TMR) Table 12.2 Clock Input to TCNT and Count Condition (Units 0 and 1) TCR Channel TMR_0 Bit 2 CKS2 0 0 TCCR Bit 1 Bit 0 Bit 1 Bit 0 CKS1 CKS0 ICKS1 ICKS0 Description 0 0 0 1 0 0 1 1 0 1 0 0 0 1 1 0 1 1 0 0 1 1 1 TMR_1 0 0 0 0 0 0 0 1 0 0 1 1 0 1 0 0 0 1 1 0 1 1 0 0 1 1 1 All 1 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Clock input prohibited Uses internal clock. Counts at rising edge of P/8. Uses internal clock. Counts at rising edge of P/2. Uses internal clock. Counts at falling edge of P/8. Uses internal clock. Counts at falling edge of P/2. Uses internal clock. Counts at rising edge of P/64. Uses internal clock. Counts at rising edge of P/32. Uses internal clock. Counts at falling edge of P/64. Uses internal clock. Counts at falling edge of P/32. Uses internal clock. Counts at rising edge of P/8192. Uses internal clock. Counts at rising edge of P/1024. Uses internal clock. Counts at falling edge of P/8192. Uses internal clock. Counts at falling edge of P/1024. Counts at TCNT_1 overflow signal*1. Clock input prohibited Uses internal clock. Counts at rising edge of P/8. Uses internal clock. Counts at rising edge of P/2. Uses internal clock. Counts at falling edge of P/8. Uses internal clock. Counts at falling edge of P/2. Uses internal clock. Counts at rising edge of P/64. Uses internal clock. Counts at rising edge of P/32. Uses internal clock. Counts at falling edge of P/64. Uses internal clock. Counts at falling edge of P/32. Uses internal clock. Counts at rising edge of P/8192. Uses internal clock. Counts at rising edge of P/1024. Uses internal clock. Counts at falling edge of P/8192. Uses internal clock. Counts at falling edge of P/1024. Counts at TCNT_0 compare match A*1. Uses external clock. Counts at rising edge*2. Uses external clock. Counts at falling edge*2. Uses external clock. Counts at both rising and falling edges*2. Notes: 1. If the clock input of channel 0 is the TCNT_1 overflow signal and that of channel 1 is the TCNT_0 compare match signal, no incrementing clock is generated. Do not use this setting. 2. To use the external clock, the DDR and ICR bits in the corresponding pin should be set to 0 and 1, respectively. For details, see section 9, I/O Ports. Rev.1.00 Jun. 07, 2006 Page 617 of 1102 REJ09B0294-0100 Section 12 8-Bit Timers (TMR) Table 12.3 Clock Input to TCNT and Count Condition (Units 2 and 3) TCR Channel TMR_4 Bit 2 CKS2 0 0 TCCR Bit 1 Bit 0 Bit 1 Bit 0 CKS1 CKS0 ICKS1 ICKS0 Description 0 0 0 1 0 0 1 1 0 1 0 0 0 1 1 0 1 1 0 0 1 1 1 TMR_5 0 0 0 0 0 0 0 1 0 0 1 1 0 1 0 0 0 1 1 0 1 1 0 0 1 1 1 All 1 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Clock input prohibited Uses internal clock. Counts at rising edge of P/8. Uses internal clock. Counts at rising edge of P/2. Uses internal clock. Counts at falling edge of P/8. Uses internal clock. Counts at falling edge of P/2. Uses internal clock. Counts at rising edge of P/64. Uses internal clock. Counts at rising edge of P/32. Uses internal clock. Counts at falling edge of P/64. Uses internal clock. Counts at falling edge of P/32. Uses internal clock. Counts at rising edge of P/8192. Uses internal clock. Counts at rising edge of P/1024. Uses internal clock. Counts at rising edge of P. Uses internal clock. Counts at falling edge of P/1024. Counts at TCNT_1 overflow signal*. Clock input prohibited Uses internal clock. Counts at rising edge of P/8. Uses internal clock. Counts at rising edge of P/2. Uses internal clock. Counts at falling edge of P/8. Uses internal clock. Counts at falling edge of P/2. Uses internal clock. Counts at rising edge of P/64. Uses internal clock. Counts at rising edge of P/32. Uses internal clock. Counts at falling edge of P/64. Uses internal clock. Counts at falling edge of P/32. Uses internal clock. Counts at rising edge of P/8192. Uses internal clock. Counts at rising edge of P/1024. Uses internal clock. Counts at rising edge of P. Uses internal clock. Counts at falling edge of P/1024. Counts at TCNT_0 compare match A*. Setting prohibited Setting prohibited Setting prohibited Note: * If the clock input of channel 4 is the TCNT_1 overflow signal and that of channel 5 is the TCNT_0 compare match signal, no incrementing clock is generated. Do not use this setting. Rev.1.00 Jun. 07, 2006 Page 618 of 1102 REJ09B0294-0100 Section 12 8-Bit Timers (TMR) 12.3.6 Timer Control/Status Register (TCSR) TCSR displays status flags, and controls compare match output. * TCSR_0 Bit Bit Name Initial Value R/W * TCSR_1 Bit Bit Name Initial Value R/W 7 CMFB 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 1 R 3 OS3 0 R/W 2 OS2 0 R/W 1 OS1 0 R/W 0 OS0 0 R/W 7 CMFB 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 ADTE 0 R/W 3 OS3 0 R/W 2 OS2 0 R/W 1 OS1 0 R/W 0 OS0 0 R/W Note: * Only 0 can be written to this bit, to clear the flag. * TCSR_0 Bit 7 Bit Name CMFB Initial Value 0 R/W 1 Description R/(W)* Compare Match Flag B [Setting condition] * * When TCNT matches TCORB When writing 0 after reading CMFB = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) * When the DTC is activated by a CMIB interrupt while 3 the DISEL bit in MRB of the DTC is 0* [Clearing conditions] Rev.1.00 Jun. 07, 2006 Page 619 of 1102 REJ09B0294-0100 Section 12 8-Bit Timers (TMR) Bit 6 Bit Name CMFA Initial Value 0 R/W 1 Description R/(W)* Compare Match Flag A [Setting condition] * * When TCNT matches TCORA When writing 0 after reading CMFA = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) * When the DTC is activated by a CMIA interrupt while 3 the DISEL bit in MRB in the DTC is 0* [Clearing conditions] 5 OVF 0 R/(W)* Timer Overflow Flag [Setting condition] When TCNT overflows from H'FF to H'00 [Clearing condition] When writing 0 after reading OVF = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) 1 4 ADTE 0 R/W A/D Trigger Enable* 3 Selects enabling or disabling of A/D converter start requests by compare match A. 0: A/D converter start requests by compare match A are disabled 1: A/D converter start requests by compare match A are enabled 3 2 OS3 OS2 0 0 R/W R/W Output Select 3 and 2* 2 These bits select a method of TMO pin output when compare match B of TCORB and TCNT occurs. 00: No change when compare match B occurs 01: 0 is output when compare match B occurs 10: 1 is output when compare match B occurs 11: Output is inverted when compare match B occurs (toggle output) Rev.1.00 Jun. 07, 2006 Page 620 of 1102 REJ09B0294-0100 Section 12 8-Bit Timers (TMR) Bit 1 0 Bit Name OS1 OS0 Initial Value 0 0 R/W R/W R/W Description Output Select 1 and 0* 2 These bits select a method of TMO pin output when compare match A of TCORA and TCNT occurs. 00: No change when compare match A occurs 01: 0 is output when compare match A occurs 10: 1 is output when compare match A occurs 11: Output is inverted when compare match A occurs (toggle output) Notes: 1. Only 0 can be written to bits 7 to 5, to clear these flags. 2. Timer output is disabled when bits OS3 to OS0 are all 0. Timer output is 0 until the first compare match occurs after a reset. 3. Available in unit 0 and unit 1 only. * TCSR_1 Bit 7 Bit Name CMFB Initial Value 0 R/W 1 Description R/(W)* Compare Match Flag B [Setting condition] * * When TCNT matches TCORB When writing 0 after reading CMFB = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) * When the DTC is activated by a CMIB interrupt while 3 the DISEL bit in MRB of the DTC is 0* [Clearing conditions] Rev.1.00 Jun. 07, 2006 Page 621 of 1102 REJ09B0294-0100 Section 12 8-Bit Timers (TMR) Bit 6 Bit Name CMFA Initial Value 0 R/W 1 Description R/(W)* Compare Match Flag A [Setting condition] * * When TCNT matches TCORA When writing 0 after reading CMFA = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) * When the DTC is activated by a CMIA interrupt while 3 the DISEL bit in MRB of the DTC is 0* [Clearing conditions] 5 OVF 0 R/(W)* Timer Overflow Flag [Setting condition] When TCNT overflows from H'FF to H'00 [Clearing condition] Cleared by reading OVF when OVF = 1, then writing 0 to OVF (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) 1 4 3 2 OS3 OS2 1 0 0 R R/W R/W Reserved This bit is always read as 1 and cannot be modified. Output Select 3 and 2* 2 These bits select a method of TMO pin output when compare match B of TCORB and TCNT occurs. 00: No change when compare match B occurs 01: 0 is output when compare match B occurs 10: 1 is output when compare match B occurs 11: Output is inverted when compare match B occurs (toggle output) Rev.1.00 Jun. 07, 2006 Page 622 of 1102 REJ09B0294-0100 Section 12 8-Bit Timers (TMR) Bit 1 0 Bit Name OS1 OS0 Initial Value 0 0 R/W R/W R/W Description Output Select 1 and 0* 2 These bits select a method of TMO pin output when compare match A of TCORA and TCNT occurs. 00: No change when compare match A occurs 01: 0 is output when compare match A occurs 10: 1 is output when compare match A occurs 11: Output is inverted when compare match A occurs (toggle output) Notes: 1. Only 0 can be written to bits 7 to 5, to clear these flags. 2. Timer output is disabled when bits OS3 to OS0 are all 0. Timer output is 0 until the first compare match occurs after a reset. 3. Available only in unit 0 and unit 1. 12.4 12.4.1 Operation Pulse Output Figure 12.5 shows an example of the 8-bit timer being used to generate a pulse output with a desired duty cycle. The control bits are set as follows: 1. Clear the bit CCLR1 in TCR to 0 and set the bit CCLR0 in TCR to 1 so that TCNT is cleared at a TCORA compare match. 2. Set the bits OS3 to OS0 in TCSR to B'0110, causing the output to change to 1 at a TCORA compare match and to 0 at a TCORB compare match. With these settings, the 8-bit timer provides pulses output at a cycle determined by TCORA with a pulse width determined by TCORB. No software intervention is required. The timer output is 0 until the first compare match occurs after a reset. Rev.1.00 Jun. 07, 2006 Page 623 of 1102 REJ09B0294-0100 Section 12 8-Bit Timers (TMR) TCNT H'FF TCORA TCORB H'00 Counter clear TMO Figure 12.5 Example of Pulse Output 12.4.2 Reset Input Figure 12.6 shows an example of the 8-bit timer being used to generate a pulse which is output after a desired delay time from a TMRI input. The control bits are set as follows: 1. Set both bits CCLR1 and CCLR0 in TCR to 1 and set the TMRIS bit in TCCR to 1 so that TCNT is cleared at the high level input of the TMRI signal. 2. In TCSR, set bits OS3 to OS0 to B'0110, causing the output to change to 1 at a TCORA compare match and to 0 at a TCORB compare match. With these settings, the 8-bit timer provides pulses output at a desired delay time from a TMRI input determined by TCORA and with a pulse width determined by TCORB and TCORA. TCORB TCORA TCNT H'00 TMRI TMO Figure 12.6 Example of Reset Input Rev.1.00 Jun. 07, 2006 Page 624 of 1102 REJ09B0294-0100 Section 12 8-Bit Timers (TMR) 12.5 12.5.1 Operation Timing TCNT Count Timing Figure 12.7 shows the TCNT count timing for internal clock input. Figure 12.8 shows the TCNT count timing for external clock input. Note that the external clock pulse width must be at least 1.5 states for increment at a single edge, and at least 2.5 states for increment at both edges. The counter will not increment correctly if the pulse width is less than these values. P Internal clock TCNT input clock TCNT N-1 N N+1 Figure 12.7 Count Timing for Internal Clock Input P External clock input pin TCNT input clock TCNT N-1 N N+1 Figure 12.8 Count Timing for External Clock Input Rev.1.00 Jun. 07, 2006 Page 625 of 1102 REJ09B0294-0100 Section 12 8-Bit Timers (TMR) 12.5.2 Timing of CMFA and CMFB Setting at Compare Match The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the TCOR and TCNT values match. The compare match signal is generated at the last state in which the match is true, just before the timer counter is updated. Therefore, when the TCOR and TCNT values match, the compare match signal is not generated until the next TCNT clock input. Figure 12.9 shows this timing. P TCNT TCOR Compare match signal CMF N N N+1 Figure 12.9 Timing of CMF Setting at Compare Match 12.5.3 Timing of Timer Output at Compare Match When a compare match signal is generated, the timer output changes as specified by the bits OS3 to OS0 in TCSR. Figure 12.10 shows the timing when the timer output is toggled by the compare match A signal. P Compare match A signal Timer output pin Figure 12.10 Timing of Toggled Timer Output at Compare Match A Rev.1.00 Jun. 07, 2006 Page 626 of 1102 REJ09B0294-0100 Section 12 8-Bit Timers (TMR) 12.5.4 Timing of Counter Clear by Compare Match TCNT is cleared when compare match A or B occurs, depending on the settings of the bits CCLR1 and CCLR0 in TCR. Figure 12.11 shows the timing of this operation. P Compare match signal TCNT N H'00 Figure 12.11 Timing of Counter Clear by Compare Match 12.5.5 Timing of TCNT External Reset* TCNT is cleared at the rising edge or high level of an external reset input, depending on the settings of bits CCLR1 and CCLR0 in TCR. The clear pulse width must be at least 2 states. Figure 12.12 and Figure 12.13 shows the timing of this operation. Note: * Clearing by an external reset is available only in units 0 and 1. P External reset input pin Clear signal TCNT N-1 N H'00 Figure 12.12 Timing of Clearance by External Reset (Rising Edge) P External reset input pin Clear signal TCNT N-1 N H'00 Figure 12.13 Timing of Clearance by External Reset (High Level) Rev.1.00 Jun. 07, 2006 Page 627 of 1102 REJ09B0294-0100 Section 12 8-Bit Timers (TMR) 12.5.6 Timing of Overflow Flag (OVF) Setting The OVF bit in TCSR is set to 1 when TCNT overflows (changes from H'FF to H'00). Figure 12.14 shows the timing of this operation. P TCNT Overflow signal H'FF H'00 OVF Figure 12.14 Timing of OVF Setting 12.6 Operation with Cascaded Connection If the bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit counter mode) or compare matches of the 8-bit channel 0 could be counted by the timer of channel 1 (compare match count mode). 12.6.1 16-Bit Counter Mode When the bits CKS2 to CKS0 in TCR_0 are set to B'100, the timer functions as a single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits. (1) Setting of Compare Match Flags * The CMF flag in TCSR_0 is set to 1 when a 16-bit compare match event occurs. * The CMF flag in TCSR_1 is set to 1 when a lower 8-bit compare match event occurs. (2) Counter Clear Specification * If the CCLR1 and CCLR0 bits in TCR_0 have been set for counter clear at compare match, the 16-bit counter (TCNT_0 and TCNT_1 together) is cleared when a 16-bit compare match event occurs. The 16-bit counter (TCNT0 and TCNT1 together) is cleared even if counter clear by the TMRI0 pin has been set. * The settings of the CCLR1 and CCLR0 bits in TCR_1 are ignored. The lower 8 bits cannot be cleared independently. Rev.1.00 Jun. 07, 2006 Page 628 of 1102 REJ09B0294-0100 Section 12 8-Bit Timers (TMR) (3) Pin Output * Control of output from the TMO0 pin by the bits OS3 to OS0 in TCSR_0 is in accordance with the 16-bit compare match conditions. * Control of output from the TMO1 pin by the bits OS3 to OS0 in TCSR_1 is in accordance with the lower 8-bit compare match conditions. 12.6.2 Compare Match Count Mode When the bits CKS2 to CKS0 in TCR_1 are set to B'100, TCNT_1 counts compare match A for channel 0. Channels 0 and 1 are controlled independently. Conditions such as setting of the CMF flag, generation of interrupts, output from the TMO pin, and counter clear are in accordance with the settings for each channel. 12.7 12.7.1 Interrupt Sources Interrupt Sources and DTC Activation * Interrupt in unit 0 and unit 1 There are three interrupt sources for the 8-bit timer (TMR_0 or TMR_1): CMIA, CMIB, and OVI. Their interrupt sources and priorities are shown in table 12.4. Each interrupt source is enabled or disabled by the corresponding interrupt enable bit in TCR or TCSR, and independent interrupt requests are sent for each to the interrupt controller. It is also possible to activate the DTC by means of CMIA and CMIB interrupts (This is available in unit 0 and unit 1 only). Table 12.4 8-Bit Timer (TMR_0 or TMR_1) Interrupt Sources (in Unit 0 and Unit 1) Signal Name CMIA0 CMIB0 OVI0 CMIA1 CMIB1 OVI1 Name CMIA0 CMIB0 OVI0 CMIA1 CMIB1 OVI1 Interrupt Source Interrupt Flag DTC Activation Possible Possible Not possible Low Possible Possible Not possible Low High Priority High TCORA_0 compare match CMFA TCORB_0 compare match CMFB TCNT_0 overflow OVF TCORA_1 compare match CMFA TCORB_1 compare match CMFB TCNT_1 overflow OVF Rev.1.00 Jun. 07, 2006 Page 629 of 1102 REJ09B0294-0100 Section 12 8-Bit Timers (TMR) * Interrupt in unit 2 and unit 3 There are two interrupt sources for the 8-bit timer (TMR_4 or TMR_5): CMIA, CMIB. The interrupt signal is CMI only. The interrupt sources are shown in table 12.5. When enabling or disabling is set by the interrupt enable bit in TCR or TCSR, and when either CMIA or CMIB interrupt source is generated, CMI is sent to the interrupt controller. To verify which interrupt source is generated, confirm by checking each flag in TCSR. No overflow-related interrupt signal exists. DTC cannot be activated by this interrupt. Table 12.5 8-Bit Timer (TMR_4 or TMR_5) Interrupt Sources (in Unit 2 and Unit 3) Signal Name CMI4 Name CMIA4 CMIB4 CMI5 CMIA5 CMIB5 Interrupt Source TCORA_4 compare match TCORB_4 compare match TCORA_5 compare match TCORB_5 compare match Interrupt Flag CMFA CMFB CMFA CMFB Not possible DTC Activation Not possible Priority 12.7.2 A/D Converter Activation The A/D converter can be activated only by TMR_0 compare match A.* If the ADTE bit in TCSR_0 is set to 1 when the CMFA flag in TCSR_0 is set to 1 by the occurrence of TMR_0 compare match A, a request to start A/D conversion is sent to the A/D converter. If the 8-bit timer conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is started. Note: * Available only in unit 0 and unit 1. Rev.1.00 Jun. 07, 2006 Page 630 of 1102 REJ09B0294-0100 Section 12 8-Bit Timers (TMR) 12.8 12.8.1 Usage Notes Notes on Setting Cycle If the compare match is selected for counter clear, TCNT is cleared at the last state in the cycle in which the values of TCNT and TCOR match. TCNT updates the counter value at this last state. Therefore, the counter frequency is obtained by the following formula. f = / (N + 1 ) f: Counter frequency : Operating frequency N: TCOR value 12.8.2 Conflict between TCNT Write and Counter Clear If a counter clear signal is generated during the T2 state of a TCNT write cycle, the clear takes priority and the write is not performed as shown in figure 12.15. TCNT write cycle by CPU T1 T2 P Address Internal write signal Counter clear signal TCNT N H'00 TCNT address Figure 12.15 Conflict between TCNT Write and Clear Rev.1.00 Jun. 07, 2006 Page 631 of 1102 REJ09B0294-0100 Section 12 8-Bit Timers (TMR) 12.8.3 Conflict between TCNT Write and Increment If a TCNT input clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the counter is not incremented as shown in figure 12.16. TCNT write cycle by CPU T1 T2 P Address Internal write signal TCNT input clock TCNT N Counter write data M TCNT address Figure 12.16 Conflict between TCNT Write and Increment 12.8.4 Conflict between TCOR Write and Compare Match If a compare match event occurs during the T2 state of a TCOR write cycle, the TCOR write takes priority and the compare match signal is inhibited as shown in figure 12.17. TCOR write cycle by CPU T1 T2 P Address Internal write signal TCNT TCOR N N TCOR write data Compare match signal Inhibited N+1 M TCOR address Figure 12.17 Conflict between TCOR Write and Compare Match Rev.1.00 Jun. 07, 2006 Page 632 of 1102 REJ09B0294-0100 Section 12 8-Bit Timers (TMR) 12.8.5 Conflict between Compare Matches A and B If compare match events A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output statuses set for compare match A and compare match B, as shown in table 12.6. Table 12.6 Timer Output Priorities Output Setting Toggle output 1-output 0-output No change Low Priority High 12.8.6 Switching of Internal Clocks and TCNT Operation TCNT may be incremented erroneously depending on when the internal clock is switched. Table 12.7 shows the relationship between the timing at which the internal clock is switched (by writing to the bits CKS1 and CKS0) and the TCNT operation. When the TCNT clock is generated from an internal clock, the rising or falling edge of the internal clock pulse are always monitored. Table 12.7 assumes that the falling edge is selected. If the signal levels of the clocks before and after switching change from high to low as shown in item 3, the change is considered as the falling edge. Therefore, a TCNT clock pulse is generated and TCNT is incremented. This is similar to when the rising edge is selected. The erroneous increment of TCNT can also happen when switching between rising and falling edges of the internal clock, and when switching between internal and external clocks. Rev.1.00 Jun. 07, 2006 Page 633 of 1102 REJ09B0294-0100 Section 12 8-Bit Timers (TMR) Table 12.7 Switching of Internal Clock and TCNT Operation No. 1 Timing to Change CKS1 and CKS0 Bits Switching from low to low* 1 TCNT Clock Operation Clock before switchover Clock after switchover TCNT input clock TCNT N CKS bits changed N+1 2 Switching from low to high* 2 Clock before switchover Clock after switchover TCNT input clock TCNT N N+1 N+2 CKS bits changed 3 Switching from high to low* 3 Clock before switchover Clock after switchover TCNT input clock TCNT N N+1 CKS bits changed *4 N+2 4 Switching from high to high Clock before switchover Clock after switchover TCNT input clock TCNT N N+1 N+2 CKS bits changed Notes: 1. 2. 3. 4. Includes switching from low to stop, and from stop to low. Includes switching from stop to high. Includes switching from high to stop. Generated because the change of the signal levels is considered as a falling edge; TCNT is incremented. Rev.1.00 Jun. 07, 2006 Page 634 of 1102 REJ09B0294-0100 Section 12 8-Bit Timers (TMR) 12.8.7 Mode Setting with Cascaded Connection If 16-bit counter mode and compare match count mode are specified at the same time, input clocks for TCNT_0 and TCNT_1 are not generated, and the counter stops. Do not specify 16-bit counter mode and compare match count mode simultaneously. 12.8.8 Module Stop State Setting Operation of the TMR can be disabled or enabled using the module stop control register. The initial setting is for operation of the TMR to be halted. Register access is enabled by clearing the module stop state. For details, see section 23, Power-Down Modes. 12.8.9 Interrupts in Module Stop State If the module stop state is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DTC activation source. Interrupts should therefore be disabled before entering the module stop state. Rev.1.00 Jun. 07, 2006 Page 635 of 1102 REJ09B0294-0100 Section 12 8-Bit Timers (TMR) Rev.1.00 Jun. 07, 2006 Page 636 of 1102 REJ09B0294-0100 Section 13 32K Timer (TM32K) Section 13 32K Timer (TM32K) The 32K timer (TM32K) is an 8-bit timer that generates a 32K timer interrupt each time the counter overflows. Figure 13.1 shows a block diagram of the TM32K. 13.1 Features * Selectable from four counter input clocks produced by frequency division of the 32.768 kHz clock * A 32K timer interrupt (32KOVI) generated by a counter overflow * Four overflow cycles of 250 ms, 500 ms, 1 s, and 2 s settable * Counter operational except in hardware standby mode or the reset state 32KOVI (IRQ15) (Interrupt request signal) Clock Counter Clock select SUBCK/32 SUBCK/64 SUBCK/128 SUBCK/256 Internal clock TCNT32K TCR32K Bus interface Module bus TK32K [Legend] TCR32K: Timer control register TCNT32K: Timer counter Figure 13.1 Block Diagram of TM32K Rev.1.00 Jun. 07, 2006 Page 637 of 1102 REJ09B0294-0100 Internal bus Section 13 32K Timer (TM32K) 13.2 Register Descriptions The TM32K has the following registers. * Timer counter (TCNT32K) * Timer control register (TCR32K) 13.2.1 Timer Counter (TCNT32K) TCNT32K is an 8-bit readable up-counter. When the TME bit in the timer control register (TCR32K) is 0, TCNT32K is initialized to H'00. Bit: Bit Name: Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 7 6 5 4 3 2 1 0 Note: A correct value cannot be read if the counter is read while the 32-kHz oscillator is not in operation (OSC32STP = 1). 13.2.2 Time Control Register (TCR32K) TCR32K enables the timer, stops the 32K oscillator, and selects the clock source to be input to TCNT32K. Bit: BIt Name: Initial Value: R/W: 7 1 R 6 1 R 5 TME 0 R/W 4 1 R 3 1 R 2 OSC32STP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Bit 7 6 5 Bit Name TME Initial Value 1 1 0 R/W R R R/W Description Reserved These bits are always read as 1 and cannot be modified. Timer Enable When this bit is set to 1, TCNT32K starts counting. When this bit is cleared, TCNT32K stops counting and is initialized to H'00. Rev.1.00 Jun. 07, 2006 Page 638 of 1102 REJ09B0294-0100 Section 13 32K Timer (TM32K) Bit 4 3 2 Bit Name Initial Value 1 1 R/W R R R/W Description Reserved These bits are always read as 1 and cannot be modified. 32-kHz Oscillator Stop 0: Starts the 32-kHz oscillator 1: Stops the 32-kHz oscillator OSC32STP* 0 1 0 CKS1 CKS0 0 0 R/W R/W Clock Select 1, 0 Select the clock source to be input to TCNT32K. The overflow cycle for SUBCK = 32.768 kHz is indicated in parentheses. 00: Clock SUBCK/32 (cycle: 250 ms) 01: Clock SUBCK/64 (cycle: 500 ms) 10: Clock SUBCK/128 (cycle: 1 s) 11: Clock SUBCK/512 (cycle: 2 s) Note: * When the CK32K bit in SUBCKCR is 1, 1 cannot be written to this bit. 13.3 Operation Setting 1 to the TME bit in TCR32K starts the count-up operation. A 32K timer interrupt (32KOVI) is generated each time TCNT32K overflows. Therefore, an interrupt can be generated at intervals with a cycle determined by the clock select bits 0 and 1. TCNT32K value H'FF Overflow Overflow Overflow Overflow H'00 TME = 1 32KOVI 32KOVI 32KOVI 32KOVI Time 32KOVI 32KOVI: 32K timer interrupt 3 clocks of 32K Figure 13.2 32K Timer Operation Rev.1.00 Jun. 07, 2006 Page 639 of 1102 REJ09B0294-0100 Section 13 32K Timer (TM32K) 13.4 Interrupt Source Overflows of the 32K timer generate a 32K timer interrupt (32KOVI) that lasts for three clocks of 32 kHz. Since 32KOVI is internally connected to IRQ15, the IRQ15F bit is set to 1 when an interrupt is generated. For the IRQ15 setting, select an interrupt request generated at the falling edge with ISCR. Table 13.1 TM32K Interrupt Source Name 32KOVI Interrupt Source TCNT32K overflow Interrupt Flag IRQ15F DTC Activation Impossible 13.5 13.5.1 Usage Notes Changing Values of Bits CKS1 and CKS0 If bits CKS1 and CKS0 in TCR32K are written to while the TM32K is operating, errors could occur in the incrementation. The TM32K must be stopped (the TME bit is set to 0) before the values of bits CKS1 and CKS0 are changed. 13.5.2 Usage Notes on 32K Timer * The 32K timer does not operate when the OSC32STP bit is set to 1. Always set the OSC32STP bit to 0 when starting the 32K timer. * When the OSC32STP bit has been changed from 1 to 0, allow enough time to ensure settling of the oscillation by the 32-kHz oscillator. 13.5.3 Note on Reading Timer Counter A counter read value is undefined during one clock of 32 kHz immediately after returning from software standby. Wait one clock of 32 kHz when reading the timer counter. 13.5.4 Note on Register Initialization TCR32K and TCNT32K of the 32K timer are initialized in hardware standby mode or in the pin reset state. These registers are not initialized by a reset caused by a watchdog timer overflow. Rev.1.00 Jun. 07, 2006 Page 640 of 1102 REJ09B0294-0100 Section 14 Watchdog Timer (WDT) Section 14 Watchdog Timer (WDT) The watchdog timer (WDT) is an 8-bit timer that outputs an overflow signal (WDTOVF) if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. At the same time, the WDT can also generate an internal reset signal. When this watchdog function is not needed, the WDT can be used as an interval timer. In interval timer operation, an interval timer interrupt is generated each time the counter overflows. Figure 14.1 shows a block diagram of the WDT. 14.1 Features * Selectable from eight counter input clocks * Switchable between watchdog timer mode and interval timer mode In watchdog timer mode If the counter overflows, the WDT outputs WDTOVF. It is possible to select whether or not the entire LSI is reset at the same time. In interval timer mode If the counter overflows, the WDT generates an interval timer interrupt (WOVI). Rev.1.00 Jun. 07, 2006 Page 641 of 1102 REJ09B0294-0100 Section 14 Watchdog Timer (WDT) Overflow WOVI (interrupt request signal) WDTOVF Internal reset signal* Interrupt control Clock Clock select Reset control P/2 P/64 P/128 P/512 P/2048 P/8192 P/32768 P/131072 Internal clocks RSTCSR TCNT TCSR Bus interface Module bus WDT [Legend] Timer control/status register TCSR: Timer counter TCNT: RSTCSR: Reset control/status register Note: * An internal reset signal can be generated by the RSTCSR setting. Figure 14.1 Block Diagram of WDT 14.2 Input/Output Pin Table 14.1 shows the WDT pin configuration. Table 14.1 Pin Configuration Name Watchdog timer overflow Symbol WDTOVF I/O Output Function Outputs a counter overflow signal in watchdog timer mode Rev.1.00 Jun. 07, 2006 Page 642 of 1102 REJ09B0294-0100 Internal bus Section 14 Watchdog Timer (WDT) 14.3 Register Descriptions The WDT has the following three registers. To prevent accidental overwriting, TCSR, TCNT, and RSTCSR have to be written to in a method different from normal registers. For details, see section 14.6.1, Notes on Register Access. * Timer counter (TCNT) * Timer control/status register (TCSR) * Reset control/status register (RSTCSR) 14.3.1 Timer Counter (TCNT) TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 when the TME bit in TCSR is cleared to 0. Bit Bit Name Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 6 5 4 3 2 1 0 14.3.2 Timer Control/Status Register (TCSR) TCSR selects the clock source to be input to TCNT, and the timer mode. Bit Bit Name Initial Value R/W Note: 7 OVF 0 R/(W)* 6 WT/IT 0 R/W 5 TME 0 R/W 4 1 R 3 1 R 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W * Only 0 can be written to this bit, to clear the flag. Rev.1.00 Jun. 07, 2006 Page 643 of 1102 REJ09B0294-0100 Section 14 Watchdog Timer (WDT) Bit 7 Bit Name OVF Initial Value 0 R/W Description 6 WT/IT 0 5 TME 0 4, 3 2 1 0 CKS2 CKS1 CKS0 All 1 0 0 0 R/(W)* Overflow Flag Indicates that TCNT has overflowed in interval timer mode. Only 0 can be written to this bit, to clear the flag. [Setting condition] When TCNT overflows in interval timer mode (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset. [Clearing condition] Cleared by reading TCSR when OVF = 1, then writing 0 to OVF (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) R/W Timer Mode Select Selects whether the WDT is used as a watchdog timer or interval timer. 0: Interval timer mode When TCNT overflows, an interval timer interrupt (WOVI) is requested. 1: Watchdog timer mode When TCNT overflows, the WDTOVF signal is output. R/W Timer Enable When this bit is set to 1, TCNT starts counting. When this bit is cleared, TCNT stops counting and is initialized to H'00. R Reserved These are read-only bits and cannot be modified. R/W R/W R/W Clock Select 2 to 0 Select the clock source to be input to TCNT. The overflow cycle for P = 20 MHz is indicated in parentheses. 000: Clock P/2 (cycle: 25.6 s) 001: Clock P/64 (cycle: 819.2 s) 010: Clock P/128 (cycle: 1.6 ms) 011: Clock P/512 (cycle: 6.6 ms) 100: Clock P/2048 (cycle: 26.2 ms) 101: Clock P/8192 (cycle: 104.9 ms) 110: Clock P/32768 (cycle: 419.4 ms) 111: Clock P/131072 (cycle: 1.68 s) Note: * Only 0 can be written to this bit, to clear the flag. Rev.1.00 Jun. 07, 2006 Page 644 of 1102 REJ09B0294-0100 Section 14 Watchdog Timer (WDT) 14.3.3 Reset Control/Status Register (RSTCSR) RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the WDT internal reset signal caused by WDT overflows. Bit Bit Name Initial Value R/W 7 WOVF 0 R/(W)* 6 RSTE 0 R/W 5 0 R/W 4 1 R 3 1 R 2 1 R 1 1 R 0 1 R Note: * Only 0 can be written to this bit, to clear the flag. Bit 7 Bit Name WOVF Initial Value 0 R/W Description R/(W)* Watchdog Timer Overflow Flag This bit is set when TCNT overflows in watchdog timer mode. This bit cannot be set in interval timer mode, and only 0 can be written. [Setting condition] When TCNT overflows (changed from H'FF to H'00) in watchdog timer mode [Clearing condition] Reading RSTCSR when WOVF = 1, and then writing 0 to WOVF (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) 6 RSTE 0 R/W Reset Enable Specifies whether or not this LSI is internally reset if TCNT overflows during watchdog timer operation. 0: LSI is not reset even if TCNT overflows (Though this LSI is not reset, TCNT and TCSR in WDT are reset) 1: LSI is reset if TCNT overflows Rev.1.00 Jun. 07, 2006 Page 645 of 1102 REJ09B0294-0100 Section 14 Watchdog Timer (WDT) Bit 5 Bit Name Initial Value 0 R/W R/W Description Reserved Although this bit is readable/writable, reading from or writing to this bit does not affect operation. 4 to 0 Note: * All 1 R Reserved These are read-only bits and cannot be modified. Only 0 can be written to this bit, to clear the flag. 14.4 14.4.1 Operation Watchdog Timer Mode To use the WDT in watchdog timer mode, set both the WT/IT and TME bits in TCSR to 1. During watchdog timer operation, if TCNT overflows without being rewritten because of a system crash or other error, the WDTOVF signal is output. This ensures that TCNT does not overflow while the system is operating normally. Software must prevent TCNT overflows by rewriting the TCNT value (normally H'00 is written) before overflow occurs. This WDTOVF signal can be used to reset the LSI internally in watchdog timer mode. If TCNT overflows when the RSTE bit in RSTCSR is set to 1, a signal that resets this LSI internally is generated at the same time as the WDTOVF signal. If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a WDT overflow, the RES pin reset has priority and the WOVF bit in RSTCSR is cleared to 0. The WDTOVF signal is output for 133 cycles of P when RSTE = 1 in RSTCSR, and for 130 cycles of P when RSTE = 0 in RSTCSR. The internal reset signal is output for 519 cycles of P. When RSTE = 1, an internal reset signal is generated. Since the system clock control register (SCKCR) is initialized, the multiplication ratio of P becomes the initial value. When RSTE = 0, an internal reset signal is not generated. Neither SCKCR nor the multiplication ratio of P is changed. When TCNT overflows in watchdog timer mode, the WOVF bit in RSTCSR is set to 1. If TCNT overflows when the RSTE bit in RSTCSR is set to 1, an internal reset signal is generated for the entire LSI. Rev.1.00 Jun. 07, 2006 Page 646 of 1102 REJ09B0294-0100 Section 14 Watchdog Timer (WDT) TCNT value Overflow H'FF H'00 WT/IT = 1 TME = 1 H'00 written to TCNT WOVF = 1 WDTOVF and internal reset are generated WT/IT = 1 H'00 written TME = 1 to TCNT Time WDTOVF signal 133 states*2 Internal reset signal*1 519 states Notes: 1. If TCNT overflows when the RSTE bit is set to 1, an internal reset signal is generated. 2. 130 states when the RSTE bit is cleared to 0. Figure 14.2 Operation in Watchdog Timer Mode Rev.1.00 Jun. 07, 2006 Page 647 of 1102 REJ09B0294-0100 Section 14 Watchdog Timer (WDT) 14.4.2 Interval Timer Mode To use the WDT as an interval timer, set the WT/IT bit to 0 and the TME bit to 1 in TCSR. When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each time the TCNT overflows. Therefore, an interrupt can be generated at intervals. When the TCNT overflows in interval timer mode, an interval timer interrupt (WOVI) is requested at the same time the OVF bit in the TCSR is set to 1. TCNT value H'FF Overflow Overflow Overflow Overflow H'00 WT/IT = 0 TME = 1 WOVI WOVI WOVI WOVI Time [Legend] WOVI: Interval timer interrupt request Figure 14.3 Operation in Interval Timer Mode 14.5 Interrupt Source During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. The OVF flag must be cleared to 0 in the interrupt handling routine. Table 14.2 WDT Interrupt Source Name WOVI Interrupt Source TCNT overflow Interrupt Flag OVF DTC Activation Impossible Rev.1.00 Jun. 07, 2006 Page 648 of 1102 REJ09B0294-0100 Section 14 Watchdog Timer (WDT) 14.6 14.6.1 Usage Notes Notes on Register Access The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below. (1) Writing to TCNT, TCSR, and RSTCSR TCNT and TCSR must be written to by a word transfer instruction. They cannot be written to by a byte transfer instruction. For writing, TCNT and TCSR are assigned to the same address. Accordingly, perform data transfer as shown in figure 14.4. The transfer instruction writes the lower byte data to TCNT or TCSR. To write to RSTCSR, execute a word transfer instruction for address H'FFA6. A byte transfer instruction cannot be used to write to RSTCSR. The method of writing 0 to the WOVF bit in RSTCSR differs from that of writing to the RSTE bit in RSTCSR. Perform data transfer as shown in figure 14.4. At data transfer, the transfer instruction clears the WOVF bit to 0, but has no effect on the RSTE bit. To write to the RSTE bit, perform data transfer as shown in figure 14.4. In this case, the transfer instruction writes the value in bit 6 of the lower byte to the RSTE bit, but has no effect on the WOVF bit. TCNT write or writing to the RSTE bit in RSTCSR: 15 Address: H'FFA4 (TCNT) H'FFA6 (RSTCSR) 8 H'5A 7 Write data 0 TCSR write: Address: H'FFA4 (TCSR) 15 H'A5 8 7 Write data 0 Writing 0 to the WOVF bit in RSTCSR: 15 Address: H'FFA6 (RSTCSR) 8 H'A5 7 H'00 0 Figure 14.4 Writing to TCNT, TCSR, and RSTCSR Rev.1.00 Jun. 07, 2006 Page 649 of 1102 REJ09B0294-0100 Section 14 Watchdog Timer (WDT) (2) Reading from TCNT, TCSR, and RSTCSR These registers can be read from in the same way as other registers. For reading, TCSR is assigned to address H'FFA4, TCNT to address H'FFA5, and RSTCSR to address H'FFA7. 14.6.2 Conflict between Timer Counter (TCNT) Write and Increment If a TCNT clock pulse is generated during the T2 cycle of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 14.5 shows this operation. TCNT write cycle T1 P T2 Address Internal write signal TCNT input clock TCNT N M Counter write data Figure 14.5 Conflict between TCNT Write and Increment 14.6.3 Changing Values of Bits CKS2 to CKS0 If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in the incrementation. The watchdog timer must be stopped (by clearing the TME bit to 0) before the values of bits CKS2 to CKS0 are changed. 14.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode If the timer mode is switched from watchdog timer mode to interval timer mode while the WDT is operating, errors could occur in the incrementation. The watchdog timer must be stopped (by clearing the TME bit to 0) before switching the timer mode. Rev.1.00 Jun. 07, 2006 Page 650 of 1102 REJ09B0294-0100 Section 14 Watchdog Timer (WDT) 14.6.5 Internal Reset in Watchdog Timer Mode This LSI is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during watchdog timer mode operation, but TCNT and TCSR of the WDT are reset. TCNT, TCSR, and RSTCR cannot be written to while the WDTOVF signal is low. Also note that a read of the WOVF flag is not recognized during this period. To clear the WOVF flag, therefore, read TCSR after the WDTOVF signal goes high, then write 0 to the WOVF flag. 14.6.6 System Reset by WDTOVF Signal If the WDTOVF signal is input to the RES pin, this LSI will not be initialized correctly. Make sure that the WDTOVF signal is not input logically to the RES pin. To reset the entire system by means of the WDTOVF signal, use a circuit like that shown in figure 14.6. This LSI Reset input RES Reset signal to entire system WDTOVF Figure 14.6 Circuit for System Reset by WDTOVF Signal (Example) 14.6.7 Transition to Watchdog Timer Mode or Software Standby Mode When the WDT operates in watchdog timer mode, a transition to software standby mode is not made even when the SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1. Instead, a transition to sleep mode is made. To transit to software standby mode, the SLEEP instruction must be executed after halting the WDT (clearing the TME bit to 0). When the WDT operates in interval timer mode, a transition to software standby mode is made through execution of the SLEEP instruction when the SSBY bit in SBYCR is set to 1. Rev.1.00 Jun. 07, 2006 Page 651 of 1102 REJ09B0294-0100 Section 14 Watchdog Timer (WDT) Rev.1.00 Jun. 07, 2006 Page 652 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) Section 15 Serial Communication Interface (SCI, IrDA, CRC) This LSI has six independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial communication. Asynchronous serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). A function is also provided for serial communication between processors (multiprocessor communication function). The SCI also supports the smart card (smart card) interface supporting ISO/IEC 7816-3 (Identification Card) as an extended asynchronous communication mode. SCI_5 enables transmitting and receiving IrDA communication waveform based on the IrDA Specifications version 1.0. This LSI incorporates the on-chip CRC (Cyclic Redundancy Check) computing unit that realizes high reliability of high-speed data transfer. Since the CRC computing unit is not connected to SCI, operation is executed by writing data to registers. Figure 15.1 shows a block diagram of the SCI_0 to SCI_4. Figure 15.2 shows a block diagram of the SCI_5 and SCI_6. 15.1 Features * Choice of asynchronous or clocked synchronous serial communication mode * Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. * On-chip baud rate generator allows any bit rate to be selected The external clock can be selected as a transfer clock source (except for the smart card interface). * Choice of LSB-first or MSB-first transfer (except in the case of asynchronous mode 7-bit data) * Four interrupt sources The interrupt sources are transmit-end, transmit-data-empty, receive-data-full, and receive error. The transmit-data-empty and receive-data-full interrupt sources can activate the DTC or DMAC. * Module stop state specifiable Rev.1.00 Jun. 07, 2006 Page 653 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) Asynchronous Mode (SCI_0, 1, 2, 4, 5, and 6): * * * * * Data length: 7 or 8 bits Stop bit length: 1 or 2 bits Parity: Even, odd, or none Receive error detection: Parity, overrun, and framing errors Break detection: Break can be detected by reading the RxD pin level directly in case of a framing error * Enables transfer rate clock input from TMR (SCI_5, SCI_6) * Average transfer rate generator (SCI_2) 10.667-MHz operation: 115.192 kbps or 460.784 kbps can be selected 16-MHz operation: 115.192 kbps, 460.784 kbps, or 720 kbps can be selected 32-MHz operation: 720 kbps * Average transfer rate generator (SCI_5, SCI_6) 8-MHz operation: 460.784 kbps can be selected 10.667-MHz operation: 115.152 kbps or 460.606 kbps can be selected 12-MHz operation: 230.263 kbps or 460.526 kbps can be selected 16-MHz operation: 115.196 kbps, 460.784 kbps, 720 kbps, or 921.569 kbps can be selected 24-MHz operation: 115.132 kbps, 460.526 kbps, 720 kbps, or 921.053 kbps can be selected 32-MHz operation: 720 kbps can be selected Clocked Synchronous Mode (SCI_0, 1, 2, and 4): * Data length: 8 bits * Receive error detection: Overrun errors Smart Card Interface: * An error signal can be automatically transmitted on detection of a parity error during reception * Data can be automatically re-transmitted on receiving an error signal during transmission * Both direct convention and inverse convention are supported Rev.1.00 Jun. 07, 2006 Page 654 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) Table 15.1 lists the functions of each channel. Table 15.1 Function List of SCI Channels SCI_0, 1, 4 Clocked synchronous mode Asynchronous mode TMR clock input When average transfer rate generator is used P = 8 Hz O O -- -- SCI_2 O O -- -- 460.784 kbps 115.192 kbps P = 12 Hz P = 16 Hz -- -- -- 720 kbps 460 784kbps 115.192 kbps P = 24 Hz -- -- SCI_5, SCI_6 -- O O 460.784 kbps 460.606 kbps 115.152 kbps 460.526 kbps 230.263 kbps 921.569 kbps 720 kbps 460.784 kbps 115.196 kbps 921.053 kbps 720 kbps 460.526 kbps 115.132 kbps P = 32 Hz -- 720 kbps 720 kbps P = 10.667 Hz -- Rev.1.00 Jun. 07, 2006 Page 655 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) Module data bus RDR TDR SCMR SSR SCR BRR P Baud rate generator P/4 P/16 RxD RSR TSR SMR Transmission/ reception control P/64 Clock Average transfer rate generator (SCI_2) At 10.667-MHz operation: 115.192 kbps 460.784 kbps At 16-MHz operation: 115.192 kbps 460.784 kbps 720 kbps At 32-MHz operation: 720 kbps TxD Parity check SCK Parity generation External clock TEI TXI RXI ERI SCR: SSR: SCMR: BRR: SEMR: [Legend] RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode register Serial control register Serial status register Smart card mode register Bit rate register Serial extended mode register (available only for SCI_2) Figure 15.1 Block Diagram of SCI_0, 1, 2, and 4 Rev.1.00 Jun. 07, 2006 Page 656 of 1102 REJ09B0294-0100 Internal data bus Bus interface Section 15 Serial Communication Interface (SCI, IrDA, CRC) Module data bus RDR TDR SCMR SSR SCR BRR P Baud rate generator P/4 P/16 RxD0 RSR TSR IrCR* Transmission/ reception control Bus interface P/64 Clock TEI TXI RXI ERI Average transfer rate generator At 8-MHz operation: 460.784 kbps At 10.667-MHz operation: 115.152 kbps 460.606 kbps At 12-MHz operation: 230.263 kbps 460.526 kbps At 16-MHz operation: 115.196 kbps 460.784 kbps 720 kbps, 921.569 kbps At 24-MHz operation: 115.132 kbps 460.526 kbps 720 kbps 921.053 kbps At 32-MHz operation: 720 kbps TxD0 Parity check Parity generation Note: * SCL_5 only. [Legend] RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode register SCR: Serial control register SSR: Serial status register SCMR: Smart card mode register BRR: Bit rate register SEMR: Serial extended mode register IrCR: IrDA control register (available only for SCI_5) TMO4, 6 TMO5, 7 TMR Figure 15.2 Block Diagram of SCI_5 and SCI_6 Rev.1.00 Jun. 07, 2006 Page 657 of 1102 REJ09B0294-0100 Internal data bus Section 15 Serial Communication Interface (SCI, IrDA, CRC) 15.2 Input/Output Pins Table 15.2 lists the pin configuration of the SCI. Table 15.2 Pin Configuration Channel 0 Pin Name* SCK0 RxD0 TxD0 1 SCK1 RxD1 TxD1 2 SCK2 RxD2 TxD2 3 SCK3 RxD3 TxD3 4 SCK4 RxD4 TxD4 5 RxD5/IrRxD TxD5/IrTxD 6 Note: * RxD6 TxD6 I/O I/O Input Output I/O Input Output I/O Input Output I/O Input Output I/O Input Output Input Output Input Output Function Channel 0 clock input/output Channel 0 receive data input Channel 0 transmit data output Channel 1 clock input/output Channel 1 receive data input Channel 1 transmit data output Channel 2 clock input/output Channel 2 receive data input Channel 2 transmit data output Channel 3 clock input/output Channel 3 receive data input Channel 3 transmit data output Channel 4 clock input/output Channel 4 receive data input Channel 4 transmit data output Channel 5 receive data input Channel 5 transmit data output Channel 6 receive data input Channel 6 transmit data output Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the channel designation. Rev.1.00 Jun. 07, 2006 Page 658 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) 15.3 Register Descriptions The SCI has the following registers. Some bits in the serial mode register (SMR), serial status register (SSR), and serial control register (SCR) have different functions in different modesnormal serial communication interface mode and smart card interface mode; therefore, the bits are described separately for each mode in the corresponding register sections. Channel 0: * * * * * * * * * Receive shift register_0 (RSR_0) Transmit shift register_0 (TSR_0) Receive data register_0 (RDR_0) Transmit data register_0 (TDR_0) Serial mode register_0 (SMR_0) Serial control register_0 (SCR_0) Serial status register_0 (SSR_0) Smart card mode register_0 (SCMR_0) Bit rate register_0 (BRR_0) Channel 1: * * * * * * * * * Receive shift register_1 (RSR_1) Transmit shift register_1 (TSR_1) Receive data register_1 (RDR_1) Transmit data register_1 (TDR_1) Serial mode register_1 (SMR_1) Serial control register_1 (SCR_1) Serial status register_1 (SSR_1) Smart card mode register_1 (SCMR_1) Bit rate register_1 (BRR_1) Rev.1.00 Jun. 07, 2006 Page 659 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) Channel 2: * * * * * * * * * * Receive shift register_2 (RSR_2) Transmit shift register_2 (TSR_2) Receive data register_2 (RDR_2) Transmit data register_2 (TDR_2) Serial mode register_2 (SMR_2) Serial control register_2 (SCR_2) Serial status register_2 (SSR_2) Smart card mode register_2 (SCMR_2) Bit rate register_2 (BRR_2) Serial extended mode register_2 (SEMR_2) Channel 4: * Receive shift register_4 (RSR_4) * Transmit shift register_4 (TSR_4) * Receive data register_4 (RDR_4) * Transmit data register_4 (TDR_4) * Serial mode register_4 (SMR_4) * Serial control register_4 (SCR_4) * Serial status register_4 (SSR_4) * Smart card mode register_4 (SCMR_4) * Bit rate register_4 (BRR_4) Channel 5: * Receive shift register_5 (RSR_5) * Transmit shift register_5 (TSR_5) * Receive data register_5 (RDR_5) * Transmit data register_5 (TDR_5) * Serial mode register_5 (SMR_5) * Serial control register_5 (SCR_5) * Serial status register_5 (SSR_5) * Smart card mode register_5 (SCMR_5) * Bit rate register_5 (BRR_5) * Serial extended mode register_5 (SEMR_5) * IrDA control register_5 (IrCR) Rev.1.00 Jun. 07, 2006 Page 660 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) Channel 6: * Receive shift register_6 (RSR_6) * Transmit shift register_6 (TSR_6) * Receive data register_6 (RDR_6) * Transmit data register_6 (TDR_6) * Serial mode register_6 (SMR_6) * Serial control register_6 (SCR_6) * Serial status register_6 (SSR_6) * Smart card mode register_6 (SCMR_6) * Serial extended mode register_6 (SEMR_6) * Bit rate register_6 (BRR_6) 15.3.1 Receive Shift Register (RSR) RSR is a shift register which is used to receive serial data input from the RxD pin and converts it into parallel data. When one frame of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU. 15.3.2 Receive Data Register (RDR) RDR is an 8-bit register that stores receive data. When the SCI has received one frame of serial data, it transfers the received serial data from RSR to RDR where it is stored. This allows RSR to receive the next data. Since RSR and RDR function as a double buffer in this way, continuous receive operations can be performed. After confirming that the RDRF bit in SSR is set to 1, read RDR only once. RDR cannot be written to by the CPU. Bit Bit Name Initial Value R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 7 6 5 4 3 2 1 0 Rev.1.00 Jun. 07, 2006 Page 661 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) 15.3.3 Transmit Data Register (TDR) TDR is an 8-bit register that stores transmit data. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered structures of TDR and TSR enable continuous serial transmission. If the next transmit data has already been written to TDR when one frame of data is transmitted, the SCI transfers the written data to TSR to continue transmission. Although TDR can be read from or written to by the CPU at all times, to achieve reliable serial transmission, write transmit data to TDR for only once after confirming that the TDRE bit in SSR is set to 1. Bit Bit Name Initial Value R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 7 6 5 4 3 2 1 0 15.3.4 Transmit Shift Register (TSR) TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first automatically transfers transmit data from TDR to TSR, and then sends the data to the TxD pin. TSR cannot be directly accessed by the CPU. 15.3.5 Serial Mode Register (SMR) SMR is used to set the SCI's serial transfer format and select the baud rate generator clock source. Some bits in SMR have different functions in normal mode and smart card interface mode. * When SMIF in SCMR = 0 Bit Bit Name Initial Value R/W 7 C/A 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W * When SMIF in SCMR = 1 Bit Bit Name Initial Value R/W 7 GM 0 R/W 6 BLK 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 BCP1 0 R/W 2 BCP0 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Rev.1.00 Jun. 07, 2006 Page 662 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) Bit Functions in Normal Serial Communication Interface Mode (When SMIF in SCMR = 0): Bit 7 Bit Name C/A Initial Value 0 R/W R/W Description Communication Mode 0: Asynchronous mode 1: Clocked synchronous mode* 6 CHR 0 R/W Character Length (valid only in asynchronous mode) 0: Selects 8 bits as the data length. 1: Selects 7 bits as the data length. LSB-first is fixed and the MSB (bit 7) in TDR is not transmitted in transmission. In clocked synchronous mode, a fixed data length of 8 bits is used. 5 PE 0 R/W Parity Enable (valid only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. For a multiprocessor format, parity bit addition and checking are not performed regardless of the PE bit setting. 4 O/E 0 R/W Parity Mode (valid only when the PE bit is 1 in asynchronous mode) 0: Selects even parity. 1: Selects odd parity. 3 STOP 0 R/W Stop Bit Length (valid only in asynchronous mode) Selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits In reception, only the first stop bit is checked. If the second stop bit is 0, it is treated as the start bit of the next transmit frame. 2 MP 0 R/W Multiprocessor Mode (valid only in asynchronous mode) When this bit is set to 1, the multiprocessor function is enabled. The PE bit and O/E bit settings are invalid in multiprocessor mode. Rev.1.00 Jun. 07, 2006 Page 663 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) Bit 1 0 Bit Name CKS1 CKS0 Initial Value 0 0 R/W R/W R/W Description Clock Select 1, 0 These bits select the clock source for the baud rate generator. 00: P clock (n = 0) 01: P/4 clock (n = 1) 10: P/16 clock (n = 2) 11: P/64 clock (n = 3) For the relation between the settings of these bits and the baud rate, see section 15.3.9, Bit Rate Register (BRR). n is the decimal display of the value of n in BRR (see section 15.3.9, Bit Rate Register (BRR)). Note: * Available in SCI_0, 1, 2, and 4 only. Setting is prohibited in SCI_5 and SCI_6. Bit Functions in Smart Card Interface Mode (When SMIF in SCMR = 1): Bit 7 Bit Name GM Initial Value 0 R/W R/W Description GSM Mode Setting this bit to 1 allows GSM mode operation. In GSM mode, the TEND set timing is put forward to 11.0 etu from the start and the clock output control function is appended. For details, see sections 15.7.6, Data Transmission (Except in Block Transfer Mode) and 15.7.8, Clock Output Control. 6 5 BLK PE 0 0 R/W R/W Setting this bit to 1 allows block transfer mode operation. For details, see section 15.7.3, Block Transfer Mode. Parity Enable (valid only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. Set this bit to 1 in smart card interface mode. 4 O/E 0 R/W Parity Mode (valid only when the PE bit is 1 in asynchronous mode) 0: Selects even parity 1: Selects odd parity For details on the usage of this bit in smart card interface mode, see section 15.7.2, Data Format (Except in Block Transfer Mode). Rev.1.00 Jun. 07, 2006 Page 664 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) Bit 3 2 Bit Name BCP1 BCP0 Initial Value 0 0 R/W R/W R/W Description Base clock Pulse 1, 0 These bits select the number of base clock cycles in a 1bit data transfer time in smart card interface mode. 00: 32 clock cycles (S = 32) 01: 64 clock cycles (S = 64) 10: 372 clock cycles (S = 372) 11: 256 clock cycles (S = 256) For details, see section 15.7.4, Receive Data Sampling Timing and Reception Margin. S is described in section 15.3.9, Bit Rate Register (BRR). 1 0 CKS1 CKS0 0 0 R/W R/W Clock Select 1, 0 These bits select the clock source for the baud rate generator. 00: P clock (n = 0) 01: P/4 clock (n = 1) 10: P/16 clock (n = 2) 11: P/64 clock (n = 3) For the relation between the settings of these bits and the baud rate, see section 15.3.9, Bit Rate Register (BRR). n is the decimal display of the value of n in BRR (see section 15.3.9, Bit Rate Register (BRR)). Note: etu (Elementary Time Unit): 1-bit transfer time Rev.1.00 Jun. 07, 2006 Page 665 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) 15.3.6 Serial Control Register (SCR) SCR is a register that enables/disables the following SCI transfer operations and interrupt requests, and selects the transfer clock source. For details on interrupt requests, see section 15.9, Interrupt Sources. Some bits in SCR have different functions in normal mode and smart card interface mode. * When SMIF in SCMR = 0 Bit Bit Name Initial Value R/W 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W * When SMIF in SCMR = 1 Bit Bit Name Initial Value R/W 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W Bit Functions in Normal Serial Communication Interface Mode (When SMIF in SCMR = 0): Initial Value 0 Bit 7 Bit Name TIE R/W R/W Description Transmit Interrupt Enable When this bit is set to 1, a TXI interrupt request is enabled. A TXI interrupt request can be cancelled by reading 1 from the TDRE flag and then clearing the flag to 0, or by clearing the TIE bit to 0. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. RXI and ERI interrupt requests can be cancelled by reading 1 from the RDRF, FER, PER, or ORER flag and then clearing the flag to 0, or by clearing the RIE bit to 0. Rev.1.00 Jun. 07, 2006 Page 666 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) Bit 5 Bit Name TE Initial Value 0 R/W R/W Description Transmit Enable When this bit is set to 1, transmission is enabled. Under this condition, serial transmission is started by writing transmit data to TDR, and clearing the TDRE flag in SSR to 0. Note that SMR should be set prior to setting the TE bit to 1 in order to designate the transmission format. If transmission is halted by clearing this bit to 0, the TDRE flag in SSR is fixed to 1. 4 RE 0 R/W Receive Enable When this bit is set to 1, reception is enabled. Under this condition, serial reception is started by detecting the start bit in asynchronous mode or the synchronous clock input in clocked synchronous mode. Note that SMR should be set prior to setting the RE bit to 1 in order to designate the reception format. Even if reception is halted by clearing this bit to 0, the RDRF, FER, PER, and ORER flags are not affected and the previous value is retained. 3 MPIE 0 R/W Multiprocessor Interrupt Enable (valid only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and ORER status flags in SSR is disabled. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. For details, see section 15.5, Multiprocessor Communication Function. When receive data including MPB = 0 in SSR is being received, transfer of the received data from RSR to RDR, detection of reception errors, and the settings of RDRF, FER, and ORER flags in SSR are not performed. When receive data including MPB = 1 is received, the MPB bit in SSR is set to 1, the MPIE bit is automatically cleared to 0, and RXI and ERI interrupt requests (in the case where the TIE and RIE bits in SCR are set to 1) and setting of the FER and ORER flags are enabled. Rev.1.00 Jun. 07, 2006 Page 667 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) Bit 2 Bit Name TEIE Initial Value 0 R/W R/W Description Transmit End Interrupt Enable When this bit is set to 1, a TEI interrupt request is enabled. A TEI interrupt request can be cancelled by reading 1 from the TDRE flag and then clearing the flag to 0 in order to clear the TEND flag to 0, or by clearing the TEIE bit to 0. 1 0 CKE1 CKE0 0 0 R/W R/W Clock Enable 1, 0 (for SCI_0, 1, and 4) These bits select the clock source and SCK pin function. * Asynchronous mode The SCK pin functions as I/O port. 01: On-chip baud rate generator The clock with the same frequency as the bit rate is output from the SCK pin. 1X: External clock The clock with a frequency 16 times the bit rate should be input from the SCK pin. * Clocked synchronous mode The SCK pin functions as the clock output pin. 1X: External clock The SCK pin functions as the clock input pin. 0X: Internal clock 00: On-chip baud rate generator Rev.1.00 Jun. 07, 2006 Page 668 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) Bit 1 0 Bit Name CKE1 CKE0 Initial Value 0 0 R/W R/W R/W Description Clock Enable 1, 0 (for SCI_2) These bits select the clock source and SCK pin function. * Asynchronous mode The SCK pin functions as I/O port. 01: On-chip baud rate generator The clock with the same frequency as the bit rate is output from the SCK pin. 1X: External clock or average transfer rate generator When an external clock is used, the clock with a frequency 16 times the bit rate should be input from the SCK pin. When an average transfer rate generator is used. * Clocked synchronous mode The SCK pin functions as the clock output pin. 1X: External clock The SCK pin functions as the clock input pin. 0X: Internal clock 00: On-chip baud rate generator 1 0 CKE1 CKE0 0 0 R/W R/W Clock Enable 1, 0 (for SCI_5 and SCI_6) These bits select the clock source. * Asynchronous mode 00: On-chip baud rate generator 1X: TMR clock input or average transfer rate generator When an average transfer rate generator is used. When TMR clock input is used. * Clocked synchronous mode Not available [Legend] X: Don't care Rev.1.00 Jun. 07, 2006 Page 669 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) Bit Functions in Smart Card Interface Mode (When SMIF in SCMR = 1): Bit 7 Bit Name TIE Initial Value 0 R/W R/W Description Transmit Interrupt Enable When this bit is set to 1,a TXI interrupt request is enabled. A TXI interrupt request can be cancelled by reading 1 from the TDRE flag and then clearing the flag to 0, or by clearing the TIE bit to 0. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. RXI and ERI interrupt requests can be cancelled by reading 1 from the RDRF, FER, PER, or ORER flag and then clearing the flag to 0, or by clearing the RIE bit to 0. 5 TE 0 R/W Transmit Enable When this bit is set to 1, transmission is enabled. Under this condition, serial transmission is started by writing transmit data to TDR, and clearing the TDRE flag in SSR to 0. Note that SMR should be set prior to setting the TE bit to 1 in order to designate the transmission format. If transmission is halted by clearing this bit to 0, the TDRE flag in SSR is fixed 1. 4 RE 0 R/W Receive Enable When this bit is set to 1, reception is enabled. Under this condition, serial reception is started by detecting the start bit in asynchronous mode or the synchronous clock input in clocked synchronous mode. Note that SMR should be set prior to setting the RE bit to 1 in order to designate the reception format. Even if reception is halted by clearing this bit to 0, the RDRF, FER, PER, and ORER flags are not affected and the previous value is retained. 3 MPIE 0 R/W Multiprocessor Interrupt Enable (valid only when the MP bit in SMR is 1 in asynchronous mode) Write 0 to this bit in smart card interface mode. 2 TEIE 0 R/W Transmit End Interrupt Enable Write 0 to this bit in smart card interface mode. Rev.1.00 Jun. 07, 2006 Page 670 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) Bit 1 0 Bit Name CKE1 CKE0 Initial Value 0 0 R/W R/W R/W Description Clock Enable 1, 0* These bits control the clock output from the SCK pin. In GSM mode, clock output can be dynamically switched. For details, see section 15.7.8, Clock Output Control. * When GM in SMR = 0 00: Output disabled (SCK pin functions as I/O port.) * 01: Clock output 1X: Reserved * When GM in SMR = 1 00: Output fixed low 01: Clock output 10: Output fixed high 11: Clock output Note: * No SCK pins exist in SCI_5 and SCI_6. 15.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. TDRE, RDRF, ORER, PER, and FER can only be cleared. Some bits in SSR have different functions in normal mode and smart card interface mode. * When SMIF in SCMR = 0 Bit Bit Name Initial Value R/W 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FRE 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W Note: * Only 0 can be written, to clear the flag. Rev.1.00 Jun. 07, 2006 Page 671 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) * When SMIF in SCMR = 1 Bit Bit Name Initial Value R/W 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 ERS 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W Note: * Only 0 can be written, to clear the flag. Bit Functions in Normal Serial Communication Interface Mode (When SMIF in SCMR = 0): Initial Value 1 Bit 7 Bit Name TDRE R/W Description R/(W)* Transmit Data Register Empty Indicates whether TDR contains transmit data. [Setting conditions] * * * When the TE bit in SCR is 0 When data is transferred from TDR to TSR When 0 is written to TDRE after reading TDRE = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) * When a TXI interrupt request is issued allowing DMAC or DTC to write data to TDR [Clearing conditions] Rev.1.00 Jun. 07, 2006 Page 672 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) Bit 6 Bit Name RDRF Initial Value 0 R/W Description R/(W)* Receive Data Register Full Indicates whether receive data is stored in RDR. [Setting condition] * When serial reception ends normally and receive data is transferred from RSR to RDR When 0 is written to RDRF after reading RDRF = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) * When an RXI interrupt request is issued allowing DMAC or DTC to read data from RDR [Clearing conditions] * The RDRF flag is not affected and retains its previous value when the RE bit in SCR is cleared to 0. Note that when the next serial reception is completed while the RDRF flag is being set to 1, an overrun error occurs and the received data is lost. 5 ORER 0 R/(W)* Overrun Error Indicates that an overrun error has occurred during reception and the reception ends abnormally. [Setting condition] * When the next serial reception is completed while RDRF = 1 In RDR, receive data prior to an overrun error occurrence is retained, but data received after the overrun error occurrence is lost. When the ORER flag is set to 1, subsequent serial reception cannot be performed. Note that, in clocked synchronous mode, serial transmission also cannot continue. [Clearing condition] * When 0 is written to ORER after reading ORER = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) Even when the RE bit in SCR is cleared, the ORER flag is not affected and retains its previous value. Rev.1.00 Jun. 07, 2006 Page 673 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) Bit 4 Bit Name FER Initial Value 0 R/W Description R/(W)* Framing Error Indicates that a framing error has occurred during reception in asynchronous mode and the reception ends abnormally. [Setting condition] * When the stop bit is 0 In 2-stop-bit mode, only the first stop bit is checked whether it is 1 but the second stop bit is not checked. Note that receive data when the framing error occurs is transferred to RDR, however, the RDRF flag is not set. In addition, when the FER flag is being set to 1, the subsequent serial reception cannot be performed. In clocked synchronous mode, serial transmission also cannot continue. [Clearing condition] * When 0 is written to FER after reading FER = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) Even when the RE bit in SCR is cleared, the FER flag is not affected and retains its previous value. Rev.1.00 Jun. 07, 2006 Page 674 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) Bit 3 Bit Name PER Initial Value 0 R/W Description R/(W)* Parity Error Indicates that a parity error has occurred during reception in asynchronous mode and the reception ends abnormally. [Setting condition] * When a parity error is detected during reception Receive data when the parity error occurs is transferred to RDR, however, the RDRF flag is not set. Note that when the PER flag is being set to 1, the subsequent serial reception cannot be performed. In clocked synchronous mode, serial transmission also cannot continue. [Clearing condition] * When 0 is written to PER after reading PER = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) Even when the RE bit in SCR is cleared, the PER bit is not affected and retains its previous value. 2 TEND 1 R Transmit End [Setting conditions] * * When the TE bit in SCR is 0 When TDRE = 1 at transmission of the last bit of a transmit character When 0 is written to TDRE after reading TDRE = 1 When a TXI interrupt request is issued allowing DMAC or DTC to write data to TDR [Clearing conditions] * * 1 MPB 0 R Multiprocessor Bit Stores the multiprocessor bit value in the receive frame. When the RE bit in SCR is cleared to 0 its previous state is retained. 0 MPBT 0 R/W Multiprocessor Bit Transfer Sets the multiprocessor bit value to be added to the transmit frame. Note: * Only 0 can be written, to clear the flag. Rev.1.00 Jun. 07, 2006 Page 675 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) Bit Functions in Smart Card Interface Mode (When SMIF in SCMR = 1): Bit 7 Bit Name TDRE Initial Value 1 R/W Description R/(W)* Transmit Data Register Empty Indicates whether TDR contains transmit data. [Setting conditions] * * * When the TE bit in SCR is 0 When data is transferred from TDR to TSR When 0 is written to TDRE after reading TDRE = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) * When a TXI interrupt request is issued allowing DMAC or DTC to write data to TDR [Clearing conditions] 6 RDRF 0 R/(W)* Receive Data Register Full Indicates whether receive data is stored in RDR. [Setting condition] * When serial reception ends normally and receive data is transferred from RSR to RDR When 0 is written to RDRF after reading RDRF = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) * When an RXI interrupt request is issued allowing DMAC or DTC to read data from RDR [Clearing conditions] * The RDRF flag is not affected and retains its previous value even when the RE bit in SCR is cleared to 0. Note that when the next reception is completed while the RDRF flag is being set to 1, an overrun error occurs and the received data is lost. Rev.1.00 Jun. 07, 2006 Page 676 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) Bit 5 Bit Name ORER Initial Value 0 R/W Description Indicates that an overrun error has occurred during reception and the reception ends abnormally. [Setting condition] * When the next serial reception is completed while RDRF = 1 In RDR, the receive data prior to an overrun error occurrence is retained, but data received following the overrun error occurrence is lost. When the ORER flag is set to 1, subsequent serial reception cannot be performed. Note that, in clocked synchronous mode, serial transmission also cannot continue. [Clearing condition] * When 0 is written to ORER after reading ORER = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) Even when the RE bit in SCR is cleared, the ORER flag is not affected and retains its previous value. R/(W)* Overrun Error 4 ERS 0 R/(W)* Error Signal Status [Setting condition] * * When a low error signal is sampled When 0 is written to ERS after reading ERS = 1 [Clearing condition] Rev.1.00 Jun. 07, 2006 Page 677 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) Bit 3 Bit Name PER Initial Value 0 R/W Description Indicates that a parity error has occurred during reception in asynchronous mode and the reception ends abnormally. [Setting condition] * When a parity error is detected during reception Receive data when the parity error occurs is transferred to RDR, however, the RDRF flag is not set. Note that when the PER flag is being set to 1, the subsequent serial reception cannot be performed. In clocked synchronous mode, serial transmission also cannot continue. [Clearing condition] * When 0 is written to PER after reading PER = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) Even when the RE bit in SCR is cleared, the PER flag is not affected and retains its previous value. R/(W)* Parity Error Rev.1.00 Jun. 07, 2006 Page 678 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) Bit 2 Bit Name TEND Initial Value 1 R/W R Description Transmit End This bit is set to 1 when no error signal is sent from the receiving side and the next transmit data is ready to be transferred to TDR. [Setting conditions] * * When both the TE and ERS bits in SCR are 0 When ERS = 0 and TDRE = 1 after a specified time passed after completion of 1-byte data transfer. The set timing depends on the register setting as follows: When GM = 0 and BLK = 0, 2.5 etu after transmission start When GM = 0 and BLK = 1, 1.5 etu after transmission start When GM = 1 and BLK = 0, 1.0 etu after transmission start When GM = 1 and BLK = 1, 1.0 etu after transmission start [Clearing conditions] * * When 0 is written to TEND after reading TEND = 1 When a TXI interrupt request is issued allowing DMAC or DTC to write the next data to TDR 1 0 Note: * MPB MPBT 0 0 R R/W Multiprocessor Bit Not used in smart card interface mode. Multiprocessor Bit Transfer Write 0 to this bit in smart card interface mode. Only 0 can be written, to clear the flag. Rev.1.00 Jun. 07, 2006 Page 679 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) 15.3.8 Smart Card Mode Register (SCMR) SCMR selects smart card interface mode and its format. Bit Bit Name Initial Value R/W 7 1 6 1 5 1 4 1 3 SDIR 0 R/W 2 SINV 0 R/W 1 1 0 SMIF 0 R/W Bit 7 to 4 3 Bit Name SDIR Initial Value All 1 0 R/W R/W Description Reserved These bits are always read as 1. Smart Card Data Transfer Direction Selects the serial/parallel conversion format. 0: Transfer with LSB-first 1: Transfer with MSB-first This bit is valid only when the 8-bit data format is used for transmission/reception; when the 7-bit data format is used, data is always transmitted/received with LSB-first. 2 SINV 0 R/W Smart Card Data Invert Inverts the transmit/receive data logic level. This bit does not affect the logic level of the parity bit. To invert the parity bit, invert the O/E bit in SMR. 0: TDR contents are transmitted as they are. Receive data is stored as it is in RDR. 1: TDR contents are inverted before being transmitted. Receive data is stored in inverted form in RDR. 1 0 SMIF 1 0 R/W Reserved This bit is always read as 1. Smart Card Interface Mode Select When this bit is set to 1, smart card interface mode is selected. 0: Normal asynchronous or clocked synchronous mode 1: Smart card interface mode Rev.1.00 Jun. 07, 2006 Page 680 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) 15.3.9 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 15.2 shows the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and clocked synchronous mode, and smart card interface mode. The initial value of BRR is H'FF, and it can be read from or written to by the CPU at all times. Table 15.3 Relationships between N Setting in BRR and Bit Rate B Mode Asynchronous mode ABCS Bit Bit Rate 0 B= P x 10 64 x 2 6 2n - 1 Error -1 xB -1 Error (%) = { Error (%) = { P x 106 B x 64 x 2 2n - 1 - 1 } x 100 x (N + 1) - 1 } x 100 x (N + 1) 1 Clocked synchronous mode Smart card interface mode [Legend] B: N: P: n and S: B= P x 106 32 x 2 2n - 1 P x 106 B x 32 x 2 2n - 1 xB -1 N= P x 106 8x2 2n - 1 xB -1 P x 106 Error (%) = { BxSx2 2n + 1 N= P x 106 Sx2 2n + 1 xB - 1 } x 100 x (N + 1) Bit rate (bit/s) BRR setting for baud rate generator (0 N 255) Operating frequency (MHz) Determined by the SMR settings shown in the following table. SMR Setting SMR Setting n 0 1 2 3 BCP1 0 0 1 1 BCP0 0 1 0 1 S 32 64 372 256 CKS1 0 0 1 1 CKS0 0 1 0 1 Rev.1.00 Jun. 07, 2006 Page 681 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) Table 15.4 shows sample N settings in BRR in normal asynchronous mode. Table 15.5 shows the maximum bit rate settable for each operating frequency. Tables 15.7 and 15.9 show sample N settings in BRR in clocked synchronous mode and smart card interface mode, respectively. In smart card interface mode, the number of base clock cycles S in a 1-bit data transfer time can be selected. For details, see section 15.7.4, Receive Data Sampling Timing and Reception Margin. Tables 15.6 and 15.8 show the maximum bit rates with external clock input. When the ABCS bit in the serial extended mode register_2, 5, and 6 (SEMR_2, 5, and 6) of SCI_2, 5, and 6 are set to 1 in asynchronous mode, the bit rate is two times that of shown in table 15.4. Table 15.4 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) Operating Frequency P (MHz) 8 Bit Rate (bit/s) n 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 2 2 1 1 0 0 0 0 0 0 N 141 103 207 103 207 103 51 25 12 7 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 n 2 2 1 1 0 0 0 0 0 0 0 9.8304 N 174 127 255 127 255 127 63 31 15 9 7 Error (%) -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 2 2 2 1 1 0 0 0 0 0 0 N 177 129 64 129 64 129 64 32 15 9 7 10 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 0.00 1.73 n 2 2 2 1 1 0 0 0 0 0 0 N 212 155 77 155 77 155 77 38 19 11 9 12 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 0.00 -2.34 Rev.1.00 Jun. 07, 2006 Page 682 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) Operating Frequency P (MHz) 12.288 Bit Rate (bit/s) n 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 2 2 2 1 1 0 0 0 0 0 0 N 217 159 79 159 79 159 79 39 19 11 9 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 n 2 2 2 1 1 0 0 0 0 0 N 248 181 90 181 90 181 90 45 22 13 14 Error (%) -0.17 0.16 0.16 0.16 0.16 0.16 0.16 -0.93 -0.93 0.00 n 3 2 2 1 1 0 0 0 0 0 0 14.7456 N 64 191 95 191 95 191 95 47 23 14 11 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 3 2 2 1 1 0 0 0 0 0 0 N 70 207 103 207 103 207 103 51 25 15 12 16 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16 Note: In SCI_2, 5, and 6, this is an example when the ABCS bit in SEMR_2, 5, and 6 is 0. When the ABCS bit is set to 1, the bit rate is two times. Table 15.4 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) Operating Frequency P (MHz) 17.2032 Bit Rate (bit/s) n 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 3 2 2 1 1 0 0 0 0 0 0 N 75 223 111 223 111 223 111 55 27 16 13 Error (%) 0.48 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 1.20 0.00 n 3 2 2 1 1 0 0 0 0 0 0 N 79 233 116 233 116 233 116 58 28 17 14 18 Error (%) -0.12 0.16 0.16 0.16 0.16 0.16 0.16 -0.69 1.02 0.00 -2.34 n 3 2 2 1 1 0 0 0 0 0 0 19.6608 N 86 255 127 255 127 255 127 63 31 19 15 Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 3 3 2 2 1 1 0 0 0 0 0 N 88 64 129 64 129 64 129 64 32 19 15 20 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 0.00 1.73 Rev.1.00 Jun. 07, 2006 Page 683 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) Operating Frequency P (MHz) 25 Bit Rate (bit/s) n 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 3 3 2 2 1 1 0 0 0 0 0 N 110 80 162 80 162 80 162 80 40 24 19 Error (%) -0.02 -0.47 0.15 -0.47 0.15 -0.47 0.15 -0.47 -0.76 0.00 1.73 n 3 3 2 2 1 1 0 0 0 0 0 N 132 97 194 97 194 97 194 97 48 29 23 30 Error (%) 0.13 -0.35 0.16 -0.35 0.16 -0.35 0.16 -0.35 -0.35 0 1.73 n 3 3 2 2 1 1 0 0 0 0 0 N 145 106 214 106 214 106 214 106 53 32 26 33 Error (%) 0.33 0.39 -0.07 0.39 -0.07 0.39 -0.07 0.39 -0.54 0 -0.54 n 3 3 2 2 1 1 0 0 0 0 0 N 154 113 227 113 227 113 227 113 56 34 28 35 Error (%) 0.23 -0.66 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.78 Note: In SCI_2, 5, and 6, this is an example when the ABCS bit in SEMR_2, 5, and 6 is 0. When the ABCS bit is set to 1, the bit rate is two times. Table 15.5 Maximum Bit Rate for Each Operating Frequency (Asynchronous Mode) Maximum Bit Rate (bit/s) 250000 307200 312500 375000 384000 437500 460800 500000 Maximum Bit Rate (bit/s) 537600 562500 614400 625000 781250 937500 1031250 1093750 P (MHz) 8 9.8304 10 12 12.288 14 14.7456 16 n 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 P (MHz) 17.2032 18 19.6608 20 25 30 33 35 n 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 Rev.1.00 Jun. 07, 2006 Page 684 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) Table 15.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode) P (MHz) 8 9.8304 10 12 12.288 14 14.7456 16 External Input Clock (MHz) 2.0000 2.4576 2.5000 3.0000 3.0720 3.5000 3.6864 4.0000 Maximum Bit Rate (bit/s) 125000 153600 156250 187500 192000 218750 230400 250000 P (MHz) 17.2032 18 19.6608 20 25 30 33 35 External Input Clock (MHz) 4.3008 4.5000 4.9152 5.0000 6.2500 7.5000 8.2500 8.7500 Maximum Bit Rate (bit/s) 268800 281250 307200 312500 390625 468750 515625 546875 Note: In SCI_2, this is an example when the ABCS bit in SEMR_2 is 0. When the ABCS bit is set to 1, the bit rate is two times. Rev.1.00 Jun. 07, 2006 Page 685 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) Table 15.7 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)* Operating Frequency P (MHz) Bit Rate (bit/s) 110 250 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M 2.5M 5M 3 2 2 1 1 0 0 0 0 0 0 0 124 -- 249 -- 124 -- 199 1 99 79 39 19 7 3 1 0 0* 1 2 8 n N n 10 N -- -- -- n 3 3 2 16 N 249 124 -- 249 -- 99 99 79 39 15 7 3 2 1 0 0 0 0 0 0 0 199 1 159 0 n 20 N n 25 N n 30 N n 33 N n 35 N -- -- 3 97 77 124 2 249 2 124 1 199 0 99 49 19 9 4 1 0* 1 3 3 2 155 2 155 1 249 1 124 0 62 24 -- -- -- -- 0 0 0 -- 0 -- 233 116 3 187 2 93 74 74 29 14 -- 2 -- 2 1 0 0 -- -- -- -- 187 1 149 0 128 3 205 2 102 2 205 1 82 82 32 -- -- -- -- 1 0 0 -- -- -- -- 164 0 136 218 108 218 87 174 87 34 -- -- -- -- 249 2 124 1 249 1 99 49 24 9 4 0 0 0 0 0 0 1 0 0 0 0 0 199 0 0 0 0 -- -- -- -- [Legend] Space: Setting prohibited. : Can be set, but there will be error. Notes: 1. Continuous transmission or reception is not possible. 2. No clocked synchronous mode exists in SCI_5 and SCI_6. Table 15.8 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)* P (MHz) 8 10 12 14 16 18 Note * External Input Clock (MHz) 1.3333 1.6667 2.0000 2.3333 2.6667 3.0000 Maximum Bit Rate (bit/s) 1333333.3 1666666.7 2000000.0 2333333.3 2666666.7 3000000.0 P (MHz) 20 25 30 33 35 External Input Clock (MHz) 3.3333 4.1667 5.0000 5.5000 5.8336 Maximum Bit Rate (bit/s) 3333333.3 4166666.7 5000000.0 5500000.0 5833625.0 No clocked synchronous mode exists in SCI_5 and SCI_6. Rev.1.00 Jun. 07, 2006 Page 686 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) Table 15.9 BRR Settings for Various Bit Rates (Smart Card Interface Mode, n = 0, S = 372) Operating Frequency P (MHz) 7.1424 Bit Rate (bit/sec) 9600 0 0 0.00 0 1 30 0 1 n N Error (%) n N 10.00 Error (%) n 10.7136 N Error (%) 25 n 0 N 1 13.00 Error (%) 8.99 Operating Frequency P (MHz) 14.2848 Bit Rate (bit/sec) 9600 0 1 0.00 0 1 12.01 0 2 n N Error (%) n N 16.00 Error (%) n 18.00 N Error (%) 15.99 n 0 N 2 20.00 Error (%) 6.60 Operating Frequency P (MHz) 25.00 Bit Rate (bit/sec) 9600 0 3 12.49 0 3 5.01 0 4 n N Error (%) n N 30.00 Error (%) n 33.00 N Error (%) 7.59 n 0 N 4 35.00 Error (%) 1.99 Table 15.10 Maximum Bit Rate for Each Operating Frequency (Smart Card Interface Mode, S = 372) P (MHz) 7.1424 10.00 10.7136 13.00 14.2848 16.00 Maximum Bit Rate (bit/s) 9600 13441 14400 17473 19200 21505 n 0 0 0 0 0 0 N 0 0 0 0 0 0 P (MHz) 18.00 20.00 25.00 30.00 33.00 35.00 Maximum Bit Rate (bit/s) 24194 26882 33602 40323 44355 47043 n 0 0 0 0 0 0 N 0 0 0 0 0 0 Rev.1.00 Jun. 07, 2006 Page 687 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) 15.3.10 Serial Extended Mode Register (SEMR_2) SEMR_2 selects the clock source in asynchronous mode of SCI_2. The base clock is automatically specified when the average transfer rate operation is selected. Bit Bit Name Initial Value R/W 7 Undefined R 6 Undefined R 5 Undefined R 4 Undefined R 3 ABCS 0 R/W 2 ACS2 0 R/W 1 ACS1 0 R/W 0 ACS0 0 R/W Bit 7 to 4 Bit Name Initial Value R/W Description Reserved These bits are always read as undefined and cannot be modified. Undefined R 3 ABCS 0 R/W Asynchronous Mode Base clock Select (valid only in asynchronous mode) Selects the base clock for a 1-bit period. 0: The base clock has a frequency 16 times the transfer rate 1: The base clock has a frequency 8 times the transfer rate Rev.1.00 Jun. 07, 2006 Page 688 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) Bit 2 1 0 Bit Name ACS2 ACS1 ACS0 Initial Value 0 0 0 R/W R/W R/W R/W Description Asynchronous Mode Clock Source Select (valid when CKE1 = 1 in asynchronous mode) These bits select the clock source for the average transfer rate function. When the average transfer rate function is enabled, the base clock is automatically specified regardless of the ABCS bit value. 000: External clock input 001: 115.192 kbps of average transfer rate specific to P = 10.667 MHz is selected (operated using the base clock with a frequency 16 times the transfer rate) 010: 460.784 kbps of average transfer rate specific to P = 10.667 MHz is selected (operated using the base clock with a frequency 8 times the transfer rate) 011: 720 kbps of average transfer rate specific to P = 32 MHz is selected (operated using the base clock with a frequency 16 times the transfer rate) 100: Setting prohibited 101: 115.192 kbps of average transfer rate specific to P = 16 MHz is selected (operated using the base clock with a frequency 16 times the transfer rate) 110: 460.784 kbps of average transfer rate specific to P = 16 MHz is selected (operated using the base clock with a frequency 16 times the transfer rate) 111: 720 kbps of average transfer rate specific to P = 16 MHz is selected (operated using the base clock with a frequency 8 times the transfer rate) The average transfer rate only supports operating frequencies of 10.667 MHz, 16 MHz, and 32 MHz. Rev.1.00 Jun. 07, 2006 Page 689 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) 15.3.11 Serial Extended Mode Register 5 and 6 (SEMR_5 and SEMR_6) SEMR_5 and SEMR_6 select the clock source in asynchronous mode of SCI_5 and SCI_6. The base clock is automatically specified when the average transfer rate operation is selected. TMQ output in TMR unit 2 and unit 3 can also be set as the serial transfer base clock. Figure 15.3 describes the examples of base clock features when the average transfer rate operation is selected. Figure 15.4 describes the examples of base clock features when the TMO output in TMR is selected. Bit Bit Name Initial Value R/W 7 Undefined R 6 Undefined R 5 Undefined R 4 ABCS 0 R/W 3 ACS3 0 R/W 2 ACS2 0 R/W 1 ACS1 0 R/W 0 ACS0 0 R/W Bit 7 to 5 Bit Name Initial Value R/W Description Reserved These bits are always read as undefined and cannot be modified. Asynchronous Mode Base Clock Select (valid only in asynchronous mode) Selects the base clock for a 1-bit period. 0: The base clock has a frequency 16 times the transfer rate 1: The base clock has a frequency 8 times the transfer rate Asynchronous Mode Clock Source Select These bits select the clock source for the average transfer rate function in the asynchronous mode. When the average transfer rate function is enabled, the base clock is automatically specified regardless of the ABCS bit value. The average transfer rate only corresponds to 8MHz, 10.667MHz, 12MHz, 16MHz, 24MHz, and 32MHz. No other clock is available. Setting of ACS3 to ACS0 must be done in the asynchronous mode (the C/A bit in SMR = 0) and the external clock input mode (the CKE bit I SCR = 1). The setting examples are in figures 15.3 and 15.4. (Each number in the four-digit number below corresponds to the value in the bits ACS3 to ACS0 from left to right respectively.) Undefined R 4 ABCS 0 R/W 3 2 1 0 ACS3 ACS2 ACS1 ACS0 0 0 0 0 R/W R/W R/W R/W Rev.1.00 Jun. 07, 2006 Page 690 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) Bit 3 2 1 0 Bit Name ACS3 ACS2 ACS1 ACS0 Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description 0000: Average transfer rate generator is not used. 0001: 115.152 kbps of average transfer rate specific to P = 10.667 MHz is selected (operated using the base clock with a frequency 16 times the transfer rate) 0010: 460.606 kbps of average transfer rate specific to P = 10.667 MHz is selected (operated using the base clock with a frequency 8 times the transfer rate) 0011: 921.569 kbps of average transfer rate specific to P = 16 MHz is selected or 460.784 kbps of average transfer rate specific to P = 8MHz is selected (operated using the base clock with a frequency 8 times the transfer rate) 0100: TMR clock input This setting allows the TMR compare match output to be used as the base clock. The table below shows the correspondence between the SCI channels and the compare match output. Compare Match TMR Unit Output Unit 2 TMO4, TMO5 Unit 3 TMO6, TMO7 SCI Channel SCI_5 SCI_6 0101: 115.196 kbps of average transfer rate specific to P = 16 MHz is selected (operated using the base clock with a frequency 16 times the transfer rate) 0110: 460.784 kbps of average transfer rate specific to P = 16 MHz is selected (operated using the base clock with a frequency 16 times the transfer rate) 0111: 720 kbps of average transfer rate specific to P = 16 MHz is selected (operated using the base clock with a frequency 8 times the transfer rate) Rev.1.00 Jun. 07, 2006 Page 691 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) Bit 3 2 1 0 Bit Name ACS3 ACS2 ACS1 ACS0 Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description 1000: 115.132 kbps of average transfer rate specific to P = 24 MHz is selected (operated using the base clock with a frequency 16 times the transfer rate) 1001: 460.526 kbps of average transfer rate specific to P = 24 or MHz or 230.263 kbps of average transfer rate specific to P = 12MHz is selected (operated using the base clock with a frequency 16 times the transfer rate) 1010: 720 kbps of average transfer rate specific to P = 24 MHz is selected (operated using the base clock with a frequency 8 times the transfer rate) 1011: 921.053 kbps of average transfer rate specific to P = 24 or MHz or 460.526 kbps of average transfer rate specific to P = 12MHz is selected (operated using the base clock with a frequency 8 times the transfer rate) 1100: 720 kbps of average transfer rate specific to P = 32 MHz is selected (operated using the base clock with a frequency 16 times the transfer rate) 1101: Reserved (setting prohibited) 111x: Reserved (setting prohibited) Rev.1.00 Jun. 07, 2006 Page 692 of 1102 REJ09B0294-0100 When = 10.667 MHz Base clock with 115.152-kbps average transfer rate (ACS3 to 0 = B'0001) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 1 2 3 4 2.667 MHz 1.8424 MHz 45 67 89 10 11 12 13 14 15 16 Base clock 10.667 MHz/4= 2.667 MHz 2.667 MHz x (38/55) = 1.8424 MHz (Average) 1 bit = Base clock x 16* 123 Average transfer rate = 1.8424 MHz/16 = 115.152 kbps Average error with 115.2 kbps = -0.043% Base clock with 460.606-kbps average transfer rate (ACS3 to 0 = B'0010) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 1 2 3 4 5.333 MHz 3.6848 MHz 45 67 8 Base clock 10.667 MHz/2 = 5.333 MHz 5.333 MHz x (38/55) = 3.6848 MHz (Average) 1 bit = Base clock x 8* 123 Average transfer rate = 3.6848 MHz/8 = 460.606 kbps Average error with 460.6 kbps = -0.043% Figure 15.3 Examples of Base Clock when Average Transfer Rate Is Selected (1) Section 15 Serial Communication Interface (SCI, IrDA, CRC) Note: * The length of one bit varies according to the base clock synchronization. Rev.1.00 Jun. 07, 2006 Page 693 of 1102 REJ09B0294-0100 When = 16 MHz Base clock with 115.196-kbps average transfer rate (ACS3 to 0 = B'0101) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 1 2 3 4 5 6 7 8 2 MHz 1.8431 MHz 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 bit = Base clock x 16* Average transfer rate = 1.8431 MHz/16 = 115.196 kbps Average error with 115.2 kbps = -0.004% REJ09B0294-0100 Average transfer rate = 7.3725 MHz/16 = 460.784 kbps Average error with 460.8 kbps = -0.004% 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 8 MHz 5.76 MHz 123 45 678 1 bit = Base clock x 8* Average transfer rate = 5.76 MHz/8 = 720 kbps Average error with 720 kbps = 0% 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 1 2 3 4 5 6 7 8 8 MHz 7.3725 MHz 12345678 1 bit = Base clock x 8* Average transfer rate = 7.3725 MHz/8 = 921.569 kbps Average error with 921.6 kbps = -0.003% Rev.1.00 Jun. 07, 2006 Page 694 of 1102 Base clock 16 MHz/8 = 2 MHz 2 MHz x (47/51) = 1.8431 MHz (Average) Base clock with 460.784-kbps average transfer rate (ACS3 to 0 = B'0110) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 1 2 3 4 5 6 7 8 Base clock 8 MHz 16 MHz/2 = 8 MHz 8 MHz x (47/51) 7.3725 MHz 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 = 7.3725 MHz (Average) 1 bit = Base clock x 16* Section 15 Serial Communication Interface (SCI, IrDA, CRC) Base clock with 720-kbps average transfer rate (ACS3 to 0 = B'0111) Base clock 16 MHz/2 = 8 MHz 8 MHz x (18/25) = 5.76 MHz (Average) Base clock with 921.569-kbps average transfer rate (ACS3 to 0 = B'0011) Base clock 16 MHz/2 = 8 MHz 8 MHz x (47/51) = 7.3725 MHz (Average) Figure 15.3 Examples of Base Clock when Average Transfer Rate Is Selected (2) Note: * The length of one bit varies according to the base clock synchronization. When = 24 MHz 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 1 2 3 MHz 1 67 89 10 11 12 13 14 15 16 1 bit = Base clock x 16* Average transfer rate =1.8421 MHz/16 = 115.132 kbps Average error with 115.2 kbps = -0.059% 1.8421 MHz 23 45 Base clock with 115.132-kbps average transfer rate (ACS3 to 0 = B'1000) Base clock 24 MHz/8 = 3 MHz 3 MHz x (35/57) = 1.8421 MHz (average) Base clock with 460.526-kbps average transfer rate (ACS3 to 0 = B'1001) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 1 2 12 MHz 1 67 89 10 11 12 13 14 15 16 1 bit = Base clock x 16* Average transfer rate = 7.3684 MHz/16 = 460.526 kbps Average error with 921.6 kbps = -0.059% 7.3684 MHz 23 45 Base clock 24 MHz/2 = 12 MHz 12 MHz x (35/57) = 7.3684 MHz (Average) Base clock with 720-kbps average transfer rate (ACS3 to 0 = B'1010) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 12 MHz 5.76 MHz 1 bit = Base clock x 8* Average transfer rate = 5.76 MHz/8= 720 kbps Average error with 720 kbps = 0% Base clock 24 MHz/2 = 12 MHz 12 MHz x (12/25) = 5.76 MHz (Average) Base clock with 921.053-kbps average transfer rate (ACS3 to 0 = B'1011) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 1 2 12 MHz 1 8 7.3684 MHz 23 45 67 1 bit = Base clock x 8* Base clock 24 MHz/2 = 12 MHz 12 MHz x (35/57) = 7.3684 MHz (Average) Average transfer rate = 7.3684 MHz/8= 921.053 kbps Average error with 921.6 kbps = -0.059% Figure 15.3 Examples of Base Clock when Average Transfer Rate Is Selected (3) Section 15 Serial Communication Interface (SCI, IrDA, CRC) Rev.1.00 Jun. 07, 2006 Page 695 of 1102 REJ09B0294-0100 Note: * The length of one bit varies according to the base clock synchronization. REJ09B0294-0100 SCI_5 Clock enable Base clock SCK5 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 4 MHz 3 MHz 1 1 bit = Base clock x 16 Average transfer rate = 3 MHz/16 = 187.5 kbps 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 Rev.1.00 Jun. 07, 2006 Page 696 of 1102 Example when TMR clock input is used in SCI_5 187.5-kbps average transfer rate is generated by TMR when = 32 MHz (1) TMO4 is set as a base clock and generates 4 MHz. (2) TMO5 is set as TCNT_4 compare match count and generates a clock enable multiplied by 3/4. The average transfer rate will be 3 MHz/16 = 187.5 kbps. Section 15 Serial Communication Interface (SCI, IrDA, CRC) TMR and SCI Settings: TMR (Unit 2) * TCR_4 = H'09 (TCNT4 cleared by TCORA_4 compare match, TCNT4 incremented at rising edge of P/2) * TCCR_4 = H'01 TMO5 * TCR_5 = H'0C (TCNT5 cleared by TCORA_5 compare match, TCNT5 incremented by TCNT_4 compare match A) TMO4 * TCCR_5 = H'00 * TCSR_4 = H'09 (0 output on TCORA_4 compare match, 1 output on TCORB_4 compare match) * TCSR_5 = H'09 (0 output on TCORA_5 compare match, 1 output on TCORB_5 compare match) * TCNT_4 = TCNT_5 = 0 * TCORA_4 = H'03, TCORB_4 = H'01 * TCORA_5 = H'03, TCORB_5 = H'00 * SEMR_5 = H'04 When SCI_6 is used, set TMO6 as a base clock and TMO7 as a clock enable. Base clock TMO4 output = 4 MHz Clock enable TMO5 output Figure 15.4 Example of Average Transfer Rate Setting when TMR Clock Is Input SCK5 Base clock = 4 MHz 3/4 = 3 MHz (Average) Section 15 Serial Communication Interface (SCI, IrDA, CRC) 15.3.12 IrDA Control Register (IrCR) IrCR selects the function of SCI_5. Bit Bit Name Initial Value R/W 7 IrE 0 R/W 6 IrCKS2 0 R/W 5 IrCKS1 0 R/W 4 IrCKS0 0 R/W 3 IrTxINV 0 R/W 2 IrRxINV 0 R/W 1 0 0 0 Bit 7 Bit Name IrE Initial Value 0 R/W R/W Description IrDA Enable Sets the SCI_5 I/O to normal SCI or IrDA. 0: TxD5/IrTxD and RxD5/IrRxD pins operate as TxD5 and RxD5. 1: TxD5/IrTxD and RxD5/IrRxD pins are operate as IrTxD and IrRxD. 6 5 4 IrCK2 IrCK1 IrCK0 0 0 0 R/W R/W R/W IrDA Clock Select 2 to 0 Sets the pulse width of high state at encoding the IrTxD output pulse when the IrDA function is enabled. 000: Pulse-width = B x 3/16 (Bit rate x 3/16) 001: Pulse-width = P/2 010: Pulse-width = P/4 011: Pulse-width = P/8 100: Pulse-width = P/16 101: Pulse-width = P/32 110: Pulse-width = P/64 111: Pulse-width = P/128 3 IrTxINV 0 R/W IrTx Data Invert This bit specifies the inversion of the logic level in IrTxD output. When inversion is done, the pulse width of high state specified by the bits 6 to 4 becomes the pulse width in low state. 0: Outputs the transmission data as it is as IrTxD output 1: Outputs the inverted transmission data as IrTxD output Rev.1.00 Jun. 07, 2006 Page 697 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) Bit 2 Bit Name IrRxINV Initial Value 0 R/W R/W Description IrRx Data Invert This bit specifies the inversion of the logic level in IrRxD output. When inversion is done, the pulse width of high state specified by the bits 6 to 4 becomes the pulse width in low state. 0: Uses the IrRxD input data as it is as receive data. 1: Uses the inverted IrRxD input data as receive data. 1, 0 All 0 -- Reserved These bits are always read as 0. It should not be set to 0. 15.4 Operation in Asynchronous Mode Figure 15.5 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), transmit/receive data, a parity bit, and stop bits (high level). In asynchronous serial communication, the communication line is usually held in the mark state (high level). The SCI monitors the communication line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transmission and reception. Idle state (mark state) 1 0/1 Parity bit 1 bit, or none 1 1 1 Serial data 0 Start bit 1 bit LSB D0 D1 D2 D3 D4 D5 D6 MSB D7 Stop bit Transmit/receive data 7 or 8 bits 1 or 2 bits One unit of transfer data (character or frame) Figure 15.5 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) Rev.1.00 Jun. 07, 2006 Page 698 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) 15.4.1 Data Transfer Format Table 15.11 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. For details on the multiprocessor bit, see section 15.5, Multiprocessor Communication Function. Table 15.11 Serial Transfer Formats (Asynchronous Mode) SMR Settings CHR 0 0 0 0 1 1 1 1 0 0 1 1 PE 0 0 1 1 0 0 1 1 - - - - MP 0 0 0 0 0 0 0 0 1 1 1 1 STOP 0 1 0 1 0 1 0 1 0 1 0 1 1 S 2 Serial Transfer Format and Frame Length 3 4 5 6 7 8 9 10 11 8-bit data STOP 12 S 8-bit data STOP STOP S 8-bit data P STOP S 8-bit data P STOP STOP S 7-bit data STOP S 7-bit data STOP STOP S 7-bit data P STOP S 7-bit data P STOP STOP S 8-bit data MPB STOP S 8-bit data MPB STOP STOP S 7-bit data MPB STOP S 7-bit data MPB STOP STOP [Legend] S: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit Rev.1.00 Jun. 07, 2006 Page 699 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) 15.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a base clock with a frequency of 16 times* the bit rate. In reception, the SCI samples the falling edge of the start bit using the base clock, and performs internal synchronization. Since receive data is sampled at the rising edge of the 8th pulse* of the base clock, data is latched at the middle of each bit, as shown in figure 15.6. Thus the reception margin in asynchronous mode is determined by formula (1) below. M = | (0.5 - 1 ) - (L - 0.5) F - | D - 0.5 | (1 + F ) | x 100 2N N [%] ... Formula (1) [Legend] M: Reception margin N: Ratio of bit rate to clock (When ABCS = 0, N = 16. When ABCS = 1, N = 8.) D: Duty cycle of clock (D = 0.5 to 1.0) L: Frame length (L = 9 to 12) F: Absolute value of clock frequency deviation Assuming values of F = 0 and D = 0.5 in formula (1), the reception margin is determined by the formula below. M = ( 0.5 - 1 ) x 100 2 x 16 [%] = 46.875% However, this is only the computed value, and a margin of 20% to 30% should be allowed in system design. 16 clocks 8 clocks 0 Internal basic clock Receive data (RxD) Synchronization sampling timing Data sampling timing 7 15 0 7 15 0 Start bit D0 D1 Figure 15.6 Receive Data Sampling Timing in Asynchronous Mode Note: * This is an example when the ABCS bit in SEMR_2, 5, and 6 is 0. When the ABCS bit is 1, a frequency of 8 times the bit rate is used as a base clock and receive data is sampled at the rising edge of the 4th pulse of the base clock. Rev.1.00 Jun. 07, 2006 Page 700 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) 15.4.3 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input to the SCK pin can be selected as the SCI's transfer clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. When an external clock is input to the SCK pin, the clock frequency should be 16 times the bit rate (when ABCS = 0) and 8 times the bit rate (when ABCS = 1). In addition, when an external clock is specified, the average transfer rate or the base clock of TMR_4 to TMR_7 can be selected by the ACS3 to ACS0 bits in SEMR_5 and SEMR_6. When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 15.7. SCK TxD 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 frame Figure 15.7 Phase Relation between Output Clock and Transmit Data (Asynchronous Mode) Rev.1.00 Jun. 07, 2006 Page 701 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) 15.4.4 SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 15.8 When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the RDRF, PER, FER, and ORER flags, or RDR. When the external clock is used in asynchronous mode, the clock must be supplied even during initialization. Start initialization [1] Clear TE and RE bits in SCR to 0 Set corresponding bit in ICR to 1 [1] [2] Set the bit in ICR for the corresponding pin when receiving data or using an external clock. Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. When the clock output is selected in asynchronous mode, the clock is output immediately after SCR settings are made. [3] [4] Set the data transfer format in SMR and SCMR. Write a value corresponding to the bit rate to BRR. This step is not necessary if an external clock is used. Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. Set CKE1 and CKE0 bits in SCR (TE and RE bits are 0) [2] Set data transfer format in SMR and SCMR Set value in BRR Wait [3] [4] [5] No 1-bit interval elapsed Yes Set TE or RE bit in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits [5] Figure 15.8 Sample SCI Initialization Flowchart Rev.1.00 Jun. 07, 2006 Page 702 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) 15.4.5 Serial Data Transmission (Asynchronous Mode) Figure 15.9 shows an example of the operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is cleared to 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a TXI interrupt request is generated. Because the TXI interrupt processing routine writes the next transmit data to TDR before transmission of the current transmit data has finished, continuous transmission can be enabled. 3. Data is sent from the TxD pin in the following order: start bit, transmit data, parity bit or multiprocessor bit (may be omitted depending on the format), and stop bit. 4. The SCI checks the TDRE flag at the timing for sending the stop bit. 5. If the TDRE flag is 0, the next transmit data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. 6. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the mark state is entered in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. Figure 15.10 shows a sample flowchart for transmission in asynchronous mode. Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1 1 1 Idle state (mark state) TDRE TEND TXI interrupt Data written to TDR and request generated TDRE flag cleared to 0 in TXI interrupt processing routine 1 frame TXI interrupt request generated TEI interrupt request generated Figure 15.9 Example of Operation for Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) Rev.1.00 Jun. 07, 2006 Page 703 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) Initialization Start transmission [1] Read TDRE flag in SSR No [2] [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a 1 is output for a frame, and transmission is enabled. [2] SCI state check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and clear the TDRE flag to 0. However, the TDRE flag is checked and cleared automatically when the DMAC or DTC is initiated by a transmit data empty interrupt (TXI) request and writes data to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set DDR for the port corresponding to the TxD pin to 1, clear DR to 0, then clear the TE bit in SCR to 0. TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 All data transmitted? Yes No [3] Read TEND flag in SSR No TEND = 1 Yes Break output Yes Clear DR to 0 and set DDR to 1 No [4] Clear TE bit in SCR to 0 Figure 15.10 Example of Serial Transmission Flowchart Rev.1.00 Jun. 07, 2006 Page 704 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) 15.4.6 Serial Data Reception (Asynchronous Mode) Figure 15.11 shows an example of the operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line, and if a start bit is detected, performs internal synchronization, stores receive data in RSR, and checks the parity bit and stop bit. 2. If an overrun error (when reception of the next data is completed while the RDRF flag in SSR is still set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag remains to be set to 1. 3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 4. If a framing error (when the stop bit is 0) is detected, the FER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 5. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Because the RXI interrupt processing routine reads the receive data transferred to RDR before reception of the next receive data has finished, continuous reception can be enabled. Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 0 1 1 Idle state (mark state) RDRF FER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt processing routine ERI interrupt request generated by framing error 1 frame Figure 15.11 Example of SCI Operation for Reception (Example with 8-Bit Data, Parity, One Stop Bit) Rev.1.00 Jun. 07, 2006 Page 705 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) Table 15.12 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 15.12 shows a sample flowchart for serial data reception. Table 15.12 SSR Status Flags and Receive Data Handling SSR Status Flag RDRF* 1 0 0 1 1 0 1 Note: * ORER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 Receive Data Lost Transferred to RDR Transferred to RDR Lost Lost Transferred to RDR Lost Receive Error Type Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error The RDRF flag retains the state it had before data reception. Rev.1.00 Jun. 07, 2006 Page 706 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) Initialization Start reception [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error processing and break detection: [2] If a receive error occurs, read the ORER, PER, and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure Yes PER FER ORER = 1 that the ORER, PER, and FER flags are [3] all cleared to 0. Reception cannot be No resumed if any of these flags are set to Error processing 1. In the case of a framing error, a (Continued on next page) break can be detected by reading the value of the input port corresponding to [4] Read RDRF flag in SSR the RxD pin. Read ORER, PER, and FER flags in SSR No [4] SCI state check and receive data read: Read SSR and check that RDRF = 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the stop bit for the current frame is received, read the RDRF flag and RDR, and clear the RDRF flag to 0. However, the RDRF flag is cleared automatically when the DMAC or DTC is initiated by an RXI interrupt and reads data from RDR. RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit in SCR to 0 [5] Figure 15.12 Sample Serial Reception Flowchart (1) Rev.1.00 Jun. 07, 2006 Page 707 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) [3] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Break? No Framing error processing Clear RE bit in SCR to 0 Yes No PER = 1 Yes Parity error processing Clear ORER, PER, and FER flags in SSR to 0 Figure 15.12 Sample Serial Reception Flowchart (2) Rev.1.00 Jun. 07, 2006 Page 708 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) 15.5 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles: an ID transmission cycle which specifies the receiving station, and a data transmission cycle for the specified receiving station. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. If the multiprocessor bit is 1, the cycle is an ID transmission cycle, and if the multiprocessor bit is 0, the cycle is a data transmission cycle. Figure 15.13 shows an example of inter-processor communication using the multiprocessor format. The transmitting station first sends data which includes the ID code of the receiving station and a multiprocessor bit set to 1. It then transmits transmit data added with a multiprocessor bit cleared to 0. The receiving station skips data until data with a 1 multiprocessor bit is sent. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip data until data with a 1 multiprocessor bit is again received. The SCI uses the MPIE bit in SCR to implement this function. When the MPIE bit is set to 1, transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags, RDRF, FER, and ORER in SSR to 1 are prohibited until data with a 1 multiprocessor bit is received. On reception of a receive character with a 1 multiprocessor bit, the MPB bit in SSR is set to 1 and the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt is generated. When the multiprocessor format is selected, the parity bit setting is invalid. All other bit settings are the same as those in normal asynchronous mode. The clock used for multiprocessor communication is the same as that in normal asynchronous mode. Rev.1.00 Jun. 07, 2006 Page 709 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) Transmitting station Communication line Receiving station A (ID = 01) Serial data Receiving station B (ID = 02) Receiving station C (ID = 03) Receiving station D (ID = 04) H'01 (MPB = 1) H'AA (MPB = 0) ID transmission cycle = Data transmission cycle = receiving station Data transmission to specification receiving station specified by ID [Legend] MPB: Multiprocessor bit Figure 15.13 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) Rev.1.00 Jun. 07, 2006 Page 710 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) 15.5.1 Multiprocessor Serial Data Transmission Figure 15.14 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same as those in asynchronous mode. Initialization Start transmission Read TDRE flag in SSR No [1] [2] [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a 1 is output for one frame, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. Set the MPBT bit in SSR to 0 or 1. Finally, clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. However, the TDRE flag is checked and cleared automatically when the DMAC or DTC is initiated by a transmit data empty interrupt (TXI) request and writes data to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set DDR for the port to 1, clear DR to 0, and then clear the TE bit in SCR to 0. TDRE = 1 Yes Write transmit data to TDR and set MPBT bit in SSR Clear TDRE flag to 0 All data transmitted? Yes Read TEND flag in SSR No [3] TEND = 1 Yes Break output? Yes Clear DR to 0 and set DDR to 1 No No [4] Clear TE bit in SCR to 0 Figure 15.14 Sample Multiprocessor Serial Transmission Flowchart Rev.1.00 Jun. 07, 2006 Page 711 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) 15.5.2 Multiprocessor Serial Data Reception Figure 15.16 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI operations are the same as in asynchronous mode. Figure 15.15 shows an example of SCI operation for multiprocessor format reception. Start bit 0 D0 D1 Data (ID1) MPB D7 1 Stop bit 1 Start bit 0 D0 Data (Data 1) D1 D7 Stop MPB bit 0 1 1 1 Idle state (mark state) MPIE RDRF RDR value MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt processing routine ID1 If not this station's ID, MPIE bit is set to 1 again RXI interrupt request is not generated, and RDR retains its state (a) Data does not match station's ID 1 Start bit 0 D0 D1 Data (ID2) D7 Stop MPB bit 1 1 Start bit 0 D0 Data (Data 2) D1 D7 Stop MPB bit 0 1 1 Idle state (mark state) MPIE RDRF RDR value ID1 MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt processing routine ID2 Matches this station's ID, so reception continues, and data is received in RXI interrupt processing routine Data 2 MPIE bit set to 1 again (b) Data matches station's ID Figure 15.15 Example of SCI Operation for Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) Rev.1.00 Jun. 07, 2006 Page 712 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) Initialization Start reception Set MPIE bit in SCR to 1 Read ORER and FER flags in SSR FER ORER = 1 No Read RDRF flag in SSR No [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] ID reception cycle: Set the MPIE bit in SCR to 1. [3] SCI state check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station's ID. If the data is not this station's ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station's ID, clear the RDRF flag to 0. [4] SCI state check and data reception: Read SSR and check that the RDRF flag is set to 1, then read the data in RDR. [5] Receive error processing and break detection: If a receive error occurs, read the ORER and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the ORER and FER flags are both cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RxD pin value. [4] [2] Yes [3] RDRF = 1 Yes Read receive data in RDR No This station's ID? Yes Read ORER and FER flags in SSR FER ORER = 1 No Read RDRF flag in SSR No Yes RDRF = 1 Yes Read receive data in RDR No All data received? Yes Clear RE bit in SCR to 0 [5] Error processing (Continued on next page) Figure 15.16 Sample Multiprocessor Serial Reception Flowchart (1) Rev.1.00 Jun. 07, 2006 Page 713 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) [5] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Break? No Framing error processing Clear RE bit in SCR to 0 Yes Clear ORER, PER, and FER flags in SSR to 0 Figure 15.16 Sample Multiprocessor Serial Reception Flowchart (2) Rev.1.00 Jun. 07, 2006 Page 714 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) 15.6 Operation in Clocked Synchronous Mode (SCI_0, 1, 2, and 4 only) Figure 15.17 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses. One character in transfer data consists of 8-bit data. In data transmission, the SCI outputs data from one falling edge of the synchronization clock to the next. In data reception, the SCI receives data in synchronization with the rising edge of the synchronization clock. After 8-bit data is output, the transmission line holds the MSB output state. In clocked synchronous mode, no parity bit or multiprocessor bit is added. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so that the next transmit data can be written during transmission or the previous receive data can be read during reception, enabling continuous data transfer. One unit of transfer data (character or frame) * Synchronization clock LSB Serial data Don't care Note: * Holds a high level except during continuous transfer. Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 Don't care * Figure 15.17 Data Format in Clocked Synchronous Communication (LSB-First) 15.6.1 Clock Either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the SCK pin can be selected, according to the setting of the CKE1 and CKE0 bits in SCR. When the SCI is operated on an internal clock, the synchronization clock is output from the SCK pin. Eight synchronization clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. Note that in the case of reception only, the synchronization clock is output until an overrun error occurs or until the RE bit is cleared to 0. (Setting is prohibited in SCI_5 and SCI_6.) Rev.1.00 Jun. 07, 2006 Page 715 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) 15.6.2 SCI Initialization (Clocked Synchronous Mode) (SCI_0, 1, 2, and 4 only) Before transmitting and receiving data, first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 15.18. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change. When the TE bit is cleared to 0, the TDRE flag is set to 1. However, clearing the RE bit to 0 does not initialize the RDRF, PER, FER, and ORER flags, or RDR. Start initialization [1] Clear TE and RE bits in SCR to 0 Set corresponding bit in ICR to 1 [1] Set the bit in ICR for the corresponding pin when receiving data or using an external clock. Set CKE1 and CKE0 bits in SCR (TE and RE bits are 0) [2] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. [3] Set the data transfer format in SMR and SCMR. [4] Write a value corresponding to the bit rate to BRR. This step is not necessary if an external clock is used. [5] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. [2] Set data transfer format in SMR and SCMR Set value in BRR Wait [3] [4] 1-bit interval elapsed? Yes No Set TE or RE bit in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits [5] Figure 15.18 Sample SCI Initialization Flowchart Rev.1.00 Jun. 07, 2006 Page 716 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) 15.6.3 Serial Data Transmission (Clocked Synchronous Mode) (SCI_0, 1, 2, and 4 only) Figure 15.19 shows an example of the operation for transmission in clocked synchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a TXI interrupt request is generated. Because the TXI interrupt processing routine writes the next transmit data to TDR before transmission of the current transmit data has finished, continuous transmission can be enabled. 3. 8-bit data is sent from the TxD pin synchronized with the output clock when clock output mode has been specified and synchronized with the input clock when use of an external clock has been specified. 4. The SCI checks the TDRE flag at the timing for sending the last bit. 5. If the TDRE flag is cleared to 0, the next transmit data is transferred from TDR to TSR, and serial transmission of the next frame is started. 6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TxD pin retains the output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. The SCK pin is fixed high. Figure 15.20 shows a sample flowchart for serial data transmission. Even if the TDRE flag is cleared to 0, transmission will not start while a receive error flag (ORER, FER, or PER) is set to 1. Make sure to clear the receive error flags to 0 before starting transmission. Note that clearing the RE bit to 0 does not clear the receive error flags. Rev.1.00 Jun. 07, 2006 Page 717 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) Transfer direction Synchronization clock Serial data TDRE TEND TXI interrupt request generated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt processing routine 1 frame TXI interrupt request generated TEI interrupt request generated Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 Figure 15.19 Example of Operation for Transmission in Clocked Synchronous Mode [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. [2] SCI state check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. However, the TDRE flag is checked and cleared automatically when the DMAC or DTC is initiated by a transmit data empty interrupt (TXI) request and writes data to TDR. Initialization Start transmission [1] Read TDRE flag in SSR No [2] TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 All data transmitted Yes Read TEND flag in SSR No [3] TEND = 1 Yes Clear TE bit in SCR to 0 No Figure 15.20 Sample Serial Transmission Flowchart Rev.1.00 Jun. 07, 2006 Page 718 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) 15.6.4 Serial Data Reception (Clocked Synchronous Mode) (SCI_0, 1, 2, and 4 only) Figure 15.21 shows an example of SCI operation for reception in clocked synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with a synchronization clock input or output, starts receiving data, and stores the receive data in RSR. 2. If an overrun error (when reception of the next data is completed while the RDRF flag in SSR is still set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag remains to be set to 1. 3. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Because the RXI interrupt processing routine reads the receive data transferred to RDR before reception of the next receive data has finished, continuous reception can be enabled. Synchronization clock Serial data RDRF ORER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt processing routine 1 frame RXI interrupt request generated ERI interrupt request generated by overrun error Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 Figure 15.21 Example of Operation for Reception in Clocked Synchronous Mode Transfer cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 15.22 shows a sample flowchart for serial data reception. Rev.1.00 Jun. 07, 2006 Page 719 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) Initialization Start reception [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Reception cannot be resumed if the ORER flag is set to 1. Read ORER flag in SSR Yes [2] ORER = 1 No [3] Error processing No (Continued below) [4] SCI state check and receive data read: Read RDRF flag in SSR [4] Read SSR and check that the RDRF flag is set to 1, then read the receive RDRF = 1 data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from Yes 0 to 1 can also be identified by an RXI interrupt. Read receive data in RDR and clear RDRF flag in SSR to 0 [5] Serial reception continuation All data received Yes Clear RE bit in SCR to 0 No [3] Error processing Overrun error processing Clear ORER flag in SSR to 0 Figure 15.22 Sample Serial Reception Flowchart 15.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) (SCI_0, 1, 2, and 4 only) Figure 15.23 shows a sample flowchart for simultaneous serial transmit and receive operations. After initializing the SCI, the following procedure should be used for simultaneous serial data transmit and receive operations. To switch from transmit mode to simultaneous transmit and receive mode, after checking that the SCI has finished transmission and the TDRE and TEND flags are set to 1, clear the TE bit to 0. Then simultaneously set both the TE and RE bits to 1 with a single instruction. To switch from receive mode to simultaneous transmit and receive mode, after checking that the SCI has finished reception, clear the RE bit to 0. Then after checking that the RDRF bit and receive error flags (ORER, FER, and PER) are cleared to 0, simultaneously set both the TE and RE bits to 1 with a single instruction. Rev.1.00 Jun. 07, 2006 Page 720 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) Initialization Start transmission/reception [1] Read TDRE flag in SSR No [2] [1] SCI initialization: The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. [2] SCI state check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. [3] Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Reception cannot be resumed if the ORER flag is set to 1. [4] SCI state check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 Read ORER flag in SSR Yes [3] Error processing [4] ORER = 1 No Read RDRF flag in SSR No RDRF = 1 Yes [5] Serial transmission/reception continuation procedure: To continue serial transmission/ Read receive data in RDR, and reception, before the MSB (bit 7) of clear RDRF flag in SSR to 0 the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to No 0. Also, before the MSB (bit 7) of [5] All data received? the current frame is transmitted, read 1 from the TDRE flag to Yes confirm that writing is possible. Then write data to TDR and clear the TDRE flag to 0. Clear TE and RE bits in SCR to 0 However, the TDRE flag is checked and cleared automatically when the DMAC or DTC is initiated by a Figure 15.23 Sample Flowchart of Simultaneous Serial Transmission and Reception Rev.1.00 Jun. 07, 2006 Page 721 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) 15.7 Operation in Smart Card Interface Mode The SCI supports the smart card interface, supporting the ISO/IEC 7816-3 (Identification Card) standard, as an extended serial communication interface function. Smart card interface mode can be selected using the appropriate register. 15.7.1 Sample Connection Figure 15.24 shows a sample connection between the smart card and this LSI. As in the figure, since this LSI communicates with the smart card using a single transmission line, interconnect the TxD and RxD pins and pull up the data transmission line to VCC using a resistor. Setting the RE and TE bits to 1 with the smart card not connected enables closed transmission/reception allowing self diagnosis. To supply the smart card with the clock pulses generated by the SCI, input the SCK pin output to the CLK pin of the smart card. A reset signal can be supplied via the output port of this LSI. (In SCI_5 and SCI-6, the clock generated in SCI cannot be provided to smart cards.) VCC TxD RxD SCK Rx (port) This LSI Main unit of the device to be connected Data line Clock line Reset line I/O CLK RST Smart card Figure 15.24 Pin Connection for Smart Card Interface Rev.1.00 Jun. 07, 2006 Page 722 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) 15.7.2 Data Format (Except in Block Transfer Mode) Figure 15.25 shows the data transfer formats in smart card interface mode. * One frame contains 8-bit data and a parity bit in asynchronous mode. * During transmission, at least 2 etu (elementary time unit: time required for transferring one bit) is secured as a guard time after the end of the parity bit before the start of the next frame. * If a parity error is detected during reception, a low error signal is output for 1 etu after 10.5 etu has passed from the start bit. * If an error signal is sampled during transmission, the same data is automatically re-transmitted after at least 2 etu. In normal transmission/reception Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Output from the transmitting station When a parity error is generated Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Output from the transmitting station Output from the receiving station Start bit Data bits Parity bit Error signal [Legend] Ds: D0 to D7: Dp: DE: Figure 15.25 Data Formats in Normal Smart Card Interface Mode For communication with the smart cards of the direct convention and inverse convention types, follow the procedure below. (Z) A Ds Z D0 Z D1 A D2 Z D3 Z D4 Z D5 A D6 A D7 Z Dp (Z) state Figure 15.26 Direct Convention (SDIR = SINV = O/E = 0) Rev.1.00 Jun. 07, 2006 Page 723 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) For the direct convention type, logic levels 1 and 0 correspond to states Z and A, respectively, and data is transferred with LSB-first as the start character, as shown in figure 15.26. Therefore, data in the start character in the figure is H'3B. When using the direct convention type, write 0 to both the SDIR and SINV bits in SCMR. Write 0 to the O/E bit in SMR in order to use even parity, which is prescribed by the smart card standard. (Z) A Ds Z D7 Z D6 A D5 A D4 A D3 A D2 A D1 A D0 Z Dp (Z) state Figure 15.27 Inverse Convention (SDIR = SINV = O/E = 1) For the inverse convention type, logic levels 1 and 0 correspond to states A and Z, respectively and data is transferred with MSB-first as the start character, as shown in figure 15.27. Therefore, data in the start character in the figure is H'3F. When using the inverse convention type, write 1 to both the SDIR and SINV bits in SCMR. The parity bit is logic level 0 to produce even parity, which is prescribed by the smart card standard, and corresponds to state Z. Since the SNIV bit of this LSI only inverts data bits D7 to D0, write 1 to the O/E bit in SMR to invert the parity bit in both transmission and reception. 15.7.3 Block Transfer Mode Block transfer mode is different from normal smart card interface mode in the following respects. * Even if a parity error is detected during reception, no error signal is output. Since the PER bit in SSR is set by error detection, clear the PER bit before receiving the parity bit of the next frame. * During transmission, at least 1 etu is secured as a guard time after the end of the parity bit before the start of the next frame. * Since the same data is not re-transmitted during transmission, the TEND flag is set 11.5 etu after transmission start. * Although the ERS flag in block transfer mode displays the error signal status as in normal smart card interface mode, the flag is always read as 0 because no error signal is transferred. Rev.1.00 Jun. 07, 2006 Page 724 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) 15.7.4 Receive Data Sampling Timing and Reception Margin Only the internal clock generated by the on-chip baud rate generator can be used as a transfer clock in smart card interface mode. In this mode, the SCI can operate on a base clock with a frequency of 32, 64, 372, or 256 times the bit rate according to the BCP1 and BCP0 bit settings (the frequency is always 16 times the bit rate in normal asynchronous mode). At reception, the falling edge of the start bit is sampled using the base clock in order to perform internal synchronization. Receive data is sampled on the 16th, 32nd, 186th and 128th rising edges of the base clock so that it can be latched at the middle of each bit as shown in figure 15.28. The reception margin here is determined by the following formula. M = | (0.5 - [Legend] 1 ) - (L - 0.5) F - | D - 0.5 | (1 + F ) | x 100% 2N N M: Reception margin (%) N: Ratio of bit rate to clock (N = 32, 64, 372, 256) D: Duty cycle of clock (D = 0 to 1.0) L: Frame length (L = 10) F: Absolute value of clock frequency deviation Assuming values of F = 0, D = 0.5, and N = 372 in the above formula, the reception margin is determined by the formula below. M= ( 0.5 - 1 ) x 100% = 49.866% 2 x 372 372 clock cycles 186 clock cycles 0 Internal basic clock Receive data (RxD) Synchronization sampling timing 185 371 0 185 371 0 Start bit D0 D1 Data sampling timing Figure 15.28 Receive Data Sampling Timing in Smart Card Interface Mode (When Clock Frequency is 372 Times the Bit Rate) Rev.1.00 Jun. 07, 2006 Page 725 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) 15.7.5 Initialization Before transmitting and receiving data, initialize the SCI using the following procedure. Initialization is also necessary before switching from transmission to reception and vice versa. 1. Clear the TE and RE bits in SCR to 0. 2. Set the ICR bit of the corresponding pin to 1. 3. Clear the error flags ERS, PER, and ORER in SSR to 0. 4. Set the GM, BLK, O/E, BCP1, BCP0, CKS1, and CKS0 bits in SMR appropriately. Also set the PE bit to 1. 5. Set the SMIF, SDIR, and SINV bits in SCMR appropriately. When the DDR corresponding to the TxD pin is cleared to 0, the TxD and RxD pins are changed from port pins to SCI pins, placing the pins into high impedance state. 6. Set the value corresponding to the bit rate in BRR. 7. Set the CKE1 and CKE0 bits in SCR appropriately. Clear the TIE, RIE, TE, RE, MPIE, and TEIE bits to 0 simultaneously. When the CKE0 bit is set to 1, the SCK pin is allowed to output clock pulses. 8. Set the TIE, RIE, TE, and RE bits in SCR appropriately after waiting for at least a 1-bit interval. Setting the TE and RE bits to 1 simultaneously is prohibited except for self diagnosis. To switch from reception to transmission, first verify that reception has completed, then initialize the SCI. At the end of initialization, RE and TE should be set to 0 and 1, respectively. Reception completion can be verified by reading the RDRF, PER, or ORER flag. To switch from transmission to reception, first verify that transmission has completed, then initialize the SCI. At the end of initialization, TE and RE should be set to 0 and 1, respectively. Transmission completion can be verified by reading the TEND flag. Rev.1.00 Jun. 07, 2006 Page 726 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) 15.7.6 Data Transmission (Except in Block Transfer Mode) Data transmission in smart card interface mode (except in block transfer mode) is different from that in normal serial communication interface mode in that an error signal is sampled and data can be re-transmitted. Figure 15.29 shows the data re-transfer operation during transmission. 1. If an error signal from the receiving end is sampled after one frame of data has been transmitted, the ERS bit in SSR is set to 1. Here, an ERI interrupt request is generated if the RIE bit in SCR is set to 1. Clear the ERS bit to 0 before the next parity bit is sampled. 2. For the frame in which an error signal is received, the TEND bit in SSR is not set to 1. Data is re-transferred from TDR to TSR allowing automatic data retransmission. 3. If no error signal is returned from the receiving end, the ERS bit in SSR is not set to 1. 4. In this case, one frame of data is determined to have been transmitted including re-transfer, and the TEND bit in SSR is set to 1. Here, a TXI interrupt request is generated if the TIE bit in SCR is set to 1. Writing transmit data to TDR starts transmission of the next data. Figure 15.31 shows a sample flowchart for transmission. All the processing steps are automatically performed using a TXI interrupt request to activate the DTC or DMAC. In transmission, the TEND and TDRE flags in SSR are simultaneously set to 1, thus generating a TXI interrupt request if the TIE bit in SCR has been set to 1. This activates the DTC or DMAC by a TXI request thus allowing transfer of transmit data if the TXI interrupt request is specified as a source of DTC or DMAC activation beforehand. The TDRE and TEND flags are automatically cleared to 0 at data transfer by the DTC or DMAC. If an error occurs, the SCI automatically retransmits the same data. During re-transmission, TEND remains as 0, thus not activating the DTC or DMAC. Therefore, the SCI and DTC or DMAC automatically transmit the specified number of bytes, including re-transmission in the case of error occurrence. However, the ERS flag is not automatically cleared; the ERS flag must be cleared by previously setting the RIE bit to 1 to enable an ERI interrupt request to be generated at error occurrence. When transmitting/receiving data using the DTC or DMAC, be sure to set and enable the DTC or DMAC prior to making SCI settings. For DTC or DMAC settings, see section 8, Data Transfer Controller (DTC) and section 7, DMA Controller (DMAC). Rev.1.00 Jun. 07, 2006 Page 727 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Retransfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE) (n + 1) th transfer frame Ds D0 D1 D2 D3 D4 TDRE Transfer from TDR to TSR TEND [2] Transfer from TDR to TSR Transfer from TDR to TSR [4] FER/ERS [1] [3] Figure 15.29 Data Re-Transfer Operation in SCI Transmission Mode Note that the TEND flag is set in different timings depending on the GM bit setting in SMR. Figure 15.30 shows the TEND flag set timing. I/O data TXI (TEND interrupt) Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Guard time 12.5 etu GM = 0 11.0 etu GM = 1 [Legend] Ds: D0 to D7: Dp: DE: Start bit Data bits Parity bit Error signal Figure 15.30 TEND Flag Set Timing during Transmission Rev.1.00 Jun. 07, 2006 Page 728 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) Start Initialization Start transmission ERS = 0? Yes No Error processing No TEND = 1? Yes Write data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? Yes No ERS = 0? Yes Error processing No TEND = 1? Yes Clear TE bit in SCR to 0 End Figure 15.31 Sample Transmission Flowchart Rev.1.00 Jun. 07, 2006 Page 729 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) 15.7.7 Serial Data Reception (Except in Block Transfer Mode) Data reception in smart card interface mode is similar to that in normal serial communication interface mode. Figure 15.32 shows the data re-transfer operation during reception. 1. If a parity error is detected in receive data, the PER bit in SSR is set to 1. Here, an ERI interrupt request is generated if the RIE bit in SCR is set to 1. Clear the PER bit to 0 before the next parity bit is sampled. 2. For the frame in which a parity error is detected, the RDRF bit in SSR is not set to 1. 3. If no parity error is detected, the PER bit in SSR is not set to 1. 4. In this case, data is determined to have been received successfully, and the RDRF bit in SSR is set to 1. Here, an RXI interrupt request is generated if the RIE bit in SCR is set to 1. Figure 15.33 shows a sample flowchart for reception. All the processing steps are automatically performed using an RXI interrupt request to activate the DTC or DMAC. In reception, setting the RIE bit to 1 allows an RXI interrupt request to be generated when the RDRF flag is set to 1. This activates the DTC or DMAC by an RXI request thus allowing transfer of receive data if the RXI interrupt request is specified as a source of DTC or DMAC activation beforehand. The RDRF flag is automatically cleared to 0 at data transfer by the DTC or DMAC. If an error occurs during reception, i.e., either the ORER or PER flag is set to 1, a transmit/receive error interrupt (ERI) request is generated and the error flag must be cleared. If an error occurs, the DTC or DMAC is not activated and receive data is skipped, therefore, the number of bytes of receive data specified in the DTC or DMAC is transferred. Even if a parity error occurs and the PER bit is set to 1 in reception, receive data is transferred to RDR, thus allowing the data to be read. Note: For operations in block transfer mode, see section 15.4, Operation in Asynchronous Mode. (n + 1) th transfer frame (DE) Ds D0 D1 D2 D3 D4 nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE RDRF [2] PER [1] Retransfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp [4] [3] Figure 15.32 Data Re-Transfer Operation in SCI Reception Mode Rev.1.00 Jun. 07, 2006 Page 730 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) Start Initialization Start reception ORER = 0 and PER = 0? No Yes No Error processing RDRF = 1? Yes Read data from RDR and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit in SCR to 0 Figure 15.33 Sample Reception Flowchart 15.7.8 Clock Output Control Clock output can be fixed using the CKE1 and CKE0 bits in SCR when the GM bit in SMR is set to 1. Specifically, the minimum width of a clock pulse can be specified. Figure 15.34 shows an example of clock output fixing timing when the CKE0 bit is controlled with GM = 1 and CKE1 = 0. CKE0 SCK Given pulse width Given pulse width Figure 15.34 Clock Output Fixing Timing Rev.1.00 Jun. 07, 2006 Page 731 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) At power-on and transitions to/from software standby mode, use the following procedure to secure the appropriate clock duty cycle. * At power-on To secure the appropriate clock duty cycle simultaneously with power-on, use the following procedure. 1. Initially, port input is enabled in the high-impedance state. To fix the potential level, use a pull-up or pull-down resistor. 2. Fix the SCK pin to the specified output using the CKE1 bit in SCR. 3. Set SMR and SCMR to enable smart card interface mode. Set the CKE0 bit in SCR to 1 to start clock output. * At mode switching At transition from smart card interface mode to software standby mode 1. Set the data register (DR) and data direction register (DDR) corresponding to the SCK pin to the values for the output fixed state in software standby mode. (SCI_0, 1, 2, and 4 only) 2. Write 0 to the TE and RE bits in SCR to stop transmission/reception. Simultaneously, set the CKE1 bit to the value for the output fixed state in software standby mode. 3. Write 0 to the CKE0 bit in SCR to stop the clock. 4. Wait for one cycle of the serial clock. In the mean time, the clock output is fixed to the specified level with the duty cycle retained. 5. Make the transition to software standby mode. At transition from smart card interface mode to software standby mode 1. Clear software standby mode. 2. Write 1 to the CKE0 bit in SCR to start clock output. A clock signal with the appropriate duty cycle is then generated. Software standby Normal operation Normal operation [1] [2] [3] [4] [5] [6] [7] Figure 15.35 Clock Stop and Restart Procedure Rev.1.00 Jun. 07, 2006 Page 732 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) 15.8 IrDA Operation If the IrDA function is enabled using the IrE bit in IrCR, the TxD5 and RxD5 pins in SCI_5 are allowed to encode and decode the waveform based on the IrDA Specifications version 1.0 (function as the IrTxD and IrRxD pins). Connecting these pins to the infrared data transceiver achieves infrared data communication based on the system defined by the IrDA Specifications version 1.0. In the system defined by the IrDA Specifications version 1.0, communication is started at a transfer rate of 9600 bps, which can be modified later as required. Since the IrDA interface provided by this LSI does not incorporate the capability of automatic modification of the transfer rate, the transfer rate must be modified through programming. Figure 15.36 is the IrDA block diagram. IrDA SCI5 TxD5/IrTxD Pulse encoder TxD RxD RxD5/IrRxD Pulse decoder IrCR Figure 15.36 IrDA Block Diagram Rev.1.00 Jun. 07, 2006 Page 733 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) (1) Transmission During transmission, the output signals from the SCI (UART frames) are converted to IR frames using the IrDA interface (see figure 15.37). For serial data of level 0, a high-level pulse having a width of 3/16 of the bit rate (1-bit interval) is output (initial setting). The high-level pulse can be selected using the IrCKS2 to IrCKS0 bits in IrCR. The high-level pulse width is defined to be 1.41 s at minimum and (3/16 + 2.5%) x bit rate or (3/16 x bit rate) +1.08 s at maximum. For example, when the frequency of system clock is 20 MHz, a high-level pulse width of 1.6 s can be specified because it is the smallest value in the range greater than 1.41 s. For serial data of level 1, no pulses are output. UART frame Start bit 0 1 0 1 0 Data Stop bit 1 1 0 1 0 Transmission IR frame Start bit 0 1 0 1 0 Data Reception Stop bit 1 1 0 1 0 Bit cycle Pulse width is 1.6 s to 3/16 bit cycle Figure 15.37 IrDA Transmission and Reception (2) Reception During reception, IR frames are converted to UART frames using the IrDA interface before inputting to SCI. 0 is output when the high level pulse is detected while 1 is output when no pulse is detected during one bit period. Note that a pulse shorter than the minimum pulse width of 1.41 s is also regarded as a 0 signal. Rev.1.00 Jun. 07, 2006 Page 734 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) (3) High-Level Pulse Width Selection Table 15.13 shows possible settings for bits IrCKS2 to IrCKS0 (minimum pulse width), and this LSI's operating frequencies and bit rates, for making the pulse width shorter than 3/16 times the bit rate in transmission. Table 15.13 IrCKS2 to IrCKS0 Bit Settings Operating Frequency P (MHz) 7.3728 8 9.8304 10 12 12.288 14 14.7456 16 17.2032 18 19.6608 20 25 30 33 35 2400 78.13 100 100 100 100 101 101 101 101 101 101 101 101 101 110 110 110 110 Bit Rate (bps) (Upper Row)/Bit Interval x 3/16 (s) (Lower Row) 9600 19.53 100 100 100 100 101 101 101 101 101 101 101 101 101 110 110 110 110 19200 9.77 100 100 100 100 101 101 101 101 101 101 101 101 101 110 110 110 110 38400 4.88 100 100 100 100 101 101 101 101 101 101 101 101 101 110 110 110 110 57600 3.26 100 100 100 100 101 101 101 101 101 101 101 101 101 110 110 110 110 115200 1.63 100 100 100 100 101 101 101 101 101 101 101 101 101 110 110 110 110 Rev.1.00 Jun. 07, 2006 Page 735 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) 15.9 15.9.1 Interrupt Sources Interrupts in Normal Serial Communication Interface Mode Table 15.14 shows the interrupt sources in normal serial communication interface mode. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt request can activate the DTC or DMAC to allow data transfer. The TDRE flag is automatically cleared to 0 at data transfer by the DTC or DMAC. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER, PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt can activate the DTC or DMAC to allow data transfer. The RDRF flag is automatically cleared to 0 at data transfer by the DTC or DMAC. A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. If a TEI interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt has priority for acceptance. However, note that if the TDRE and TEND flags are cleared to 0 simultaneously by the TXI interrupt processing routine, the SCI cannot branch to the TEI interrupt processing routine later. Note that the priority order for interrupts is different between the group of SCI_0, 1, 2, and 4 and the group of SCI_5 and SCI_6. Table 15.14 SCI Interrupt Sources (SCI_0, 1, 2, and 4) Name ERI RXI TXI TEI Interrupt Source Receive error Receive data full Interrupt Flag ORER, FER, or PER RDRF DTC Activation Not possible Possible Possible Not possible DMAC Activation Not possible Possible Possible Not possible Low Priority High Transmit data empty TDRE Transmit end TEND Rev.1.00 Jun. 07, 2006 Page 736 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) Table 15.15 SCI Interrupt Sources (SCI_5 and SCI_6) Name RXI TXI ERI TEI Interrupt Source Receive data full Interrupt Flag RDRF DTC Activation Not possible Not possible Not possible Not possible DMAC Activation Possible Possible Not possible Not possible Low Priority High Transmit data empty TDRE Receive error Transmit end ORER, FER, or PER TEND 15.9.2 Interrupts in Smart Card Interface Mode Table 15.16 shows the interrupt sources in smart card interface mode. A transmit end (TEI) interrupt request cannot be used in this mode. Note that the priority order for interrupts is different between the group of SCI_0, 1, 2, and 4 and the group of SCI_5 and SCI_6. Table 15.16 SCI Interrupt Sources (SCI_0, 1, 2, and 4) Name ERI RXI TXI Interrupt Source Interrupt Flag DTC Activation Not possible Possible Possible DMAC Activation Not possible Possible Possible Low Priority High Receive error or error ORER, PER, or ERS signal detection Receive data full Transmit data empty RDRF TEND Table 15.17 SCI Interrupt Sources (SCI_5 and SCI_6) Name RXI TXI ERI Interrupt Source Receive data full Transmit data empty Interrupt Flag RDRF TDRE DTC Activation Not possible Not possible Not possible DMAC Activation Possible Possible Not possible Low Priority High Receive error or error ORER, PER, or ERS signal detection Rev.1.00 Jun. 07, 2006 Page 737 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) Data transmission/reception using the DTC or DMAC is also possible in smart card interface mode, similar to in the normal SCI mode. In transmission, the TEND and TDRE flags in SSR are simultaneously set to 1, thus generating a TXI interrupt. This activates the DTC or DMAC by a TXI request thus allowing transfer of transmit data if the TXI request is specified as a source of DTC or DMAC activation beforehand. The TDRE and TEND flags are automatically cleared to 0 at data transfer by the DTC or DMAC. If an error occurs, the SCI automatically re-transmits the same data. During re-transmission, the TEND flag remains as 0, thus not activating the DTC or DMAC. Therefore, the SCI and DTC or DMAC automatically transmit the specified number of bytes, including re-transmission in the case of error occurrence. However, the ERS flag in SSR, which is set at error occurrence, is not automatically cleared; the ERS flag must be cleared by previously setting the RIE bit in SCR to 1 to enable an ERI interrupt request to be generated at error occurrence. When transmitting/receiving data using the DTC or DMAC, be sure to set and enable the DTC or DMAC prior to making SCI settings. For DTC or DMAC settings, see section 8, Data Transfer Controller (DTC) and section 7, DMA Controller (DMAC). In reception, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. This activates the DTC or DMAC by an RXI request thus allowing transfer of receive data if the RXI request is specified as a source of DTC or DMAC activation beforehand. The RDRF flag is automatically cleared to 0 at data transfer by the DTC or DMAC. If an error occurs, the RDRF flag is not set but the error flag is set. Therefore, the DTC or DMAC is not activated and an ERI interrupt request is issued to the CPU instead; the error flag must be cleared. Rev.1.00 Jun. 07, 2006 Page 738 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) 15.10 Usage Notes 15.10.1 Module Stop State Setting Operation of the SCI can be disabled or enabled using the module stop control register. The initial setting is for operation of the SCI to be halted. Register access is enabled by clearing the module stop state. For details, see section 23, Power-Down Modes. 15.10.2 Break Detection and Processing When framing error detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set, and the PER flag may also be set. Note that, since the SCI continues the receive operation even after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. 15.10.3 Mark State and Break Detection When the TE bit is 0, the TxD pin is used as an I/O port whose direction (input or output) and level are determined by DR and DDR. This can be used to set the TxD pin to mark state (high level) or send a break during serial data transmission. To maintain the communication line in mark state (the state of 1) until TE is set to 1, set both DDR and DR to 1. Since the TE bit is cleared to 0 at this point, the TxD pin becomes an I/O port, and 1 is output from the TxD pin. To send a break during serial transmission, first set DDR to 1 and DR to 0, and then clear the TE bit to 0. When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin. 15.10.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) Transmission cannot be started when a receive error flag (ORER, FER, or RER) is set to 1, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that the receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0. Rev.1.00 Jun. 07, 2006 Page 739 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) 15.10.5 Relation between Writing to TDR and TDRE Flag The TDRE flag in SSR is a status flag which indicates that transmit data has been transferred from TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1. Data can be written to TDR irrespective of the TDRE flag status. However, if new data is written to TDR when the TDRE flag is 0, that is, when the previous data has not been transferred to TSR yet, the previous data in TDR is lost. Be sure to write transmit data to TDR after verifying that the TDRE flag is set to 1. 15.10.6 Restrictions on Using DTC or DMAC * When the external clock source is used as a synchronization clock, update TDR by the DMAC or DTC and wait for at least five P clock cycles before allowing the transmit clock to be input. If the transmit clock is input within four clock cycles after TDR modification, the SCI may malfunction (see figure 15.38). * When using the DMAC or DTC to read RDR, be sure to set the receive end interrupt (RXI) as the DTC or DMAC activation source. SCK t TDRE LSB Serial data D0 D1 D2 D3 D4 D5 D6 D7 Note: When external clock is supplied, t must be more than four clock cycles. Figure 15.38 Sample Transmission using DTC in Clocked Synchronous Mode * The DTC is not activated by the RXI or TXI request by SCI_5 or SCI6. Rev.1.00 Jun. 07, 2006 Page 740 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) 15.10.7 SCI Operations during Power-Down State Transmission: Before specifying the module stop state or making a transition to software standby mode, stop the transmit operations (TE = TIE = TEIE = 0). TSR, TDR, and SSR are reset. The states of the output pins in the module stop state or in software standby mode depend on the port settings, and the pins output a high-level signal after cancellation. If the transition is made during data transmission, the data being transmitted will be undefined. To transmit data in the same transmission mode after cancellation of the power-down state, set the TE bit to 1, read SSR, write to TDR, clear TDRE in this order, and then start transmission. To transmit data in a different transmission mode, initialize the SCI first. Figure 15.39 shows a sample flowchart for transition to software standby mode during transmission. Figures 15.40 and 15.41 show the port pin states during transition to software standby mode. Before specifying the module stop state or making a transition to software standby mode from the transmission mode using DTC transfer, stop all transmit operations (TE = TIE = TEIE = 0). Setting the TE and TIE bits to 1 after cancellation sets the TXI flag to start transmission using the DTC. Reception: Before specifying the module stop state or making a transition to software standby mode, stop the receive operations (RE = 0). RSR, RDR, and SSR are reset. If transition is made during data reception, the data being received will be invalid. To receive data in the same reception mode after cancellation of the power-down state, set the RE bit to 1, and then start reception. To receive data in a different reception mode, initialize the SCI first. For using the IrDA function, set the IrE bit in addition to setting the RE bit. Figure 15.42 shows a sample flowchart for mode transition during reception. Rev.1.00 Jun. 07, 2006 Page 741 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) Transmission All data transmitted? Yes Read TEND flag in SSR No [1] TEND = 1 Yes TE = 0 [2] No [1] Data being transmitted is lost halfway. Data can be normally transmitted from the CPU by setting the TE bit to 1, reading SSR, writing to TDR, and clearing the TDRE bit to 0 after clearing software standby mode; however, if the DTC has been activated, the data remaining in the DTC will be transmitted when both the TE and TIE bits are set to 1. [2] Clear the TIE and TEIE bits to 0 when they are 1. [3] Setting of the module stop state is included. Make transition to software standby mode Cancel software standby mode [3] Change operating mode? Yes Initialization No TE = 1 Start transmission Figure 15.39 Sample Flowchart for Software Standby Mode Transition during Transmission Transition to Software standby Transmission end software standby mode canceled mode Transmission start TE bit SCK* output pin TxD output pin Port input/output Port input/output High output Start SCI TxD output Stop Port input/output Port High output SCI TxD output Port Note: * Not output in SCI_5, 6. Figure 15.40 Port Pin States during Software Standby Mode Transition (Internal Clock, Asynchronous Transmission) Rev.1.00 Jun. 07, 2006 Page 742 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) Transmission start Transmission end Transition to Software standby software standby mode canceled mode TE bit SCK output pin TxD output pin Port input/output Port input/output Marking output SCI TxD output Last TxD bit retained Port input/output Port High output* SCI TxD output Port Note: * Initialized in software standby mode Figure 15.41 Port Pin States during Software Standby Mode Transition (Internal Clock, Clocked Synchronous Transmission) (Setting is Prohibited in SCI_5 and SCI_6) Reception Read RDRF flag in SSR RDRF = 1 Yes Read receive data in RDR No [1] [1] Data being received will be invalid. [2] Setting of the module stop state is included. RE = 0 Make transition to software standby mode Cancel software standby mode [2] Change operating mode? Yes Initialization No RE = 1 Start reception Figure 15.42 Sample Flowchart for Software Standby Mode Transition during Reception Rev.1.00 Jun. 07, 2006 Page 743 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) 15.11 CRC Operation Circuit The cyclic redundancy check (CRC) operation circuit detects errors in data blocks. 15.11.1 Features The features of the CRC operation circuit are listed below. * CRC code generated for any desired data length in an 8-bit unit * CRC operation executed on eight bits in parallel * One of three generating polynomials selectable * CRC code generation for LSB-first or MSB-first communication selectable Figure 15.43 shows a block diagram of the CRC operation circuit. CRCCR Control signal Internal bus CRCDIR CRC code generation circuit CRCDOR [Legend] CRCCR: CRC control register CRCDIR: CRC data input register CRCDOR: CRC data output register Figure 15.43 Block Diagram of CRC Operation Circuit Rev.1.00 Jun. 07, 2006 Page 744 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) 15.11.2 Register Descriptions The CRC operation circuit has the following registers. * CRC control register (CRCCR) * CRC data input register (CRCDIR) * CRC data output register (CRCDOR) (1) CRC Control Register (CRCCR) CRCCR initializes the CRC operation circuit, switches the operation mode, and selects the generating polynomial. Bit Bit Name Initial Value R/W 7 DORCLR 0 W 6 0 R 5 0 R 4 0 R 3 0 R 2 LMS 0 R/W 1 G1 0 R/W 0 G0 0 R/W Bit 7 6 to 3 2 Bit Name DORCLR -- LMS Initial Value 0 All 0 0 R/W W R R/W Description CRCDOR Clear Setting this bit to 1 clears CRCDOR to H'0000. Reserved The initial value should not be changed. CRC Operation Switch Selects CRC code generation for LSB-first or MSB-first communication. 0: Performs CRC operation for LSB-first communication. The lower byte (bits 7 to 0) is first transmitted when CRCDOR contents (CRC code) are divided into two bytes to be transmitted in two parts. 1: Performs CRC operation for MSB-first communication. The upper byte (bits 15 to 8) is first transmitted when CRCDOR contents (CRC code) are divided into two bytes to be transmitted in two parts. Rev.1.00 Jun. 07, 2006 Page 745 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) Bit 1 0 Bit Name G1 G0 Initial Value 0 0 R/W R/W R/W Description CRC Generating Polynomial Select: Selects the polynomial. 00: Reserved 01: X + X + X + 1 10: X + X + X + 1 11: X + X + X + 1 16 12 5 16 15 2 8 2 (2) CRC Data Input Register (CRCDIR) CRCDIR is an 8-bit readable/writable register, to which the bytes to be CRC-operated are written. The result is obtained in CRCDOR. Bit Bit Name Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 6 5 4 3 2 1 0 (3) CRC Data Output Register (CRCDOR) CRCDOR is a 16-bit readable/writable register that contains the result of CRC operation when the bytes to be CRC-operated are written to CRCDIR after CRCDOR is cleared. When the CRC operation result is additionally written to the bytes to which CRC operation is to be performed, the CRC operation result will be H'0000 if the data contains no CRC error. When bits 1 and 0 in CRCCR (G1 and G0 bits) are set to 0 and 1, respectively, the lower byte of this register contains the result. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 7 6 5 4 3 2 1 0 Rev.1.00 Jun. 07, 2006 Page 746 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) 15.11.3 CRC Operation Circuit Operation The CRC operation circuit generates a CRC code for LSB-first/MSB-first communications. An 16 12 5 example in which a CRC code for hexadecimal data H'F0 is generated using the X + X + X + 1 polynomial with the G1 and G0 bits in CRCCR set to B'11 is shown below. 1. Write H'83 to CRCCR 7 CRCCR 1 0 0 0 0 0 2. Write H'F0 to CRCDIR 7 CRCDIR 1 1 1 1 0 0 0 11 0 00 CRCDOR clearing 7 CRCDORH CRCDORL 0 0 0 0 0 0 0 0 0 0 0 0 0 00 00 CRCDORH CRCDORL 7 1 1 1 0 1 0 1 0 CRC code generation 0 0 1 1 1 11 11 3. Read from CRCDOR CRC code = H'F78F 4. Serial transmission (LSB first) CRC code 7 1 1 F 1 1 0 1 7 1 0 1 7 1 0 8 0 0 1 1 F 1 0 1 7 1 1 F 1 1 0 0 0 0 Data 0 0 Output Figure 15.44 LSB-First Data Transmission 1. Write H'87 to CRCCR 7 CRCCR 1 0 0 0 0 1 2. Write H'F0 to CRCDIR 7 CRCDIR 1 1 1 1 0 0 0 0 11 0 0 7 CRCDORH CRCDORL 0 0 0 0 0 0 0 0 CRCDOR clearing 0 0 0 0 0 00 00 CRCDORH CRCDORL 7 1 0 1 0 1 0 0 1 CRC code generation 0 1 1 1 1 1 1 1 1 3. Read from CRCDOR CRC code = H'EF1F 4. Serial transmission (MSB first) Data 7 Output 1 1 F 1 1 0 0 0 0 0 0 7 1 1 E 1 0 1 1 F 1 CRC code 0 1 7 0 0 1 0 1 1 1 F 1 0 1 Figure 15.45 MSB-First Data Transmission Rev.1.00 Jun. 07, 2006 Page 747 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) 1. Serial reception (LSB first) CRC code 7 1 1 F 1 1 0 1 7 1 0 1 7 1 0 8 0 0 1 1 F 1 0 1 7 1 1 F 1 1 0 0 0 0 Data 0 0 Input 2. Write H'83 to CRCCR 7 CRCCR 1 0 0 0 0 0 1 0 1 3. Write H'F0 to CRCDIR 7 CRCDIR 1 1 1 1 0 0 0 0 0 CRCDOR clearing 7 CRCDORH CRCDORL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRCDORH CRCDORL 7 1 1 1 0 1 0 1 0 CRC code generation 0 0 1 1 1 1 1 1 1 4. Write H'8F to CRCDIR 7 CRCDIR 1 0 0 0 1 1 1 0 1 5. Write H'F7 to CRCDIR 7 CRCDIR 1 1 1 1 0 1 1 0 1 CRC code generation 7 CRCDORH CRCDORL 0 1 0 1 0 1 0 1 0 0 0 1 0 1 0 0 1 CRCDORH CRCDORL 7 0 0 0 0 0 0 0 0 CRC code generation 0 0 0 0 0 0 0 0 0 6. Read from CRCDOR CRC code = H'0000 No error Figure 15.46 LSB-First Data Reception Rev.1.00 Jun. 07, 2006 Page 748 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) 1. Serial reception (MSB first) Data 7 Input 1 1 F 1 1 0 0 0 0 0 0 7 1 1 E 1 0 1 1 F 1 CRC code 0 1 7 0 0 1 0 1 1 1 F 1 0 1 2. Write H'83 to CRCCR 7 CRCCR 1 0 0 0 0 1 1 0 1 3. Write H'F0 to CRCDIR 7 CRCDIR 1 1 1 1 0 0 0 0 0 CRCDOR clearing 7 CRCDORH CRCDORL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRCDORH CRCDORL 7 1 0 1 0 1 0 0 1 CRC code generation 0 1 1 1 1 1 1 1 1 4. Write H'EF to CRCDIR 7 CRCDIR 1 1 1 0 1 1 1 0 1 5. Write H'1F to CRCDIR 7 CRCDIR 0 0 0 1 1 1 1 0 1 CRC code generation 7 CRCDORH CRCDORL 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 1 0 CRCDORH CRCDORL 7 0 0 0 0 0 0 0 0 CRC code generation 0 0 0 0 0 0 0 0 0 6. Read from CRCDOR CRC code = H'0000 No error Figure 15.47 MSB-First Data Reception Rev.1.00 Jun. 07, 2006 Page 749 of 1102 REJ09B0294-0100 Section 15 Serial Communication Interface (SCI, IrDA, CRC) 15.11.4 Note on CRC Operation Circuit Note that the sequence to transmit the CRC code differs between LSB-first transmission and MSB-first transmission. 1. CRC code generation After specifying the operation method, write data to CRCDIR in the sequence of (1) (2) (3) (4). 7 0 CRCDIR (1) (2) (3) (4) CRC code generation 0 (5) (6) 7 CRCDORH CRCDORL 2. Transmission data (i) LSB-first transmission CRC code 7 (5) 07 (6) 07 (4) 07 (3) 07 (2) 07 (1) 0 Output (ii) MSB-first transmission CRC code 7 Output (1) 07 (2) 07 (3) 07 (4) 07 (5) 07 (6) 0 Figure 15.48 LSB-First and MSB-First Transmit Data Rev.1.00 Jun. 07, 2006 Page 750 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) Section 16 USB Function Module (USB) This LSI incorporates a USB function module (USB). 16.1 Features * The UDC (USB device controller) conforming to USB2.0 and transceiver process USB protocol automatically. Automatic processing of USB standard commands for endpoint 0 (some commands and class/vendor commands require decoding and processing by firmware) * Transfer speed: Supports full-speed (12 Mbps) * Endpoint configuration: Endpoint Name Endpoint 0 Maximum FIFO Buffer Abbreviation Transfer Type Packet Size Capacity (Byte) EP0s EP0i EP0o Endpoint 1 Endpoint 2 Endpoint 3 EP1 EP2 EP3 Setup Control-in Control-out Bulk-out Bulk-in Interrupt-in 8 8 8 64 64 8 8 8 8 128 128 8 DMA Transfer -- -- -- Possible Possible -- Configuration1-Interface0-AlternateSetting0 EndPoint1 EndPoint2 EndPoint3 * Interrupt requests: Generates various interrupt signals necessary for USB transmission/reception * Power mode: Self power mode or bus power mode can be selected by the power mode bit (PWMD) in the control register (CTLR). Rev.1.00 Jun. 07, 2006 Page 751 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) Figure 16.1 shows the block diagram of the USB. Peripheral bus USB function module Interrupt requests Status and control registers D+ UDC FIFO Transceiver D- Clock for USB (48 MHz) [Legend] UDC: USB device controller Figure 16.1 Block Diagram of USB 16.2 Input/Output Pins Table 16.1 shows the USB pin configuration. Table 16.1 Pin Configuration Pin Name VBUS USD+ USDDrVcc DrVss I/O Input I/O I/O Input Input Function USB cable connection monitor pin USB data I/O pin USB data I/O pin Power supply pin for USB on-chip transceiver Ground pin for USB on-chip transceiver Rev.1.00 Jun. 07, 2006 Page 752 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) 16.3 Register Descriptions The USB has following registers. For the information on the addresses of these registers and the state of the register in each processing condition, see section 24, List of Registers. * Interrupt flag register 0 (IFR0) * Interrupt flag register 1 (IFR1) * Interrupt flag register 2 (IFR2) * Interrupt select register 0 (ISR0) * Interrupt select register 1 (ISR1) * Interrupt select register 2 (ISR2) * Interrupt enable register 0 (IER0) * Interrupt enable register 1 (IER1) * Interrupt enable register 2 (IER2) * EP0i data register (EPDR0i) * EP0o data register (EPDR0o) * EP0s data register (EPDR0s) * EP1 data register (EPDR1) * EP2 data register (EPDR2) * EP3 data register (EPDR3) * EP0o receive data size register (EPSZ0o) * EP1 receive data size register (EPSZ1) * Trigger register (TRG) * Data status register (DASTS) * FIFO clear register (FCLR) * DMA transfer setting register (DMA) * Endpoint stall register (EPSTL) * Configuration value register (CVR) * Control register (CTLR) * Endpoint information register (EPIR) * Transceiver test register 0 (TRNTREG0) * Transceiver test register 1 (TRNTREG1) Rev.1.00 Jun. 07, 2006 Page 753 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) 16.3.1 Interrupt Flag Register 0 (IFR0) IFR0, together with interrupt flag registers 1and 2 (IFR1and IFR2), indicates interrupt status information required by the application. When an interrupt source is generated, the corresponding bit is set to 1. And then this bit, in combination with interrupt enable register 0 (IER0), generates an interrupt request to the CPU. To clear, write 0 to the bit to be cleared and 1 to the other bits. However, since EP1FULL and EP2EMPTY are status bits, these bits cannot be cleared. Bit Bit Name Initial Value R/W 7 BRST 0 R/W 6 EP1 FULL 0 R 5 EP2 TR 0 R/W 4 3 2 EP0o TS 0 R/W 1 EP0i TR 0 R/W 0 EP0i TS 0 R/W EP2 EMPTY SETUP TS 1 R 0 R/W Bit 7 Bit Name BRST Initial Value 0 R/W R/W Description Bus Reset This bit is set to 1 when a bus reset signal is detected on the USB bus. (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) 6 EP1FULL 0 R EP1 FIFO Full This bit is set when endpoint 1 receives one packet of data successfully from the host, and holds a value of 1 as long as there is valid data in the FIFO buffer. This is a status bit, and cannot be cleared. 5 EP2TR 0 R/W EP2 Transfer Request This bit is set if there is no valid transmit data in the FIFO buffer when an IN token for endpoint 2 is received from the host. A NACK handshake is returned to the host until data is written to the FIFO buffer and packet transmission is enabled. (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) Rev.1.00 Jun. 07, 2006 Page 754 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) Bit 4 Bit Name EP2EMPTY Initial Value 1 R/W R Description EP2 FIFO Empty This bit is set when at least one of the dual endpoint 2 transmit FIFO buffers is ready for transmit data to be written. This is a status bit, and cannot be cleared. 3 SETUPTS 0 R/W Setup Command Receive Complete This bit is set to 1 when endpoint 0 receives successfully a setup command requiring decoding on the application side, and returns an ACK handshake to the host. (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) 2 EP0oTS 0 R/W EP0o Receive Complete This bit is set to 1 when endpoint 0 receives data from the host successfully, stores the data in the FIFO buffer, and returns an ACK handshake to the host. (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) 1 EP0iTR 0 R/W EP0i Transfer Request This bit is set if there is no valid transmit data in the FIFO buffer when an IN token for endpoint 0 is received from the host. A NACK handshake is returned to the host until data is written to the FIFO buffer and packet transmission is enabled. (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) 0 EP0iTS 0 R/W EP0i Transmit Complete This bit is set when data is transmitted to the host from endpoint 0 and an ACK handshake is returned. (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) Rev.1.00 Jun. 07, 2006 Page 755 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) 16.3.2 Interrupt Flag Register 1 (IFR1) IFR1, together with interrupt flag registers 0 and 2 (IFR0 and IFR2), indicates interrupt status information required by the application. When an interrupt source is generated, the corresponding bit is set to 1. And then this bit, in combination with interrupt enable register 1 (IER1), generates an interrupt request to the CPU. To clear, write 0 to the bit to be cleared and 1 to the other bits. Bit Bit Name Initial Value R/W 7 0 R 6 0 R 5 0 R 4 0 R 3 VBUS MN 0 R 2 EP3 TR 0 R/W 1 EP3 TS 0 R/W 0 VBUSF 0 R/W Bit 7 6 5 4 3 Bit Name -- -- -- VBUS MN Initial Value 0 0 0 0 0 R/W R R R R R Description Reserved These bits are always read as 0. The write value should always be 0. This is a status bit which monitors the state of the VBUS pin. This bit reflects the state of the VBUS pin and generates no interrupt request. This bit is always 0 when the PULLUP_E bit in DMA is 0. 2 EP3 TR 0 R/W EP3 Transfer Request This bit is set if there is no valid transmit data in the FIFO buffer when an IN token for endpoint 3 is received from the host. A NACK handshake is returned to the host until data is written to the FIFO buffer and packet transmission is enabled. (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) 1 EP3 TS 0 R/W EP3 Transmit Complete This bit is set when data is transmitted to the host from endpoint 3 and an ACK handshake is returned. (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) Rev.1.00 Jun. 07, 2006 Page 756 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) Bit 0 Bit Name VBUSF Initial Value 0 R/W R/W Description USB Disconnection Detection When the function is connected to the USB bus or disconnected from it, this bit is set to 1. The VBUS pin of this module is used for detecting connection or disconnection. (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) 16.3.3 Interrupt Flag Register 2 (IFR2) IFR2, together with interrupt flag registers 0 and 1 (IFR0 and IFR1), indicates interrupt status information required by the application. When an interrupt source is generated, the corresponding bit is set to 1. And then this bit, in combination with interrupt enable register 2 (IER2), generates an interrupt request to the CPU. To clear, write 0 to the bit to be cleared and 1 to the other bits. Bit Bit Name Initial Value R/W 7 0 R 6 0 R 5 SURSS 0 R 4 SURSF 0 R/W 3 CFDN 0 R/W 2 0 R 1 SETC 0 R/W 0 SETI 0 R/W Bit 7 6 5 Bit Name -- -- SURSS Initial Value 0 0 0 R/W R R R Description Reserved These bits are always read as 0. The write value should always be 0. Suspend/Resume Status This is a status bit that describes bus state. 0: Normal state 1: Suspended state This bit is a status bit and generates no interrupt request. Rev.1.00 Jun. 07, 2006 Page 757 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) Bit 4 Bit Name SURSF Initial Value 0 R/W R/W Description Suspend/Resume Detection This bit is set to 1 when the state changed from normal to suspended state or vice versa. The corresponding interrupt output is RESUME, USBINTN2, and USBINTN3. (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) 3 CFDN 0 R/W End Point Information Load End This bit is set to 1 when writing data in the endpoint information register to the EPIR register ends (load end). This module starts the USB operation after the endpoint information is completely set. (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) 2 -- 0 R Reserved This bit is always read as 0. The write value should always be 0. (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) 1 SETC 0 R/W Set_Configuration Command Detection When the Set_Configuration command is detected, this bit is set to 1. (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) 0 SETI 0 R/W Set_Interface Command Detection When the Set_Interface command is detected, this bit is set to 1. (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) Rev.1.00 Jun. 07, 2006 Page 758 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) 16.3.4 Interrupt Select Register 0 (ISR0) ISR0 selects the vector numbers of the interrupt requests indicated in interrupt flag register 0 (IFR0). If the USB issues an interrupt request to the INTC when a bit in ISR0 is cleared to 0, the interrupt corresponding to the bit will be USBINTN2. If the USB issues an interrupt request to the INTC when a bit in ISR0 is set to 1, the corresponding interrupt will be USBINTN3. Bit Bit Name Initial Value R/W 7 BRST 0 R/W 6 EP1 FULL 0 R/W 5 EP2 TR 0 R/W 4 3 2 EP0o TS 0 R/W 1 EP0i TR 0 R/W 0 EP0i TS 0 R/W EP2 EMPTY SETUP TS 0 R/W 0 R/W Bit 7 6 5 4 3 2 1 0 Bit Name BRST EP1 FULL EP2 TR Initial Value 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Bus Reset EP1 FIFO Full EP2 Transfer Request EP2 FIFO Empty Setup Command Receive Complete EP0o Receive Complete EP0i Transfer Request EP0i Transmission Complete EP2 EMPTY 0 SETUP TS EP0o TS EP0i TR EP0i TS 0 0 0 0 Rev.1.00 Jun. 07, 2006 Page 759 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) 16.3.5 Interrupt Select Register 1 (ISR1) ISR1 selects the vector numbers of the interrupt requests indicated in interrupt flag register 1 (IFR1). If the USB issues an interrupt request to the INTC when a bit in ISR0 is cleared to 0, the interrupt corresponding to the bit will be USBINTN2. If the USB issues an interrupt request to the INTC when a bit in ISR0 is set to 1, the corresponding interrupt will be USBINTN3. Bit Bit Name Initial Value R/W 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 EP3 TR 1 R/W 1 EP3 TS 1 R/W 0 VBUSF 1 R/W Bit 7 6 5 4 3 2 1 0 Bit Name EP3 TR EP3 TS VBUSF Initial Value 0 0 0 0 0 1 1 1 R/W R R R R R R/W R/W R/W Description Reserved These bits are always read as 0. The write value should always be 0. EP3 Transfer Request EP3 Transmission Complete USB Bus Connect Rev.1.00 Jun. 07, 2006 Page 760 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) 16.3.6 Interrupt Select Register 2 (ISR2) ISR2 selects the vector numbers of the interrupt requests indicated in interrupt flag register 2 (IFR2). If the USB issues an interrupt request to the INTC when a bit in ISR0 is cleared to 0, the interrupt corresponding to the bit will be USBINTN2. If the USB issues an interrupt request to the INTC when a bit in ISR0 is set to 1, the corresponding interrupt will be USBINTN3. Bit Bit Name Initial Value R/W 7 0 R 6 0 R 5 0 R 4 SURSE 1 R/W 3 CFDN 1 R/W 2 1 R 1 SETCE 1 R/W 0 SETIE 1 R/W Bit 7 6 5 4 3 2 Bit Name SURSE CFDN Initial Value 0 0 0 1 1 1 R/W R R R R/W R/W R Description Reserved These bits are always read as 0. The write value should always be 0. Suspend/Resume Detection End Point Information Load End Reserved This bit is always read as 1. The write value should always be 1. 1 0 SETCE SETIE 1 1 R/W R/W Set_Configuration Command Detection Set_Interface Command Detection Rev.1.00 Jun. 07, 2006 Page 761 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) 16.3.7 Interrupt Enable Register 0 (IER0) IER0 enables the interrupt requests of interrupt flag register 0 (IFR0). When an interrupt flag is set to 1 while the corresponding bit of each interrupt is set to 1, an interrupt request is sent to the CPU. The interrupt vector number is determined by the contents of interrupt select register 0 (ISR0). Bit Bit Name Initial Value R/W 7 BRST 0 R/W 6 EP1 FULL 0 R/W 5 EP2 TR 0 R/W 4 3 2 EP0o TS 0 R/W 1 EP0i TR 0 R/W 0 EP0i TS 0 R/W EP2 EMPTY SETUP TS 0 R/W 0 R/W Bit 7 6 5 4 3 2 1 0 Bit Name BRST EP1 FULL EP2 TR EP2 EMPTY SETUP TS EP0o TS EP0i TR EP0i TS Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Bus Reset EP1 FIFO Full EP2 Transfer Request EP2 FIFO Empty Setup Command Receive Complete EP0o Receive Complete EP0i Transfer Request EP0i Transmission Complete Rev.1.00 Jun. 07, 2006 Page 762 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) 16.3.8 Interrupt Enable Register 1 (IER1) IER1 enables the interrupt requests of interrupt flag register 1 (IFR1). When an interrupt flag is set to 1 while the corresponding bit of each interrupt is set to 1, an interrupt request is sent to the CPU. The interrupt vector number is determined by the contents of interrupt select register 1 (ISR1). Bit Bit Name Initial Value R/W 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 EP3 TR 0 R/W 1 EP3 TS 0 R/W 0 VBUSF 0 R/W Bit 7 6 5 4 3 2 1 0 Bit Name EP3 TR EP3 TS VBUSF Initial Value 0 0 0 0 0 0 0 0 R/W R R R R R R/W R/W R/W Description Reserved These bits are always read as 0. The write value should always be 0. EP3 Transfer Request EP3 Transmission Complete USB Bus Connect 16.3.9 Interrupt Enable Register 2 (IER2) IER2 enables the interrupt requests of interrupt flag register 2 (IFR2). When an interrupt flag is set to 1 while the corresponding bit of each interrupt is set to 1, an interrupt request is sent to the CPU. The interrupt vector number is determined by the contents of interrupt select register 2 (ISR2). Bit Bit Name Initial Value R/W 7 SSRSME 0 R/W 6 0 R 5 0 R 4 SURSE 0 R/W 3 CFDN 0 R/W 2 0 R 1 SETCE 0 R/W 0 SETIE 0 R/W Rev.1.00 Jun. 07, 2006 Page 763 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) Bit 7 Bit Name SSRSME Initial Value 0 R/W R/W Description Resume Detection for Software Standby Cancel For the details of the operation, see section 16.5.3, Suspend and Resume Operations. 6, 5 All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. 4 SURSE 0 R/W Suspend/Resume Detection For the details of the operation, see section 16.5.3, Suspend and Resume Operations. 3 2 CFDN 0 0 R/W R End Point Information Load End Reserved This bit is always read as 0. The write value should always be 0. 1 0 SETCE SETIE 0 0 R/W R/W Set_Configuration Command Detection Set_Interface Command Detection 16.3.10 EP0i Data Register (EPDR0i) EPDR0i is an 8-byte transmit FIFO buffer for endpoint 0. EPDR0i holds one packet of transmit data for control-in. Transmit data is fixed by writing one packet of data and setting EP0iPKTE in the trigger register. When an ACK handshake is returned from the host after the data has been transmitted, EP0iTS in interrupt flag register 0 is set. This FIFO buffer can be initialized by means of EP0iCLR in the FCLR register. Bit Bit Name Initial Value R/W 7 D7 Undefined W 6 D6 Undefined W 5 D5 Undefined W 4 D4 Undefined W 3 D3 Undefined W 2 D2 Undefined W 1 D1 Undefined W 0 D0 Undefined W Bit 7 to 0 Bit Name D7 to D0 Initial Value R/W Description Data register for control-in transfer Undefined W Rev.1.00 Jun. 07, 2006 Page 764 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) 16.3.11 EP0o Data Register (EPDR0o) EPDR0o is an 8-byte receive FIFO buffer for endpoint 0. EPDR0o holds endpoint 0 receive data other than setup commands. When data is received successfully, EP0oTS in interrupt flag register 0 is set, and the number of receive bytes is indicated in the EP0o receive data size register. After the data has been read, setting EP0oRDFN in the trigger register enables the next packet to be received. This FIFO buffer can be initialized by means of BP0oCLR in the FCLR register. Bit Bit Name Initial Value R/W 7 D7 0 R 6 D6 0 R 5 D5 0 R 4 D4 0 R 3 D3 0 R 2 D2 0 R 1 D1 0 R 0 D0 0 R Bit 7 to 0 Bit Name D7 to D0 Initial Value All 0 R/W R Description Data register for control-out transfer 16.3.12 EP0s Data Register (EPDR0s) EPDR0s is an 8-byte FIFO buffer specifically for receiving endpoint 0 setup commands. Only the setup command to be processed by the application is received. When command data is received successfully, the SETUPTS bit in interrupt flag register 0 is set. As a latest setup command must be received in high priority, if data is left in this buffer, it will be overwritten with new data. If reception of the next command is started while the current command is being read, command reception has priority, the read by the application is forcibly stopped, and the read data is invalid. Bit Bit Name Initial Value R/W 7 D7 0 R 6 D6 0 R 5 D5 0 R 4 D4 0 R 3 D3 0 R 2 D2 0 R 1 D1 0 R 0 D0 0 R Bit 7 to 0 Bit Name D7 to D0 Initial Value All 0 R/W R Description Data register for storing the setup command at the control-out transfer Rev.1.00 Jun. 07, 2006 Page 765 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) 16.3.13 EP1 Data Register (EPDR1) EPDR1 is a 128-byte receive FIFO buffer for endpoint 1. EPDR1 has a dual-buffer configuration, and has a capacity of twice the maximum packet size. When one packet of data is received successfully, EP1FULL in interrupt flag register 0 is set, and the number of receive bytes is indicated in the EP1 receive data size register. After the data has been read, the buffer that was read is enabled to receive data again by writing 1 to the EP1RDFN bit in the trigger register. The receive data in this FIFO buffer can be transferred by DMA. This FIFO buffer can be initialized by means of EP1CLR in the FCLR register. Bit Bit Name Initial Value R/W 7 D7 0 R 6 D6 0 R 5 D5 0 R 4 D4 0 R 3 D3 0 R 2 D2 0 R 1 D1 0 R 0 D0 0 R Bit 7 to 0 Bit Name D7 to D0 Initial Value All 0 R/W R Description Data register for endpoint 1 transfer 16.3.14 EP2 Data Register (EPDR2) EPDR2 is a 128-byte transmit FIFO buffer for endpoint 2. EPDR2 has a dual-buffer configuration, and has a capacity of twice the maximum packet size. When transmit data is written to this FIFO buffer and EP2PKTE in the trigger register is set, one packet of transmit data is fixed, and the dual-FIFO buffer is switched over. The transmit data for this FIFO buffer can be transferred by DMA. This FIFO buffer can be initialized by means of EP2CLR in the FCLR register. Bit Bit Name Initial Value R/W 7 D7 Undefined W 6 D6 Undefined W 5 D5 Undefined W 4 D4 Undefined W 3 D3 Undefined W 2 D2 Undefined W 1 D1 Undefined W 0 D0 Undefined W Bit 7 to 0 Bit Name D7 to D0 Initial Value R/W Description Data register for endpoint 2 transfer Undefined W Rev.1.00 Jun. 07, 2006 Page 766 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) 16.3.15 EP3 Data Register (EPDR3) EPDR3 is an 8-byte transmit FIFO buffer for endpoint 3. EPDR3 holds one packet of transmit data for the interrupt transfer of endpoint 3. Transmit data is fixed by writing one packet of data and setting EP3PKTE in the trigger register. When an ACK handshake is returned from the host after one packet of data has been transmitted successfully, EP3TS in interrupt flag register 0 is set. This FIFO buffer can be initialized by means of EP3CLR in the FCLR register. Bit Bit Name Initial Value R/W 7 D7 Undefined W 6 D6 Undefined W 5 D5 Undefined W 4 D4 Undefined W 3 D3 Undefined W 2 D2 Undefined W 1 D1 Undefined W 0 D0 Undefined W Bit 7 to 0 Bit Name D7 to D0 Initial Value R/W Description Data register for endpoint 3 transfer Undefined W 16.3.16 EP0o Receive Data Size Register (EPSZ0o) EPSZ0o indicates the number of bytes received at endpoint 0 from the host. Bit Bit Name Initial Value R/W 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 -- 0 R Bit 7 to 0 Bit Name -- Initial Value All 0 R/W R Description Number of receive data for endpoint 0 Rev.1.00 Jun. 07, 2006 Page 767 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) 16.3.17 EP1 Receive Data Size Register (EPSZ1) EPSZ1 is a receive data size resister for endpoint 1. EPSZ1 indicates the number of bytes received from the host. The FIFO for endpoint 1 has a dual-buffer configuration. The size of the received data indicated by this register is the size of the currently selected side (can be read by CPU). Bit Bit Name Initial Value R/W 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 -- 0 R Bit 7 to 0 Bit Name -- Initial Value All 0 R/W R Description Number of received bytes for endpoint 1 16.3.18 Trigger Register (TRG) TRG generates one-shot triggers to control the transfer sequence for each endpoint. Bit Bit Name Initial Value R/W 7 Undefined 6 EP3 PKTE Undefined W 5 EP1 RDFN Undefined W 4 EP2 PKTE Undefined W 3 Undefined 2 1 0 EP0s RDFN EP0o RDFN EP0i PKTE Undefined W Undefined W Undefined W Bit 7 6 Bit Name EP3 PKTE Initial Value Undefined Undefined R/W W Description Reserved The write value should always be 0. EP3 Packet Enable After one packet of data has been written to the endpoint 3 transmit FIFO buffer, the transmit data is fixed by writing 1 to this bit. Rev.1.00 Jun. 07, 2006 Page 768 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) Bit 5 Bit Name EP1 RDFN Initial Value Undefined R/W W Description EP1 Read Complete Write 1 to this bit after one packet of data has been read from the endpoint 1 FIFO buffer. The endpoint 1 receive FIFO buffer has a dual-buffer configuration. Writing 1 to this bit initializes the FIFO that was read, enabling the next packet to be received. 4 EP2 PKTE Undefined W EP2 Packet Enable After one packet of data has been written to the endpoint 2 transmit FIFO buffer, the transmit data is fixed by writing 1 to this bit. 3 2 Undefined W Reserved The write value should always be 0. EP0s Read Complete Write 1 to this bit after data for the EP0s command FIFO has been read. Writing 1 to this bit enables transfer of data in the following data stage. A NACK handshake is returned in response to transfer requests from the host in the data stage until 1 is written to this bit. EP0s RDFN Undefined 1 EP0o RDFN Undefined W EP0o Read Complete Writing 1 to this bit after one packet of data has been read from the endpoint 0 transmit FIFO buffer initializes the FIFO buffer, enabling the next packet to be received. 0 EP0i PKTE Undefined W EP0i Packet Enable After one packet of data has been written to the endpoint 0 transmit FIFO buffer, the transmit data is fixed by writing 1 to this bit. Rev.1.00 Jun. 07, 2006 Page 769 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) 16.3.19 Data Status Register (DASTS) DASTS indicates whether the transmit FIFO buffers contain valid data. A bit is set when data is written to the corresponding FIFO buffer and the packet enable state is set, and cleared when all data has been transmitted to the host. Bit Bit Name Initial Value R/W 7 0 R 6 0 R 5 EP3 DE 0 R 4 EP2 DE 0 R 3 0 R 2 0 R 1 0 R 0 EP0i DE 0 R Bit 7 6 5 Bit Name EP3 DE Initial Value 0 0 0 R/W R R R Description Reserved These bits are always read as 0. The write value should always be 0. EP3 Data Present This bit is set when the endpoint 3 FIFO buffer contains valid data. 4 EP2 DE 0 R EP2 Data Present This bit is set when the endpoint 2 FIFO buffer contains valid data. 3 2 1 0 EP0i DE 0 0 0 0 R R R R Reserved These bits are always read as 0. EP0i Data Present This bit is set when the endpoint 0 FIFO buffer contains valid data. Rev.1.00 Jun. 07, 2006 Page 770 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) 16.3.20 FIFO Clear Register (FCLR) FCLR is a register to initialize the FIFO buffers for each endpoint. Writing 1 to a bit clears all the data in the corresponding FIFO buffer. Note that the corresponding interrupt flag is not cleared. Do not clear a FIFO buffer during transfer. Bit Bit Name Initial Value R/W 7 Undefined 6 EP3 CLR Undefined W 5 EP1 CLR Undefined W 4 EP2 CLR Undefined W 3 Undefined 2 Undefined 1 EP0o CLR Undefined W 0 EP0i CLR Undefined W Bit 7 6 Bit Name EP3 CLR Initial Value Undefined Undefined R/W W Description Reserved The write value should always be 0. EP3 Clear Writing 1 to this bit initializes the endpoint 3 transmit FIFO buffer. 5 EP1 CLR Undefined W EP1 Clear Writing 1 to this bit initializes both sides of the endpoint 1 receive FIFO buffer. 4 EP2 CLR Undefined W EP2 Clear Writing 1 to this bit initializes both sides of the endpoint 2 transmit FIFO buffer. 3 2 1 EP0o CLR Undefined Undefined W Reserved The write value should always be 0. EP0o Clear Writing 1 to this bit initializes the endpoint 0 receive FIFO buffer. 0 EP0i CLR Undefined W EP0i Clear Writing 1 to this bit initializes the endpoint 0 transmit FIFO buffer. Rev.1.00 Jun. 07, 2006 Page 771 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) 16.3.21 DMA Transfer Setting Register (DMA) DMA transfer can be carried out between the endpoint 1 and 2 data registers and memory by means of the on-chip direct memory access controller (DMAC). Dual address transfer is performed in bytes. To start DMA transfer, DMAC settings must be made in addition to the settings in this register. Bit Bit Name Initial Value R/W 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 PULLUP_E 0 R/W 1 EP2DMAE 0 R/W 0 EP1DMAE 0 R/W Bit 7 6 5 4 3 2 Bit Name Initial Value 0 0 0 0 0 R/W R R R R R R/W Description Reserved These bits are always read as 0. The write value should always be 0. PULLUP_E 0 PULLUP Enable This pin performs the pull-up control for the D+ pin, with using PM4 as the pull-up control pin. 0: D+ is not pulled up. 1: D+ is pulled up. Rev.1.00 Jun. 07, 2006 Page 772 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) Bit 1 Bit Name EP2DMAE Initial Value 0 R/W R/W Description Endpoint 2 DMA Transfer Enable When this bit is set, DMA transfer is enabled from memory to the endpoint 2 transmit FIFO buffer. If there is at least one byte of open space in the FIFO buffer, a DMAC start interrupt signal (USBINTN1) is asserted. In DMA transfer, when 64 bytes are written to the FIFO buffer the EP2 packet enable bit is set automatically, allowing 64 bytes of data to be transferred, and if there is still space in the other side of the two FIFOs, the DMAC start interrupt signal (USBINTN1) is asserted again. However, if the size of the data packet to be transmitted is less than 64 bytes, the EP2 packet enable bit is not set automatically, and so should be set by the CPU with a DMA transfer end interrupt. As EP2-related interrupt requests to the CPU are not automatically masked, interrupt requests should be masked as necessary in the interrupt enable register. * Operating procedure 1. Write of 1 to the EP2 DMAE bit in DMAR 2. Set the DMAC to activate through USBINTN1 3. Transfer count setting in the DMAC 4. DMAC activation 5. DMA transfer 6. DMA transfer end interrupt generated See section 16.8.3, DMA Transfer for Endpoint 2. Rev.1.00 Jun. 07, 2006 Page 773 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) Bit 0 Bit Name EP1DMAE Initial Value 0 R/W R/W Description Endpoint 1 DMA Transfer Enable When this bit is set, a DMAC start interrupt signal (USBINTN0) is asserted and DMA transfer is enabled from the endpoint 1 receive FIFO buffer to memory. If there is at least one byte of receive data in the FIFO buffer, the DMAC start interrupt signal (USBINTN0) is asserted. In DMA transfer, when all the received data is read, EP1 is automatically read and the completion trigger operates. EP1-related interrupt requests to the CPU are not automatically masked. * Operating procedure: 1. Write of 1 to the EP1 DMAE bit in DMA 2. Set the DMAC to activate through USBINTN0 3. Transfer count setting in the DMAC 4. DMAC activation 5. DMA transfer 6. DMA transfer end interrupt generated See section 16.8.2, DMA Transfer for Endpoint 1. Rev.1.00 Jun. 07, 2006 Page 774 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) 16.3.22 Endpoint Stall Register (EPSTL) The bits in EPSTL are used to forcibly stall the endpoints on the application side. While a bit is set to 1, the corresponding endpoint returns a stall handshake to the host. The stall bit for endpoint 0 is cleared automatically on reception of 8-byte command data for which decoding is performed by the function and the EP0 STL bit is cleared. When the SETUPTS flag in the IFR0 register is set to 1, writing 1 to the EP0 STL bit is ignored. For detailed operation, see section 16.7, Stall Operations. Bit Bit Name Initial Value R/W 7 0 R 6 0 R 5 0 R 4 0 R 3 EP3STL 0 R/W 2 EP2STL 0 R/W 1 EP1STL 0 R/W 0 EP0STL 0 R/W Bit 7 6 5 4 3 Bit Name EP3STL Initial Value 0 0 0 0 0 R/W R R R R R/W Description Reserved These bits are always read as 0. The write value should always be 0. EP3 Stall When this bit is set to 1, endpoint 3 is placed in the stall state. 2 EP2STL 0 R/W EP2 Stall When this bit is set to 1, endpoint 2 is placed in the stall state. 1 EP1STL 0 R/W EP1 Stall When this bit is set to 1, endpoint 1 is placed in the stall state. 0 EP0STL 0 R/W EP0 Stall When this bit is set to 1, endpoint 0 is placed in the stall state. Rev.1.00 Jun. 07, 2006 Page 775 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) 16.3.23 Configuration Value Register (CVR) This register stores the Configuration, Interface, or Alternate set value when the Set Configuration or Set Interface command from the host is correctly received. Bit Bit Name Initial Value R/W 7 CNFV1 0 R 6 CNFV0 0 R 5 INTV1 0 R 4 INTV0 0 R 3 0 R 2 ALTV2 0 R 1 ALTV1 0 R 0 ALTV0 0 R Bit 7 6 5 4 3 Bit Name CNFV1 CNFV0 INTV1 INTV0 Initial Value All 0 R/W R Description These bits store Configuration Setting value when they receive Set Configuration command. CNFV is updated when the SETC bit in IFR2 is set to 1. These bits store Interface Setting value when they receive Set Interface command. INTV is updated when the SETI bit in IFR2 is set to 1. Reserved This bit is always read as 0. The write value should always be 0. All 0 R 0 R 2 1 0 ALTV2 ALTV1 ALTV0 0 0 0 R R R These bits store Alternate Setting value when they receive Set Interface command. ALTV2 to ALTV0 are updated when the SETI bit in IFR2 is set to 1. 16.3.24 Control Register (CTLR) This register sets functions for bits ASCE, PWMD, RSME, and, PWUPS. Bit Bit Name Initial Value R/W 7 0 R 6 0 R 5 0 R 4 RWUPS 0 R 3 RSME 0 R/W 2 PWMD 0 R/W 1 ASCE 0 R/W 0 0 R Rev.1.00 Jun. 07, 2006 Page 776 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) Bit 7 6 5 4 Bit Name RWUPS Initial Value 0 0 0 0 R/W R R R R Description Reserved These bits are always read as 0. The write value should always be 0. Remote Wakeup Status This status bit indicates remote wakeup command from USB host is enabled or disabled. This bit is set to 0 when remote wakeup command from UBM host is disabled by Device_Remote_Wakeup due to Set Feature or Clear Feature request. This bit is set to 1 when remote wakeup command is enabled. 3 RSME 0 R/W Resume Enable This bit releases the suspend state (or executes remote wakeup). When RSME is set to 1, resume request starts. If RSME is once set to 1, clear this bit to 0 again afterwards. In this case, the value 1 set to RSME must be kept for at least one clock period of 12-MHz clock. 2 PWMD 0 R/W Bus Power Mode This bit specifies the USB power mode. When PWMD is set to 0, the self-power mode is selected for this module. When set to 1, the bus-power mode is selected. 1 ASCE 0 R/W Automatic Stall Clear Enable Setting the ASCE bit to 1 automatically clears the stall setting bit (the EPxSTL (x = 1, 2, or 3) bit in EPSTLR0 or EPSTR1) of the end point that has returned the stall handshake to the host. The automatic stall clear enable is common to the all end points. Thus the individual control of the end point is not possible. When the ASCE bit is set to 0, the stall setting bit is not automatically cleared. This bit must be released by the users. To enable this bit, make sure that the ASCE bit should be set to 1 before the EPxSTL (x = 1, 2, or 3) bit in EPSTL is set to 1. 0 -- 0 R Reserved This bit is always read as 0. The write value should always be 0. Rev.1.00 Jun. 07, 2006 Page 777 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) 16.3.25 Endpoint Information Register (EPIR) This register sets the information for each endpoint. Each endpoint needs five bytes to store the information. Writing data should be done in sequence starting at logical endpoint 0. Do not write data of more than 50 bytes (five bytes multiplied by ten endpoints) to this register. The information should be written to this register only once at a power-on reset and no data should be written after that. Description of writing data for one endpoint is shown below. Although this register consists of one register to which data is written sequentially for one address, the write data for the endpoint 0 is described as EPIR00 to EPIR05 (EPIR endpoint number in write order) to make the explanation understood easier. Write should start at EPIR00. Bit Bit Name Initial Value R/W 7 D7 Undefined W 6 D6 Undefined W 5 D5 Undefined W 4 D4 Undefined W 3 D3 Undefined W 2 D2 Undefined W 1 D1 Undefined W 0 D0 Undefined W * EPIR00 Bit 7 to 4 Bit Name D7 to D4 Initial Value Undefined R/W W Description Endpoint Number [Enable setting range] 0 to 3 3, 2 D3, D2 Undefined W Endpoint Configuration Number [Enable setting range] 0 or 1 1, 0 D1, D0 Undefined W Endpoint Interface Number [Enable setting range] 0 to 3 Rev.1.00 Jun. 07, 2006 Page 778 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) * EPIR01 Bit 7, 6 Bit Name D7, D6 Initial Value Undefined R/W W Description Endpoint Alternate Number [Possible setting range] 0 or 1 5, 4 D5, D4 Undefined W Endpoint Transmission [Possible setting range] 0: Control 1: Setting prohibited 2: Bulk 3: Interrupt 3 D3 Undefined W Endpoint Transmission Direction [Possible setting range] 0: Out 1: In 2 to 0 D2 to D0 Undefined W Reserved [Possible setting range] Fixed to 0. * EPIR02 Bit 7 to 1 Bit Name D7 to D1 Initial Value Undefined R/W W Description Endpoint Maximum Packet Size [Possible setting range] 0 to 64 0 D0 Undefined W Reserved [Possible setting range] Fixed to 0. * EPIR03 Bit 7 to 0 Bit Name D7 to D0 Initial Value Undefined R/W W Description Reserved [Possible setting range] Fixed to 0. Rev.1.00 Jun. 07, 2006 Page 779 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) * EPIR04 Bit 7 to 0 Bit Name D7 to D0 Initial Value Undefined R/W W Description Endpoint FIFO Number [Possible setting range] 0 to 3 The endpoint number is the endpoint number the USB host uses. The endpoint FIFO number corresponds to the endpoint number described in this manual. Thus data transfer between the USB host and the endpoint FIFO can be enabled by putting the endpoint number and the endpoint FIFO number in one-to-one correspondence. Note that the setting value is subject to a limitation described below. Since each endpoint FIFO number is optimized by the exclusive software that corresponds to the transfer system, direction, and the maximum packet size, make sure to set the endpoint FIFO number to the data described in table 16.2. 1. The endpoint FIFO number 1 cannot designate other than the maximum packed size of 8 bytes, control transfer method, and out transfer direction. 2. The endpoint number 0 and the endpoint FIFO number must have one-on one relationship. 3. The maximum packet size for the endpoint FIFO number 0 is 8 bytes only. 4. The endpoint FIFO number 0 can specify only the maximum packet size and the data for the rest should be all 0. 5. The maximum packet size for the endpoint FIFO numbers 1 and 2 is limited to 64 bytes. 6. The maximum packet size for the endpoint FIFO numbers 3 is limited to 8 bytes. 7. The maximum number of endpoint information setting is ten. 8. Up to ten endpoint information setting should be made. 9. Write 0 to the endpoints not in use. Table 16.2 shows the example of limitations for the maximum packet size, the transfer method, and the transfer direction. Table 16.2 Example of Limitations for Setting Values Endpoint FIFO Number 0 1 2 3 Maximum Packet Size 8 bytes 64 bytes 64 bytes 8 bytes Transfer Method Control Bulk Bulk Interrupt Transfer Direction Out In In Rev.1.00 Jun. 07, 2006 Page 780 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) Table 16.3 shows a specific example of setting. Table 16.3 Example of Setting Endpoint Number Conf. 0 1 2 3 1 1 1 1 1 Int. 0 0 0 1 1 Alt. 0 0 0 0 1 Transfer Method Control Bulk Bulk Interrupt Transfer Direction In/Out Out In In Maximum Packet Size 8 bytes 64 bytes 64 bytes 8 bytes Endpoint FIFO Number 0 1 2 3 N 0 1 2 3 4 5 6 7 8 9 EPIR[N]0 00 14 24 34 00 00 00 00 00 00 EPIR[N]1 00 20 28 38 00 00 00 00 00 00 EPIR[N]2 10 80 80 10 00 00 00 00 00 00 EPIR[N]3 00 00 00 00 00 00 00 00 00 00 EPIR[N]4 00 01 02 03 00 00 00 00 00 00 Configuration 1 Interface 0 Alternate Setting 0 Endpoint Number 0 1 2 3 Endpoint FIFO Number 0 1 2 3 Attribute Control BulkOut BulkIn InterruptIn Rev.1.00 Jun. 07, 2006 Page 781 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) 16.3.26 Transceiver Test Register 0 (TRNTREG0) TRNTREG0 controls the on-chip transceiver output signals. Setting the PTSTE bit to 1 specifies the transceiver output signals (USD+ and USD-) arbitrarily. Table 16.4 shows the relationship between TRNTREG0 setting and pin output. Bit Bit Name Initial Value R/W 7 PTSTE 0 R/W 6 0 R 5 0 R 4 0 R 3 SUSPEND 0 R/W 2 txenl 0 R/W 1 txse0 0 R/W 0 txdata 0 R/W Bit 7 Bit Name PTSTE Initial Value 0 R/W R/W Description Pin Test Enable Enables the test control for the on-chip transceiver output pins (USD+ and USD-). 6 to 4 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 3 2 1 0 SUSPEND txenl txse0 txdata 0 0 0 0 R/W R/W R/W R/W On-Chip Transceiver Output Signal Setting SUSPEND: Sets the (SUSPEND) signal of the on-chip transceiver. txenl: txse0: txdata: Sets the output enable (txenl) signal of the on-chip transceiver. Sets the Signal-ended 0 (txse0) signal of the on-chip transceiver. Sets the (txdata) signal of the on-chip transceiver. Rev.1.00 Jun. 07, 2006 Page 782 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) Table 16.4 Relationship between TRNTREG0 Setting and Pin Output Pin Input VBUS 0 1 1 1 1 1 PTSTE X 0 1 1 1 1 Register Setting txenl X X 0 0 0 1 txse0 X X 0 0 1 X txdata X X 0 1 x X USD+ Hi-Z 0 1 0 Hi-Z Pin Output USDHi-Z 1 0 0 Hi-Z [Legend] X: Don't care. : Cannot be controlled. Indicates state in normal operation according to the USB operation and port settings. Rev.1.00 Jun. 07, 2006 Page 783 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) 16.3.27 Transceiver Test Register 1 (TRNTREG1) TRNTREG1 is a test register that can monitor the on-chip transceiver input signal. Setting bits PTSTE and txenl in TRNTREG0 to 1 enables monitoring the on-chip transceiver input signal. Table 16.5 shows the relationship between pin input and TRNTREG1 monitoring value. Bit Bit Name Initial Value R/W 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 xver_data * R 1 dpls * R 0 dmns * R Bit 7 to 3 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 2 1 0 xver_data dpls dmns * * * R R R On-Chip Transceiver Input Signal Monitor xver_data: Monitors the differential input level (xver_data) signal of the on-chip transceiver. dpls: dmns: Monitors the USD+ (dpls) signal of the onchip transceiver. Monitors the USD- (dmns) signal of the onchip transceiver. Note: * Determined by the state of pins, VBUS, USD+, and USD- Rev.1.00 Jun. 07, 2006 Page 784 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) Table 16.5 Relationship between Pin Input and TRNTREG1 Monitoring Value Register Setting Pin Input TRNTREG1 Monitoring Value PTSTE SUSPEND VBUS USD+ USD- xver_data dpls 0 X 0 1 X 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 dmns Remarks 0 0 1 0 1 0 1 0 1 1 Can be monitored when VBUS = 0 Cannot be monitored when PTSTE = 0 Can be monitored when PTSTE = 1 0 1 1 1 1 1 1 1 1 1 X 0 0 0 0 1 1 1 1 X X 1 1 1 1 1 1 1 1 0 X 0 0 1 1 0 0 1 1 X X 0 1 0 1 0 1 0 1 X [Legend] X: Don't care. Rev.1.00 Jun. 07, 2006 Page 785 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) 16.4 Interrupt Sources This module has five interrupt signals. Table 16.6 shows the interrupt sources and their corresponding interrupt request signals. The USBINTN interrupt signals are activated at low level. The USBINTN interrupt requests can only be detected at low level (specified as level sensitive). Table 16.6 Interrupt Sources Transfer Mode Control transfer (EP0) Interrupt Source EP0i_TS* EP0i_TR* EP0o_TS* SETUP_TS* Bulk_in transfer (EP2) EP2_EMPTY Interrupt Request Signal DTC Activation DMAC Activation x x x x USBINTN1 Register IFR0 Bit 0 1 2 3 4 Description EP0i transfer complete EP0i transfer request EP0o receive complete Setup command receive complete EP2 FIFO empty USBINTN2 or x USBINTN3 USBINTN2 or x USBINTN3 USBINTN2 or x USBINTN3 USBINTN2 or x USBINTN3 USBINTN2 or x USBINTN3 USBINTN2 or x USBINTN3 USBINTN2 or x USBINTN3 USBINTN2 or x USBINTN3 USBINTN2 or x USBINTN3 USBINTN2 or x USBINTN3 USBINTN2 or x USBINTN3 x -- 5 6 Bulk_out transfer (EP1) Status Status EP2_TR EP1_FULL EP2 transfer request EP1 FIFO Full x USBINTN0 7 IFR1 0 BRST VBUSF Bus reset USB disconnection detection EP3 transfer complete EP3 transfer request x x 1 2 3 4 5 6 7 Interrupt_in EP3_TS transfer (EP3) EP3_TR Status -- VBUSMN Reserved x x x -- VBUS connection -- status -- -- Rev.1.00 Jun. 07, 2006 Page 786 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) Interrupt Request Signal Register IFR2 Bit 0 1 2 3 4 Transfer Mode Status Interrupt Source SETI SETC Description Set_Interface command detection Set_Configuration command detection Endpoint information load end Suspend/resume detection DTC DMAC Activation Activation x x -- x x USBINTN2 or x USBINTN3 USBINTN2 or x USBINTN3 -- -- -- Status Reserved CFDN SURSF USBINTN2 or x USBINTN3 USBINTN2, x USBINTN3, or RESUME -- -- x -- 5 6 7 -- SURSS Reserved Suspend/resume status -- x -- Note: * EP0 interrupts must be assigned to the same interrupt request signal. * USBINTN0 signal DMAC start interrupt signal only EP1. See section 16.8, DMA Transfer. * USBINTN1 signal DMAC start interrupt signal only EP1. See section 16.8, DMA Transfer. * USBINTN2 signal The USBINTN2 signal requests interrupt sources for which the corresponding bits in interrupt select registers 0 to 2 (ISR0 to ISR2) are cleared to 0. The USBINTN2 is driven low if a corresponding bit in the interrupt flag register is set to 1. * USBINTN3 signal The USBINTN3 signal requests interrupt sources for which the corresponding bits in interrupt select registers 0 to 2 (ISR0 to ISR2) are cleared to 0. The USBINTN3 is driven low if a corresponding bit in the interrupt flag register is set to 1. * RESUME signal The RESUME signal is a resume interrupt signal for canceling software standby mode. The RESUME signal is driven low at the transition to the resume state for canceling software standby mode. Rev.1.00 Jun. 07, 2006 Page 787 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) 16.5 16.5.1 Operation Cable Connection USB function Cable disconnected VBUS pin = 0 V UDC core reset Application USB module interrupt setting As soon as preparations are completed, enable D+ pull-up in general output port Initial settings USB cable connection No General output port D+ pull-up enabled? Yes Interrupt request IFR1.VBUSF = 1 USB bus connection interrupt Clear VBUSF flag (IFR1.VBUSF) UDC core reset release Firmware preparations for start of USB communication Bus reset reception IFR0.BRST = 1 Bus reset interrupt Interrupt request Clear bus reset flag (IFR0.BRST) Wait for setup command reception complete interrupt Clear FIFOs (EP0, EP1, EP2, EP3) Wait for setup command reception complete interrupt Figure 16.2 Cable Connection Operation The above flowchart shows the operation in the case of in section 16.9, Example of USB External Circuitry. In applications that do not require USB cable connection to be detected, processing by the USB bus connection interrupt is not necessary. Preparations should be made with the bus-reset interrupt. Rev.1.00 Jun. 07, 2006 Page 788 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) 16.5.2 Cable Disconnection USB function Cable connected VBUS pin = 1 Application USB cable disconnection VBUS pin = 0 UDC core reset End Figure 16.3 Cable Disconnection Operation The above flowchart shows the operation in section 16.9, Example of USB External Circuitry. Rev.1.00 Jun. 07, 2006 Page 789 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) 16.5.3 (1) Suspend and Resume Operations Suspend Operation If the USB bus enters the suspend state from the non-suspend state, perform the operation as shown in figure 16.4. USB function USB cable connected Application Clear SURSF in IFR2 to 0 Bus idle of 3 ms or more occurs Check if SURSS in IFR2 is set to 1 Suspend/resume interrupt occurs (IFR2/SURSF = 1) RESUME Remote wakeup enabled? (CTLR/RWUPS = 1?) No Yes Check remote-wakeup function enabled Check remote-wakeup function disabled System needs to enter power-down mode? Yes No Need to enter software standby mode? Yes Clear SURSE in IER2 to 0 No Set SURSE in IER2 to 1 Set SSRSME in IER2 to 1 Clear SSRSME in IER2 to 0 Enter software standby mode USB module stop Wait for suspend/ resume interrupt Figure 16.4 Suspend Operation Rev.1.00 Jun. 07, 2006 Page 790 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) (2) Resume Operation from Up-Stream If the USB bus enters the non-suspend state from the suspend state by resume signal output from up-stream, perform the operation as shown in figure 16.5. USB function USB cable connected USB bus in suspend state Application Resume interrupts is requested from the up-stream. Suspend/resume interrupt occurs. (IFR2/SURSF = 1) RESUME Yes Software standby mode ? No Cancel software standby mode Oscillation stabilization time has passed? No Yes USB module stopped? Yes Start USB operating clock oscillation Cancel USB module stop No Clear SURSF in IFR2 to 0 Check if SURSS in IFR2 is cleared to 0 Set SURSE in IER2 to 1 Clear SSRSME in IER2 to 0 Return to normal state Figure 16.5 Resume Operation from Up-Stream Rev.1.00 Jun. 07, 2006 Page 791 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) (3) Transition from Suspend State to Software Standby Mode and Canceling Software Standby Mode If the USB bus enters from the suspend state to software standby mode, perform the operation as shown in figure 16.6. When canceling software standby mode, ensure enough time for the system clock oscillation to be settled. Transition from suspend state to software standby mode (1) Detect that USB bus is in suspend state (8) Canceling software standby mode Detect that USB bus is in resume state (2) Set SURSF in IFR2 to 1 (9) RESUME interrupt (3) USBINTN interrupt (10) Cancel software standby mode Wait for system clock oscillation to be settled (4) Clear SURSF in IFR2 to 0 Check if SURSS in IFR2 is set to 1 (11) Clear SURSF in IER2 to 0 Set SSRSME in IER2 to 1 (12) Shift to software standby mode (execute SLEEP instruction) Clear SURSF in IFR2 to 0 Check if SURSS in IFR2 is cleared to 0 (5) Set SURSF in IER2 to 1 Clear SSRSME in IER2 to 0 (6) USB communications can be resumed through USB registers (7) Stop all clocks of LSI Denotation of figures : Operation by firmware setting : Automatic operation by LSI hardware Figure 16.6 Flow of Transition to and Canceling Software Standby Mode Rev.1.00 Jun. 07, 2006 Page 792 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) (1) USB bus state Normal (3) USBINTN interrupt Suspend (8) Resume normal SURSF (2) (4) (11) SURSS (4) SSRSME = 1 (5) (11) (12) RESUME interrupt (9) Software standby (6) (10) Oscillator USB dedicated clock (cku) Module clock (p) (7) (7) Software standby Oscillation settling time Figure 16.7 Timing of Transition to and Canceling Software Standby Mode Rev.1.00 Jun. 07, 2006 Page 793 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) (4) Remote-Wakeup Operation If the USB bus enters the non-suspend (resume) state from the suspend state by the remotewakeup signal output from this function, perform the operation as shown in figure 16.8. USB function USB cable connected USB bus in suspend state Application Remote wakeup enabled? (CTLR/RWUPS = 1?) No Yes Bus wakeup source generated Wait for resume from up-stream Yes Cancel software standby mode Software standby mode ? No Oscillation stabilization time has passed? No Yes USB module stopped? Yes Start USB operating clock oscillation Resume output signal Suspend/resume interrupt occurs. (IFR2/SURSF = 1) Cancel USB module stop No Remote wakeup execution (CTLR/RSME= 1) RESUME Clear SURSF in IFR2 to 0 Check if SURSS in IFR2 is cleared to 0 Return to normal state Figure 16.8 Remote-Wakeup Rev.1.00 Jun. 07, 2006 Page 794 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) 16.5.4 Control Transfer Control transfer consists of three stages: setup, data (not always included), and status (figure 16.9). The data stage comprises a number of bus transactions. Operation flowcharts for each stage are shown below. Setup stage Control-in SETUP(0) DATA0 Data stage IN(1) DATA1 Status stage ... IN(0/1) DATA0/1 IN(0) DATA0 OUT(1) DATA1 Control-out SETUP(0) DATA0 OUT(1) DATA1 OUT(0) DATA0 ... OUT(0/1) DATA0/1 IN(1) DATA1 No data SETUP(0) DATA0 IN(1) DATA1 Figure 16.9 Transfer Stages in Control Transfer Rev.1.00 Jun. 07, 2006 Page 795 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) (1) Setup Stage USB function SETUP token reception Application Receive 8-byte command data in EP0s Command to be processed by application? Yes Set setup command reception complete flag (IFR0.SETUP TS = 1) No Automatic processing by this module Interrupt request Clear SETUP TS flag (IFR0.SETUP TS = 0) Clear EP0i FIFO (FCLR.EP0iCLR = 1) Clear EP0o FIFO (FCLR.EP0oCLR = 1) To data stage Read 8-byte data from EP0s Decode command data Determine data stage direction*1 Write 1 to EP0s read complete bit (TRG.EP0s RDFN = 1) *2 To control-in data stage To control-out data stage Notes: 1. In the setup stage, the application analyzes command data from the host requiring processing by the application, and determines the subsequent processing (for example, data stage direction, etc.). 2. When the transfer direction is control-out, the EP0i transfer request interrupt required in the status stage should be enabled here. When the transfer direction is control-in, this interrupt is not required and should be disabled. Figure 16.10 Setup Stage Operation Rev.1.00 Jun. 07, 2006 Page 796 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) (2) Data Stage (Control-In) USB function IN token reception Application From setup stage 1 written to TRG.EP0s RDFN? Yes Valid data in EP0i FIFO? Yes Data transmission to host ACK Set EP0i transmission complete flag (IFR0.EP0i TS = 1) No NACK Write data to EP0i data register (EPDR0i) No NACK Write 1 to EP0i packet enable bit (TRG.EP0i PKTE = 1) Interrupt request Clear EP0i transmission complete flag (IFR0.EP0i TS = 0) Write data to EP0i data register (EPDR0i) Write 1 to EP0i packet enable bit (TRG.EP0i PKTE = 1) Figure 16.11 Data Stage (Control-In) Operation The application first analyzes command data from the host in the setup stage, and determines the subsequent data stage direction. If the result of command data analysis is that the data stage is intransfer, one packet of data to be sent to the host is written to the FIFO. If there is more data to be sent, this data is written to the FIFO after the data written first has been sent to the host (EP0iTS bit in IFR0 = 1). The end of the data stage is identified when the host transmits an OUT token and the status stage is entered. Note: If the size of the data transmitted by the function is smaller than the data size requested by the host, the function indicates the end of the data stage by returning to the host a packet shorter than the maximum packet size. If the size of the data transmitted by the function is an integral multiple of the maximum packet size, the function indicates the end of the data stage by transmitting a zero-length packet. Rev.1.00 Jun. 07, 2006 Page 797 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) (3) Data Stage (Control-Out) USB function OUT token reception Application 1 written to TRG.EP0s RDFN? Yes No NACK Data reception from host ACK Set EP0o reception complete flag (IFR0.EP0o TS = 1) Interrupt request Clear EP0o reception complete flag (IFR0.EP0o TS = 0) Read data from EP0o receive data size register (EPSZ0o) No NACK OUT token reception 1 written to TRG.EP0o RDFN? Yes Read data from EP0o data register (EPDR0o) Write 1 to EP0o read complete bit (TRG.EP0o RDFN = 1) Figure 16.12 Data Stage (Control-Out) Operation The application first analyzes command data from the host in the setup stage, and determines the subsequent data stage direction. If the result of command data analysis is that the data stage is outtransfer, the application waits for data from the host, and after data is received (EP0oTS bit in IFR0 = 1), reads data from the FIFO. Next, the application writes 1 to the EP0o read complete bit, empties the receive FIFO, and waits for reception of the next data. The end of the data stage is identified when the host transmits an IN token and the status stage is entered. Rev.1.00 Jun. 07, 2006 Page 798 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) (4) Status Stage (Control-In) USB function OUT token reception Application 0-byte reception from host ACK Set EP0o reception complete flag (IFR0.EP0o TS = 1) Interrupt request Clear EP0o reception complete flag (IFR0.EP0o TS = 0) Write 1 to EP0o read complete bit (TRG.EP0o RDFN = 1) End of control transfer End of control transfer Figure 16.13 Status Stage (Control-In) Operation The control-in status stage starts with an OUT token from the host. The application receives 0byte data from the host, and ends control transfer. Rev.1.00 Jun. 07, 2006 Page 799 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) (5) Status Stage (Control-Out) USB function IN token reception Application Valid data in EP0i FIFO? Yes 0-byte transmission to host ACK Set EP0i transmission complete flag (IFR0.EP0i TS = 1) No NACK Interrupt request Clear EP0i transfer request flag (IFR0.EP0i TR = 0) Write 1 to EP0i packet enable bit (TRG.EP0i PKTE = 1) Interrupt request Clear EP0i transmission complete flag (IFR0.EP0i TS = 0) End of control transfer End of control transfer Figure 16.14 Status Stage (Control-Out) Operation The control-out status stage starts with an IN token from the host. When an IN-token is received at the start of the status stage, there is not yet any data in the EP0i FIFO, and so an EP0i transfer request interrupt is generated. The application recognizes from this interrupt that the status stage has started. Next, in order to transmit 0-byte data to the host, 1 is written to the EP0i packet enable bit but no data is written to the EP0i FIFO. As a result, the next IN token causes 0-byte data to be transmitted to the host, and control transfer ends. After the application has finished all processing relating to the data stage, 1 should be written to the EP0i packet enable bit. Rev.1.00 Jun. 07, 2006 Page 800 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) 16.5.5 EP1 Bulk-Out Transfer (Dual FIFOs) USB function OUT token reception Application Space in EP1 FIFO? Yes Data reception from host ACK Set EP1 FIFO full status (IFR0.EP1 FULL = 1) No NACK Read EP1 receive data size register (EPSZ1) Interrupt request Read data from EP1 data register (EPDR1) Write 1 to EP1 read complete bit (TRG.EP1 RDFN = 1) Both EP1 FIFOs empty? Yes Clear EP1 FIFO full status (IFR0.EP1 FULL = 0) No Interrupt request Figure 16.15 EP1 Bulk-Out Transfer Operation EP1 has two 64-byte FIFOs, but the user can receive data and read receive data without being aware of this dual-FIFO configuration. When one FIFO is full after reception is completed, the EP1FULL bit in IFR0 is set. After the first receive operation into one of the FIFOs when both FIFOs are empty, the other FIFO is empty, and so the next packet can be received immediately. When both FIFOs are full, NACK is returned to the host automatically. When reading of the receive data is completed following data reception, 1 is written to the EP1RDFN bit in TRG. This operation empties the FIFO that has just been read, and makes it ready to receive the next packet. Rev.1.00 Jun. 07, 2006 Page 801 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) 16.5.6 EP2 Bulk-In Transfer (Dual FIFOs) USB function IN token reception Application Valid data in EP2 FIFO? Yes Data transmission to host ACK No NACK Interrupt request Clear EP2 transfer request flag (IFR0.EP2 TR = 0) Enable EP2 FIFO empty interrupt (IER0.EP2 EMPTY = 1) Space in EP2 FIFO? No Yes Set EP2 empty status (IFR0.EP2 EMPTY = 1) Interrupt request IER0.EP2 EMPTY interrupt Clear EP2 empty status (IFR0.EP2 EMPTY = 0) Write one packet of data to EP2 data register (EPDR2) Write 1 to EP2 packet enable bit (TRG.EP2 PKTE = 1) Figure 16.16 EP2 Bulk-In Transfer Operation EP2 has two 64-byte FIFOs, but the user can transmit data and write transmit data without being aware of this dual-FIFO configuration. However, one data write is performed for one FIFO. For example, even if both FIFOs are empty, it is not possible to perform EP2PKTE at one time after consecutively writing 128 bytes of data. EP2PKTE must be performed for each 64-byte write. When performing bulk-in transfer, as there is no valid data in the FIFOs on reception of the first IN token, an EP2TR bit interrupt in IFR0 is requested. With this interrupt, 1 is written to the EP2EMPTY bit in IER0, and the EP2 FIFO empty interrupt is enabled. At first, both EP2 FIFOs are empty, and so an EP2 FIFO empty interrupt is generated immediately. Rev.1.00 Jun. 07, 2006 Page 802 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) The data to be transmitted is written to the data register using this interrupt. After the first transmit data write for one FIFO, the other FIFO is empty, and so the next transmit data can be written to the other FIFO immediately. When both FIFOs are full, EP2 EMPTY is cleared to 0. If at least one FIFO is empty, the EP2EMPTY bit in IFR0 is set to 1. When ACK is returned from the host after data transmission is completed, the FIFO used in the data transmission becomes empty. If the other FIFO contains valid transmit data at this time, transmission can be continued. When transmission of all data has been completed, write 0 to the EP2EMPTY bit in IER0 and disable interrupt requests. Rev.1.00 Jun. 07, 2006 Page 803 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) 16.5.7 EP3 Interrupt-In Transfer USB function Application Is there data for transmission to host? IN token reception Yes Write data to EP3 data register (EPDR3) Valid data in EP3FIFO? Yes Data transmission to host ACK Set EP3 transmission complete flag (IFR1.EP3 TS = 1) Interrupt request Clear EP3 transmission complete flag (IFR1.EP3 TS = 0) No NACK Write 1 to EP3 packet enable bit (TRG.EP3 PKTE = 1) No Is there data for transmission to host? Yes Write data to EP3 data register (EPDR3) Write 1 to EP3 packet enable bit (TRG.EP3 PKTE = 1) No Note: This flowchart shows just one example of interrupt transfer processing. Other possibilities include an operation flow in which, if there is data to be transferred, the EP3 DE bit in the data status register is referenced to confirm that the FIFO is empty, and then data is written to the FIFO. Figure 16.17 Operation of EP3 Interrupt-In Transfer Rev.1.00 Jun. 07, 2006 Page 804 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) 16.6 Processing of USB Standard Commands and Class/Vendor Commands Processing of Commands Transmitted by Control Transfer 16.6.1 A command transmitted from the host by control transfer may require decoding and execution of command processing on the application side. Whether command decoding is required on the application side is indicated in table 16.7 below. Table 16.7 Command Decoding on Application Side Decoding not Necessary on Application Side Clear Feature Get Configuration Get Interface Get Status Set Address Set Configuration Set Feature Set Interface Decoding Necessary on Application Side Get Descriptor Class/Vendor command Set Descriptor Sync Frame If decoding is not necessary on the application side, command decoding and data stage and status stage processing are performed automatically. No processing is necessary by the user. An interrupt is not generated in this case. If decoding is necessary on the application side, this module stores the command in the EP0s FIFO. After reception is completed successfully, the IFR0/SETUP TS flag is set and an interrupt request is generated. In the interrupt routine, eight bytes of data must be read from the EP0s data register (EPDR0s) and decoded by firmware. The necessary data stage and status stage processing should then be carried out according to the result of the decoding operation. Rev.1.00 Jun. 07, 2006 Page 805 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) 16.7 16.7.1 Stall Operations Overview This section describes stall operations in this module. There are two cases in which the USB function module stall function is used: * When the application forcibly stalls an endpoint for some reason * When a stall is performed automatically within the USB function module due to a USB specification violation The USB function module has internal status bits that hold the status (stall or non-stall) of each endpoint. When a transaction is sent from the host, the module references these internal status bits and determines whether to return a stall to the host. These bits cannot be cleared by the application; they must be cleared with a Clear Feature command from the host. However, the internal status bit for EP0 is automatically cleared only when the setup command is received. 16.7.2 Forcible Stall by Application The application uses the EPSTL register to issue a stall request for the USB function module. When the application wishes to stall a specific endpoint, it sets the corresponding bit in EPSTL (11 in figure 16.18). The internal status bits are not changed at this time. When a transaction is sent from the host for the endpoint for which the EPSTL bit was set, the USB function module references the internal status bit, and if this is not set, references the corresponding bit in EPSTL (1-2 in figure 16.18). If the corresponding bit in EPSTL is set, the USB function module sets the internal status bit and returns a stall handshake to the host (1-3 in figure 16.18). If the corresponding bit in EPSTL is not set, the internal status bit is not changed and the transaction is accepted. Once an internal status bit is set, it remains set until cleared by a Clear Feature command from the host, without regard to the EPSTL register. Even after a bit is cleared by the Clear Feature command (3-1 in figure 16.18), the USB function module continues to return a stall handshake while the bit in EPSTL is set, since the internal status bit is set each time a transaction is executed for the corresponding endpoint (1-2 in figure 16.18). To clear a stall, therefore, it is necessary for the corresponding bit in EPSTL to be cleared by the application, and also for the internal status bit to be cleared with a Clear Feature command (2-1, 2-2, and 2-3 in figure 16.18). Rev.1.00 Jun. 07, 2006 Page 806 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) (1) Transition from normal operation to stall (1-1) USB Internal status bit 0 EPSTL 01 1. 1 written to EPSTL by application (1-2) Reference Transaction request Internal status bit 0 EPSTL 1 1. IN/OUT token received from host 2. EPSTL referenced (1-3) Stall STALL handshake Internal status bit 01 To (2-1) or (3-1) (2) When Clear Feature is sent after EPSTL is cleared (2-1) Transaction request Internal status bit 1 EPSTL 10 EPSTL 1 1. 1 set in EPSTL 2. Internal status bit set to 1 3. Transmission of STALL handshake 1. EPSTL cleared to 0 by application 2. IN/OUT token received from host 3. Internal status bit already set to 1 4. EPSTL not referenced 5. Internal status bit not changed (2-2) STALL handshake Internal status bit 1 EPSTL 0 1. Transmission of STALL handshake (2-3) Clear Feature command Internal status bit 10 EPSTL 0 1. Internal status bit cleared to 0 Normal status restored (3) When Clear Feature is sent before EPSTL is cleared to 0 (3-1) Clear Feature command Internal status bit 10 To (1-2) EPSTL 1 1. Internal status bit cleared to 0 2. EPSTL not changed Figure 16.18 Forcible Stall by Application Rev.1.00 Jun. 07, 2006 Page 807 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) 16.7.3 Automatic Stall by USB Function Module When a stall setting is made with the Set Feature command, or in the event of a USB specification violation, the USB function module automatically sets the internal status bit for the relevant endpoint without regard to the EPSTL register, and returns a stall handshake (1-1 in figure 16.19). Once an internal status bit is set, it remains set until cleared by a Clear Feature command from the host, without regard to the EPSTL register. After a bit is cleared by the Clear Feature command, EPSTL is referenced (3-1 in figure 16.19). The USB function module continues to return a stall handshake while the internal status bit is set, since the internal status bit is set even if a transaction is executed for the corresponding endpoint (2-1 and 2-2 in figure 16.19). To clear a stall, therefore, the internal status bit must be cleared with a Clear Feature command (3-1 in figure 16.19). If set by the application, EPSTL should also be cleared (2-1 in figure 16.19). (1) Transition from normal operation to stall (1-1) STALL handshake Internal status bit 01 To (2-1) or (3-1) EPSTL 0 1. In case of USB specification violation, etc., USB function module stalls endpoint automatically (2) When transaction is performed when internal status bit is set, and Clear Feature is sent (2-1) Transaction request Internal status bit 1 EPSTL 0 1. EPSTL cleared to 0 by application 2. IN/OUT token received from host 3. Internal status bit already set to 1 4. EPSTL not referenced 5. Internal status bit not changed 1. Transmission of STALL handshake (2-2) STALL handshake Internal status bit 1 EPSTL 0 Stall status maintained (3) When Clear Feature is sent before transaction is performed (3-1) Clear Feature command Internal status bit 10 EPSTL 0 1. Internal status bit cleared to 0 2. EPSTL not changed Normal status restored Figure 16.19 Automatic Stall by USB Function Module Rev.1.00 Jun. 07, 2006 Page 808 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) 16.8 16.8.1 DMA Transfer Overview DMA transfer can be performed for endpoints 1 and 2 in this module. Note that word or longword data cannot be transferred. When endpoint 1 holds at least one byte of valid receive data, a DMA request for endpoint 1 is generated. When endpoint 2 holds no valid data, a DMA request for endpoint 2 is generated. If the DMA transfer is enabled by setting the EP1DMAE bit in the DMA transfer setting register to 1, zero-length data reception at endpoint 1 is ignored. When the DMA transfer is enabled, the RDFN bit for EP1 and PKTE bit for EP2 do not need to be set to 1 in TRG (note that the PKTE bit must be set to 1 when the transfer data is less than the maximum number of bytes). When all the data received at EP1 is read, the FIFO automatically enters the EMPTY state. When the maximum number of bytes (64 bytes) are written to the EP2 FIFO, the FIFO automatically enters the FULL state, and the data in the FIFO can be transmitted (see figures 16.20 and 16.21). 16.8.2 DMA Transfer for Endpoint 1 When the data received at EP1 is transferred by the DMAC, the USB function module automatically performs the same processing as writing 1 to the RDFN bit in TRG if the currently selected FIFO becomes empty. Accordingly, in DMA transfer, do not write 1 to the RDFN bit in TRG. If the user writes 1 to the RDFN bit in DMA transfer, correct operation cannot be guaranteed. Figure 16.20 shows an example of receiving 150 bytes of data from the host. In this case, internal processing which is the same as writing 1 to the RDFN bit in TRG is automatically performed three times. This internal processing is performed when the currently selected data FIFO becomes empty. Accordingly, this processing is automatically performed both when 64-byte data is sent and when data less than 64 bytes is sent. 64 bytes 64 bytes 22 bytes RDFN (Automatically performed) RDFN RDFN (Automatically (Automatically performed) performed) Figure 16.20 RDFN Bit Operation for EP1 Rev.1.00 Jun. 07, 2006 Page 809 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) 16.8.3 DMA Transfer for Endpoint 2 When the transmit data at EP2 is transferred by the DMAC, the USB function module automatically performs the same processing as writing 1 to the PKTE bit in TRG if the currently selected FIFO (64 bytes) becomes full. Accordingly, to transfer data of a multiple of 64 bytes, the user need not write 1 to the PKTE bit. To transfer data of less than 64 bytes, the user must write 1 to the PKTE bit using the DMA transfer end interrupt of the on-chip DMAC. If the user writes 1 to the PKTE bit when the maximum number of bytes (64 bytes) are transferred, correct operation cannot be guaranteed. Figure 16.21 shows an example for transmitting 150 bytes of data to the host. In this case, internal processing which is the same as writing 1 to the PKTE bit in TRG is automatically performed twice. This internal processing is performed when the currently selected data FIFO becomes full. Accordingly, this processing is automatically performed only when 64-byte data is sent. When the last 22 bytes are sent, the internal processing for writing 1 to the PKTE bit is not performed, and the user must write 1 to the PKTE bit by software. In this case, the application has no more data to transfer but the USB function module continues to output DMA requests for EP2 as long as the FIFO has an empty space. When all data has been transferred, write 0 to the EP2DMAE bit in DMAR to cancel DMA requests for EP2. 64 bytes 64 bytes 22 bytes PKTE (Automatically performed) PKTE is PKTE (Automatically not performed performed) Execute by DMA transfer end interrupt (user) Figure 16.21 PKTE Bit Operation for EP2 Rev.1.00 Jun. 07, 2006 Page 810 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) 16.9 Example of USB External Circuitry 1. USB Transceiver This module supports the on-chip transceiver only, not the external transceiver. 2. D+ Pull-Up Control The general output port (PM4) is used for D+ pull-up control pin. The PM4 pin is driven high by the PULLUP_E bit of DMA when the USB cable VBUS is connected. Thus, USB host/hub connection notification (D+ pill-up) is enabled. 3. Detection of USB Cable Connection/Disconnection As USB states, etc., are managed by hardware in this module, a VBUS signal that recognizes connection/disconnection is necessary. The power supply signal (VBUS) in the USB cable is used for this purpose. However, if the cable is connected to the USB host/hub when the function (system installing this LSI) power is off, a voltage (5 V) will be applied from the USB host/hub. Therefore, an IC (such as an HD74LV1G08A or 2G08A) that allows voltage application when the system power is off should be connected externally. USB Vcc PULLUP_E On-chip transceiver Vcc (3.3 V) DrVCC (3.3 V) PM4 VBUS*3 USD+ USD- DrVSS Vss Vcc (3.3 V) Regulator*1 Vcc *2 External pull-up control circuit supporting full-speed Notes: 1.5 k VBUS (5 V) D+ D- GND USB connector 1. Reduce voltage to the operating voltage of this LSI (3.3 V). 2. To protect this LSI from being damaged, use the IC (such as HD74LV-A Series) which can be applied voltage even when the system power is turned off. 3. Prevent noise from the VBUS pin while the USB is performing communication. Figure 16.22 Example of Circuitry in Bus Power Mode Rev.1.00 Jun. 07, 2006 Page 811 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) USB Vcc PULLUP_E On-chip transceiver Vcc (3.3 V) DrVCC (3.3 V) PM4 VBUS*2 USD+ USD- DrVSS Vss Vcc 3.3 V *1 Vcc *1 External pull-up control circuit supporting full-speed 1.5 k VBUS (5 V) D+ D- GND USB connector Notes: 1. To protect this LSI from being damaged, use the IC (such as HD74LV-A Series) which can be applied voltage even when the system power is turned off. 2. Prevent noise from the VBUS pin while the USB is performing communication. Figure 16.23 Example of Circuitry in Self Power Mode Rev.1.00 Jun. 07, 2006 Page 812 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) 16.10 Usage Notes 16.10.1 Receiving Setup Data Note the following for EPDR0s that receives 8-byte setup data: 1. As a latest setup command must be received in high priority, the write from the USB bus takes priority over the read from the CPU. If the next setup command reception is started while the CPU is reading data after the data is received, the read from the CPU is forcibly terminated. Therefore, the data read after reception is started becomes invalid. 2. EPDR0s must always be read in 8-byte units. If the read is terminated at a midpoint, the data received at the next setup cannot be read correctly. 16.10.2 Clearing the FIFO If a USB cable is disconnected during data transfer, the data being received or transmitted may remain in the FIFO. When disconnecting a USB cable, clear the FIFO. While a FIFO is transferring data, it must not be cleared. 16.10.3 Overreading and Overwriting the Data Registers Note the following when reading or writing to a data register of this module. (1) Receive data registers The receive data registers must not be read exceeding the valid amount of receive data, that is, the number of bytes indicated by the receive data size register. Even for EPDR1 which has double FIFO buffers, the maximum data to be read at one time is 64 bytes. After the data is read from the current valid FIFO buffer, be sure to write 1 to EP1RDFN in TRG, which switches the valid buffer, updates the receive data size to the new number of bytes, and enables the next data to be received. (2) Transmit data registers The transmit data registers must not be written to exceeding the maximum packet size. Even for EPDR2 which has double FIFO buffers, write data within the maximum packet size at one time. After the data is written, write 1 to PKTE in TRG to switch the valid buffer and enable the next data to be written. Data must not be continuously written to the two FIFO buffers. Rev.1.00 Jun. 07, 2006 Page 813 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) 16.10.4 Assigning Interrupt Sources to EP0 The EP0-related interrupt sources indicated by the interrupt source bits (bits 0 to 3) in IFR0 must be assigned to the same interrupt signal with ISR0. The other interrupt sources have no limitations. 16.10.5 Clearing the FIFO When DMA Transfer is Enabled The endpoint 1 data register (EPDR1) cannot be cleared when DMA transfer for endpoint 1 is enabled (EP1 DMAE in DMAR = 1). Cancel DMA transfer before clearing the register. 16.10.6 Notes on TR Interrupt Note the following when using the transfer request interrupt (TR interrupt) for IN transfer to EP0i, EP2, or EP3. The TR interrupt flag is set if the FIFO for the target EP has no data when the IN token is sent from the USB host. However, at the timing shown in figure 16.24, multiple TR interrupts occur successively. Take appropriate measures against malfunction in such a case. Note: This module determines whether to return NAKC if the FIFO of the target EP has no data when receiving the IN token, but the TR interrupt flag is set after a NAKC handshake is sent. If the next IN token is sent before PKTE of TRG is written to, the TR interrupt flag is set again. TR interrupt routine CPU Clear Writes TRG. TR flag transmit data PKTE TR interrupt routine Host IN token IN token IN token USB Determines whether to return NACK NACK Sets TR flag Determines whether to return NACK NACK Transmits data ACK Sets TR flag (Sets the flag again) Figure 16.24 TR Interrupt Flag Set Timing Rev.1.00 Jun. 07, 2006 Page 814 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) 16.10.7 Restrictions on Peripheral Module Clock (P) Operating Frequency Specify the peripheral module clock (P) for the USB at 14 MHz or more. To set the USB dedicated clock (cku) at 48 MHz, specify the peripheral module clock (P) as shown in table 16.8. Operation cannot be guaranteed if any frequency other than in the following table is specified. Table 16.8 Selection of Peripheral Clock (P) when USB is Connected MD_CLK 0 1 EXTAL Input Clock Frequency 12 MHz 16 MHz USB Dedicated Clock (cku: 48 MHz) EXTAL x 4 EXTAL x 3 P EXTAL x 2 (24 MHz) EXTAL x 1 (16 MHz) EXTAL x 2 (32 MHz) Rev.1.00 Jun. 07, 2006 Page 815 of 1102 REJ09B0294-0100 Section 16 USB Function Module (USB) Rev.1.00 Jun. 07, 2006 Page 816 of 1102 REJ09B0294-0100 Section 17 I2C Bus Interface 2 (IIC2) Section 17 I C Bus Interface 2 (IIC2) This LSI has a two-channel I C bus interface. The I2C bus interface conforms to and provides a subset of the Philips I2C bus (inter-IC bus) interface functions. The register configuration that controls the I2C bus differs partly from the Philips configuration, however. Figure 17.1 shows the block diagram of the I2C bus interface 2. Figure 17.2 shows an example of I/O pin connections to external circuits. 2 2 17.1 Features * Continuous transmission/reception Since the shift register, transmit data register, and receive data register are independent from each other, the continuous transmission/reception can be performed. * Start and stop conditions generated automatically in master mode * Selection of acknowledge output levels when receiving * Automatic loading of acknowledge bit when transmitting * Bit synchronization/wait function In master mode, the state of SCL is monitored per bit, and the timing is synchronized automatically. If transmission or reception is not yet possible, drive the SCL signal low until preparations are completed * Six interrupt sources Transmit-data-empty (including slave-address match), transmit-end, receive-data-full (including slave-address match), arbitration lost, NACK detection, and stop condition detection * Direct bus drive Two pins, the SCL and SDA pins function as NMOS open-drain outputs. Rev.1.00 Jun. 07, 2006 Page 817 of 1102 REJ09B0294-0100 Section 17 I2C Bus Interface 2 (IIC2) Transfer clock generator SCL Output control Transmission/ reception control circuit ICCRA ICCRB ICMR Noise canceler ICDRT SAR Internal data bus SDA Output control ICDRS Noise canceler Address comparator ICDRR Bus state decision circuit Arbitration decision circuit ICEIR Interrupt generator ICSR [Legend] ICCRA: ICCRB: ICMR: ICSR: ICIER: ICDRT: ICDRR: ICDRS: SAR: bus control register A I2C bus control register B I2C mode register I2C status register I2C interrupt enable register I2C transmit data register I2C receive data register I2C bus shift register Slave address register I2C Interrupt request Figure 17.1 Block Diagram of I C Bus Interface 2 2 Rev.1.00 Jun. 07, 2006 Page 818 of 1102 REJ09B0294-0100 Section 17 I2C Bus Interface 2 (IIC2) Vcc Vcc SCL in SCL out SCL SCL SDA in SDA out SDA SDA SCL SDA (Master) SCL in SCL out SCL in SCL out SDA in SDA out (Slave 1) SDA in SDA out (Slave 2) Figure 17.2 Connections to the External Circuit by the I/O Pins 17.2 Input/Output Pins 2 Table 17.1 shows the pin configuration of the I C bus interface 2. Table 17.1 Pin Configuration of the I C Bus Interface 2 Channel 0 Abbreviation SCL0 SDA0 1 SCL1 SDA1 I/O I/O I/O I/O I/O Function Channel 0 serial clock I/O pin Channel 0 serial data I/O pin Channel 1 serial clock I/O pin Channel 1 serial data I/O pin 2 Note: The pin symbols are represented as SCL and SDA; channel numbers are omitted in this manual. Rev.1.00 Jun. 07, 2006 Page 819 of 1102 REJ09B0294-0100 SCL SDA Section 17 I2C Bus Interface 2 (IIC2) 17.3 2 Register Descriptions The I C bus interface 2 has the following registers. Channel 0: * I C bus control register A_0 (ICCRA_0) 2 2 2 2 2 * I C bus control register B_0 (ICCRB_0) * I C bus mode register_0 (ICMR_0) * I C bus interrupt enable register_0 (ICIER_0) * I C bus status register_0 (ICSR_0) * Slave address register_0 (SAR_0) * I C bus transmit data register_0 (ICDRT_0) 2 2 2 * I C bus receive data register_0 (ICDRR_0) * I C bus shift register_0 (ICDRS_0) Channel 1: * I C bus control register A_1 (ICCRA_1) 2 2 2 2 2 * I C bus control register B_1 (ICCRB_1) * I C bus mode register_1 (ICMR_1) * I C bus interrupt enable register_1 (ICIER_1) * I C bus status register_1 (ICSR_1) * Slave address register_1 (SAR_1) * I C bus transmit data register_1 (ICDRT_1) 2 2 2 * I C bus receive data register_1 (ICDRR_1) * I C bus shift register_1 (ICDRS_1) Rev.1.00 Jun. 07, 2006 Page 820 of 1102 REJ09B0294-0100 Section 17 I2C Bus Interface 2 (IIC2) 17.3.1 I C Bus Control Register A (ICCRA) 2 2 ICCRA enables or disables I C bus interface, controls transmission or reception, and selects master or slave mode, transmission or reception, and transfer clock frequency in master mode. Bit Bit Name Initial Value R/W 7 ICE 0 R/W 6 RCVD 0 R/W 5 MST 0 R/W 4 TRS 0 R/W 3 CKS3 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Bit 7 Bit Name ICE Initial Value 0 R/W R/W Description I C Bus Interface Enable 0: This module is halted 1: This bit is enabled for transfer operations (SCL and SDA pins are bus drive state) 2 6 RCVD 0 R/W Reception Disable This bit enables or disables the next operation when TRS is 0 and ICDRR is read. 0: Enables next reception 1: Disables next reception 5 4 MST TRS 0 0 R/W R/W Master/Slave Select Transmit/Receive Select When arbitration is lost in master mode, MST and TRS are both reset by hardware, causing a transition to slave receive mode. Modification of the TRS bit should be made between transfer frames. Operating modes are described below according to MST and TRS combination. 00: Slave receive mode 01: Slave transmit mode 10: Master receive mode 11: Master transmit mode 3 2 1 0 CKS3 CKS2 CKS1 CKS0 0 0 0 0 R/W R/W R/W R/W Transfer Clock Select 3 to 0 These bits are valid only in master mode. Make setting according to the required transfer rate. For details on the transfer rate, see table 17.2. Rev.1.00 Jun. 07, 2006 Page 821 of 1102 REJ09B0294-0100 Section 17 I2C Bus Interface 2 (IIC2) Table 17.2 Transfer Rate Bit 3 CKS3 0 Bit 2 CKS2 0 Bit 1 CKS1 0 Bit 0 CKS0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Clock P/28 P/40 P/48 P/64 P/168 P/100 P/112 P/128 P/56 P/80 P/96 P/128 P/336 P/200 P/224 P/256 P = 8 MHz 286 kHz 200 kHz 167 kHz 125 kHz 47.6 kHz 80.0 kHz 71.4 kHz 62.5 kHz 143 kHz 100 kHz 83.3 kHz 62.5 kHz 23.8 kHz 40.0 kHz 35.7 kHz 31.3 kHz P = 10 MHz 357 kHz 250 kHz 208 kHz 156 kHz 59.5 kHz 100 kHz 89.3 kHz 78.1 kHz 179 kHz 125 kHz 104 kHz 78.1 kHz 29.8 kHz 50.0 kHz 44.6 kHz 39.1 kHz Transfer Rate P = 20 MHz 714 kHz 500 kHz 417 kHz 313 kHz 119 kHz 200 kHz 179 kHz 156 kHz 357 kHz 250 kHz 208 kHz 156 kHz 59.5 kHz 100 kHz 89.3 kHz 78.1 kHz P = 25 MHz 893 kHz 625 kHz 521 kHz 391 kHz 149 kHz 250 kHz 223 kHz 195 kHz 446 kHz 313 kHz 260 kHz 195 kHz 74.4 kHz 125 kHz 112 kHz 97.7 kHz P = 33 MHz 1179 kHz 825 kHz 688 kHz 516 kHz 196 kHz 330 kHz 295 kHz 258 kHz 589 kHz 413 kHz 344 kHz 258 kHz 98.2 kHz 165 kHz 147 kHz 129 kHz 17.3.2 I C Bus Control Register B (ICCRB) 2 ICCRB issues start/stop condition, manipulates the SDA pin, monitors the SCL pin, and controls 2 reset in the I C control module. Bit Bit Name Initial Value R/W 7 BBSY 0 R/W 6 SCP 1 R/W 5 SDAO 1 R 4 1 R/W 3 SCLO 1 R 2 1 1 IICRST 0 R/W 0 1 Rev.1.00 Jun. 07, 2006 Page 822 of 1102 REJ09B0294-0100 Section 17 I2C Bus Interface 2 (IIC2) Bit 7 Initial Bit Name Value BBSY 0 R/W R/W Description Bus Busy This bit indicates whether the I C bus is occupied or released and to issue start and stop conditions in master mode. This bit is set to 1 when the SDA level changes from high to low under the condition of SCL = high, assuming that the start condition has been issued. This bit is cleared to 0 when the SDA level changes from low to high under the condition of SDA = high, assuming that the stop condition has been issued. Follow this procedure also when re-transmitting a start condition. To issue a start or stop condition, use the MOV instruction. 2 6 SCP 1 R/W Start/Stop Condition Issue This bit controls the issuance of start or stop condition in master mode. To issue a start condition, write 1 to BBSY and 0 to SCP. A re-transmit start condition is issued in the same way. To issue a stop condition, write 0 to BBSY and 0 to SCP. This bit is always read as 1. If 1 is written, the data is not stored. 5 SDAO 1 R This bit monitors the output level of SDA. 0: When reading, the SDA pin outputs a low level 1: When reading the SDA pin outputs a high level 4 3 SCLO 1 1 R/W R Reserved The write value should always be 1. This bit monitors the SCL output level. When reading and SCLO is 1, the SCL pin outputs a high level. When reading and SCLO is 0, the SCL pin outputs a low level. 2 1 IICRST 1 0 R/W Reserved This bit is always read as 0. IIC Control Module Reset This bit reset the IIC control module except the I C registers. If hang-up occurs because of communication 2 failure during I C operation, by setting this bit to 1, the 2 0 1 Reserved This bit is always read as 1. Rev.1.00 Jun. 07, 2006 Page 823 of 1102 REJ09B0294-0100 Section 17 I2C Bus Interface 2 (IIC2) 17.3.3 I C Bus Mode Register (ICMR) 2 ICMR selects MSB first or LSB first, controls the master mode wait and selects the number of transfer bits. Bit Bit Name Initial Value R/W 7 0 R/W 6 WAIT 0 R/W 5 1 4 1 3 BCWP 1 R/W 2 BC2 0 R/W 1 BC1 0 R/W 0 BC0 0 R/W Bit 7 6 Bit Name WAIT Initial Value 0 0 R/W R/W R/W Description Reserved The write value should always be 0. Wait Insertion This bit selects whether to insert a wait after data transfer except for the acknowledge bit. When this bit is set to 1, after the falling of the clock for the last data bit, the low period is extended for two transfer clocks. When this bit is cleared to 0, data and the acknowledge bit are transferred consecutively with no waits inserted. The setting of this bit is invalid in slave mode. 5 4 3 BCWP 1 1 1 R/W Reserved These bits are always read as 1. BC Write Protect This bit controls the modification of the BC2 to BC0 bits. When modifying, this bit should be cleared to 0 and the MOV instruction should be used. 0: When writing, the values of BC2 to BC0 are set 1: When reading, 1 is always read When writing, the settings of BC2 to BC0 are invalid. Rev.1.00 Jun. 07, 2006 Page 824 of 1102 REJ09B0294-0100 Section 17 I2C Bus Interface 2 (IIC2) Bit 2 1 0 Bit Name BC2 BC1 BC0 Initial Value 0 0 0 R/W R/W R/W R/W Description Bit Counter 2 to 0 These bits specify the number of bits to be transferred next. The settings of these bits should be made during intervals between transfer frames. When setting these bits to a value other than 000, the setting should be made while the SCL line is low. The value return to 000 at the end of a data transfer including the acknowledge bit. 000: 9 001: 2 010: 3 011: 4 100: 5 101: 6 110: 7 111: 8 I C control module can be reset without setting the ports and initializing the registers. 2 17.3.4 I C Bus Interrupt Enable Register (ICIER) 2 ICIER enables or disables interrupt sources and the acknowledge bits, sets the acknowledge bits to be transferred, and confirms the acknowledge bit to be received. Bit Bit Name Initial Value R/W 7 TIE 0 R/W 6 TEIE 0 R/W 5 RIE 0 R/W 4 NAKIE 0 R/W 3 STIE 0 R/W 2 ACKE 0 R/W 1 ACKBR 0 R 0 ACKBT 0 R/W Rev.1.00 Jun. 07, 2006 Page 825 of 1102 REJ09B0294-0100 Section 17 I2C Bus Interface 2 (IIC2) Bit 7 Initial Bit Name Value TIE 0 R/W R/W Description Transmit Interrupt Enable When the TDRE bit in ICSR is set to 1, this bit enables or disables the transmit data empty interrupt (TXI) request. 0: Transmit data empty interrupt (TXI) request is disabled 1: Transmit data empty interrupt (TXI) request is enabled 6 TEIE 0 R/W Transmit End Interrupt Enable This bit enables or disables the transmit end interrupt (TEI) request at the rising of the ninth clock while the TDRE bit in ICSR is set to 1. The TEI request can be canceled by clearing the TEND bit or the TEIE bit to 0. 0: Transmit end interrupt (TEI) request is disabled 1: Transmit end interrupt (TEI) request is enabled 5 RIE 0 R/W Receive Interrupt Enable This bit enables or disables the receive full interrupt (RXI) request when receive data is transferred from ICDRS to ICDRR and the RDRF bit in ICSR is set to 1. The RXI request can be canceled by clearing the RDRF or RIE bit to 0. 0: Receive data full interrupt (RXI) request is disabled 1: Receive data full interrupt (RXI) request is enabled 4 NAKIE 0 R/W NACK Receive Interrupt Enable This bit enables or disables the NACK receive interrupt (NAKI) request when the NACKF and AL bits in ICSR are set to 1. The NAKI request can be canceled by clearing the NACKF or AL bit, or the NAKIE bit to 0. 0: NACK receive interrupt (NAKI) request is disabled 1: NACK receive interrupt (NAKI) request is enabled Rev.1.00 Jun. 07, 2006 Page 826 of 1102 REJ09B0294-0100 Section 17 I2C Bus Interface 2 (IIC2) Bit 3 Initial Bit Name Value STIE 0 R/W R/W Description Stop Condition Detection Interrupt Enable 0: Stop condition detection interrupt (STPI) request is disabled 1: Stop condition detection interrupt (STPI) request is enabled 2 ACKE 0 R/W Acknowledge Bit Decision Select 0: The value of the acknowledge bit is ignored and continuous transfer is performed 1: If the acknowledge bit is 1, continuous transfer is suspended 1 ACKBR 0 R Receive Acknowledge In transmit mode, this bit stores the acknowledge data that are returned by the receive device. This bit cannot be modified. 0: Receive acknowledge = 0 1: Receive acknowledge = 1 0 ACKBT 0 R/W Transmit Acknowledge In receive mode, this bit specifies the bit to be sent at the acknowledge timing. 0: 0 is sent at the acknowledge timing 1: 1 is sent at the acknowledge timing Rev.1.00 Jun. 07, 2006 Page 827 of 1102 REJ09B0294-0100 Section 17 I2C Bus Interface 2 (IIC2) 17.3.5 I C Bus Status Register (ICSR) 2 ICSR confirms the interrupt request flags and status. Bit Bit Name Initial Value R/W 7 TDRE 0 R/W 6 TEND 0 R/W 5 RDRF 0 R/W 4 NACKF 0 R/W 3 STOP 0 R/W 2 AL 0 R/W 1 AAS 0 R/W 0 ADZ 0 R/W Bit 7 Bit Name TDRE Initial Value 0 R/W R/W Description Transmit Data Register Empty [Setting condition] * When data is transferred from ICDRT to ICDRS and ICDRT becomes empty When 0 is written to this bit after reading TDRE = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) When data is written to ICDRT [Clearing conditions] * * 6 TEND 0 R/W Transmit End [Setting condition] * When the ninth clock of SCL rises while the TDRE flag is 1 When 0 is written to this bit after reading TEND = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) When data is written to ICDRT [Clearing conditions] * * Rev.1.00 Jun. 07, 2006 Page 828 of 1102 REJ09B0294-0100 Section 17 I2C Bus Interface 2 (IIC2) Bit 5 Bit Name RDRF Initial Value 0 R/W R/W Description Receive Data Register Full [Setting condition] * When receive data is transferred from ICDRS to ICDRR When 0 is written to this bit after reading RDRF = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) When data is read from ICDRR [Clearing conditions] * * 4 NACKF 0 R/W No Acknowledge Detection Flag [Setting condition] * When no acknowledge is detected from the receive device in transmission while the ACKE bit in ICIER is set to 1 When 0 is written to this bit after reading NACKF = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) [Clearing condition] * 3 STOP 0 R/W Stop Condition Detection Flag [Setting condition] * When a stop condition is detected after frame transfer When 0 is written to this bit after reading STOP = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) [Clearing condition] * Rev.1.00 Jun. 07, 2006 Page 829 of 1102 REJ09B0294-0100 Section 17 I2C Bus Interface 2 (IIC2) Bit 2 Bit Name AL Initial Value 0 R/W R/W Description Arbitration Lost Flag This flag indicates that arbitration was lost in master mode. When two or more master devices attempt to seize the 2 bus at nearly the same time, the I C bus monitors SDA, 2 and if the I C bus interface detects data differing from the data it sent, it sets AL to 1 to indicate that the bus has been taken by another master. [Setting conditions] * When the internal SDA and the SDA pin level disagree at the rising of SCL in master transmit mode When the SDA pin outputs a high level in master mode while a start condition is detected When 0 is written to this bit after reading AL = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) * [Clearing condition] * 1 AAS 0 R/W Slave Address Recognition Flag In slave receive mode, this flag is set to 1 when the first frame following a start condition matches bits SVA6 to SVA0 in SAR. [Setting conditions] * * When the slave address is detected in slave receive mode When the general call address is detected in slave receive mode When 0 is written to this bit after reading AAS = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) [Clearing condition] * Rev.1.00 Jun. 07, 2006 Page 830 of 1102 REJ09B0294-0100 Section 17 I2C Bus Interface 2 (IIC2) Bit 0 Bit Name ADZ Initial Value 0 R/W R/W Description General Call Address Recognition Flag This bit is valid in slave receive mode. [Setting condition] * When the general call address is detected in slave receive mode When 0 is written to this bit after reading ADZ = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) [Clearing condition] * 17.3.6 Slave Address Register (SAR) SAR is sets the slave address. In slave mode, if the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition, the LSI operates as the slave device. Bit Bit Name Initial Value R/W 7 SVA6 0 R/W 6 SVA5 0 R/W 5 SVA4 0 R/W 4 SVA3 0 R/W 3 SVA2 0 R/W 2 SVA1 0 R/W 1 SVA0 0 R/W 0 0 R/W Bit 7 to 1 Initial Bit Name Value SVA6 to SVA0 0 R/W R/W Description Slave Address 6 to 0 These bits set a unique address differing from the 2 addresses of other slave devices connected to the I C bus. 0 0 R/W Reserved Although this bit is readable/writable, only 0 should be written to. Rev.1.00 Jun. 07, 2006 Page 831 of 1102 REJ09B0294-0100 Section 17 I2C Bus Interface 2 (IIC2) 17.3.7 I C Bus Transmit Data Register (ICDRT) 2 ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects a 2 space in the I C bus shift register, it transfers the transmit data which has been written to ICDRT to ICDRS and starts transmitting data. If the next data is written to ICDRT during transmitting data to ICDRS, continuous transmission is possible. Bit Bit Name Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 6 5 4 3 2 1 0 17.3.8 I C Bus Receive Data Register (ICDRR) 2 ICDRR is an 8-bit read-only register that stores the receive data. When one byte of data has been received, ICDRR transfers the receive data from ICDRS to ICDRR and the next data can be received. ICDRR is a receive-only register; therefore, this register cannot be written to by the CPU. Bit Bit Name Initial Value R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 7 6 5 4 3 2 1 0 17.3.9 I C Bus Shift Register (ICDRS) 2 ICDRS is an 8-bit write-only register that is used to transmit/receive data. In transmission, data is transferred from ICDRT to ICDRS and the data is sent from the SDA pin. In reception, data is transferred from ICDRS to ICDRR after one by of data is received. This register cannot be read from the CPU. Bit Bit Name Initial Value R/W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 7 6 5 4 3 2 1 0 Rev.1.00 Jun. 07, 2006 Page 832 of 1102 REJ09B0294-0100 Section 17 I2C Bus Interface 2 (IIC2) 17.4 17.4.1 Operation I C Bus Format 2 2 2 Figure 17.3 shows the I C bus formats. Figure 17.4 shows the I C bus timing. The first frame following a start condition always consists of 8 bits. (a) I2C bus format S 1 SLA 7 1 R/W 1 A 1 DATA n A 1 m A/A 1 P 1 n: Transfer bit count (n = 1 to 8) m: Transfer frame count (m 1) (b) I2C bus format (start condition retransmission) S 1 SLA 7 1 R/W 1 A 1 DATA n1 m1 A/A 1 S 1 SLA 7 1 R/W 1 A 1 DATA n2 m2 A/A 1 P 1 n1 and n2: Transfer bit count (n1 and n2 = 1 to 8) m1 and m2: Transfer frame count (m1 and m2 1) Figure 17.3 I C Bus Formats 2 SDA SCL 1-7 S SLA 8 R/W 9 A 1-7 DATA 2 8 9 A 1-7 DATA 8 9 A P Figure 17.4 I C Bus Timing [Legend] S: SLA: R/W: A: P: Start condition. The master device drives SDA from high to low while SCL is high. Slave address Indicates the direction of data transfer; from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0. Acknowledge. The receive device drives SDA low. Stop condition. The master device drives SDA from low to high while SCL is high. DATA: Transferred data Rev.1.00 Jun. 07, 2006 Page 833 of 1102 REJ09B0294-0100 Section 17 I2C Bus Interface 2 (IIC2) 17.4.2 2 Master Transmit Operation In I C bus format master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device return an acknowledge signal. Figures 17.5 and 17.6 show the operating timings in master transmit mode. The transmission procedure and operations in master transmit mode are described below. 1. Set the ICR bit in the corresponding register to 1. Set the ICE bit in ICCRA to 1. Set the WAIT bit in ICMR and the CKS3 to CKS0 bits in ICCRA to 1. (initial setting) 2. Read the BSSY flag in ICCRB to confirm that the bus is free. Set the MST and TRS bits in ICCRA to select master transmit mode. Then, write 1 to BBSY and 0 to SCP using the MOV instruction. (The start condition is issued.) This generates the start condition. 3. After confirming that TDRE in ICSR has been set, write the transmit data (the first byte shows the slave address and R/W) to ICDRT. After this, when TDRE is automatically cleared to 0, data is transferred from ICDRT to ICDRS. TDRE is set again. 4. When transmission of one byte data is completed while TDRE is 1, TEND in ICSR is set to 1 at the rising of the ninth transmit clock pulse. Read the ACKBR bit in ICIER to confirm that the slave device has been selected. Then, write the second byte data to ICDRT. When ACKBR is 1, the slave device has not been acknowledged, so issue a stop condition. To issue the stop condition, write 0 to BBSY and SCP using the MOV instruction. SCL is fixed to a low level until the transmit data is prepared or the stop condition is issued. 5. The transmit data after the second byte is written to ICDRT every time TDRE is set. 6. Write the number of bytes to be transmitted to ICDRT. Wait until TEND is set (the end of last byte data transmission) while TDRE is 1, or wait for NACK (NACKF in ICSR is 1) from the receive device while CKE in ICIER is 1. Then, issue the stop condition to clear TEND or NACKF. 7. When the STOP bit in ICSR is set to 1, the operation returns to the slave receive mode. Rev.1.00 Jun. 07, 2006 Page 834 of 1102 REJ09B0294-0100 Section 17 I2C Bus Interface 2 (IIC2) SCL (Master output) SDA (Master output) 1 2 3 4 5 6 7 8 9 1 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W A Bit 7 Bit 6 Slave address SDA (Slave output) TDRE TEND ICDRT Address + R/W Data 1 Data 2 ICDRS Address + R/W Data 1 User processing [2] Instruction of start condition issuance [4] Write data to ICDRT (second byte) [3] Write data to ICDRT (first byte) [5] Write data to ICDRT (third byte) Figure 17.5 Master Transmit Mode Operation Timing 1 SCL (Master output) SDA (Master output) SDA (Slave output) TDRE 9 1 2 3 4 5 6 7 8 9 Bit 7 A Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 A/A TEND ICDRT Data n ICDRS User processing Data n [5] Write data to ICDRT [6] Issue stop condition. Clear TEND. [7] Set slave receive mode Figure 17.6 Master Transmit Mode Operation Timing 2 Rev.1.00 Jun. 07, 2006 Page 835 of 1102 REJ09B0294-0100 Section 17 I2C Bus Interface 2 (IIC2) 17.4.3 Master Receive Operation In master receive mode, the master device outputs the receive clock, receives data from the slave device, and returns an acknowledge signal. Figures 17.7 and 17.8 show the operation timings in master receive mode. The reception procedure and operations in master receive mode are shown below. 1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCRA to 0 to switch from master transmit mode to master receive mode. Then, clear the TDRE bit to 0. 2. When ICDDR is read (dummy read), reception is started, the receive clock pulse is output, and data is received, in synchronization with the internal clock. The master mode outputs the level specified by the ACKBT in ICIER to SDA, at the ninth receive clock pulse. 3. After the reception of the first frame data is completed, the RDRF bit in ICSR is set to 1 at the rising of the ninth receive clock pulse. At this time, the received data is read by reading ICDRR. At the same time, RDRF is cleared. 4. The continuous reception is performed by reading ICDRR and clearing RDRF to 0 every time RDRF is set. If the eighth receive clock pulse falls after reading ICDRR by other processing while RDRF is 1, SCL is fixed to a low level until ICDRR is read. 5. If the next frame is the last receive data, set the RCVD bit in ICCR1 before reading ICDRR. This enables the issuance of the stop condition after the next reception. 6. When the RDRF bit is set to 1 at the rising of the ninth receive clock pulse, the stop condition is issued. 7. When the STOP bit in ICSR is set to 1, read ICDRR and clear RCVD to 0. 8. The operation returns to the slave receive mode. Rev.1.00 Jun. 07, 2006 Page 836 of 1102 REJ09B0294-0100 Section 17 I2C Bus Interface 2 (IIC2) Master transmit mode SCL (Master output) SDA (Master output) SDA (Slave output) TDRE A Bit 7 9 1 Master receive mode 2 3 4 5 6 7 8 9 A 1 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 TEND TRS RDRF ICDRS Data 1 ICDRR Data 1 User processing [1] Clear TEND and TRS, then TDRE [2] Read ICDRR (dummy read) [3] Read ICDRR Figure 17.7 Master Receive Mode Operation Timing 1 Rev.1.00 Jun. 07, 2006 Page 837 of 1102 REJ09B0294-0100 Section 17 I2C Bus Interface 2 (IIC2) SCL (Master output) SDA (Master output) SDA (Slave output) RDRF 9 A 1 2 3 4 5 6 7 8 9 A/A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RCVD ICDRS Data n-1 Data n ICDRR User processing Data n-1 Data n [5] Set RCVD then read ICDRR [6] Issue stop condition [7] Read ICDRR and clear RCVD [8] Set slave receive mode Figure 17.8 Master Receive Mode Operation Timing 2 17.4.4 Slave Transmit Operation In slave transmit mode, the slave device outputs the transmit data, and the master device outputs the receive clock pulse and returns an acknowledge signal. Figures 17.9 and 17.10 show the operation timings in slave transmit mode. The transmission procedure and operations in slave transmit mode are described below. 1. Set the ICR bit in the corresponding register to 1, then set the ICE bit in ICCRA to 1. Set the ACKBIT in ICIER, and perform other initial settings. Set the MST and TRS bits in ICCRA to select slave receive mode, and wait until the slave address matches. 2. When the slave address matches in the first frame following the detection of the start condition, the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rising of the ninth clock pulse. At this time, if the eighth bit data (R/W) is 1, TRS in ICCRA and TDRE in ICSR are set to 1, and the mode changes to slave transmit mode automatically. The continuous transmission is performed by writing the transmit data to ICDRT every time TDRE is set. 3. If TDRE is set after writing the last transmit data to ICDRT, wait until TEND in ICSR is set to 1, with TDRE = 1. When TEND is set, clear TEND. 4. Clear TRS for end processing, and read ICDRR (dummy read) to free SCL. 5. Clear TDRE. Rev.1.00 Jun. 07, 2006 Page 838 of 1102 REJ09B0294-0100 Section 17 I2C Bus Interface 2 (IIC2) Slave receive mode SCL (Master output) SDA (Master output) SCL (Slave output) SDA (Slave output) TDRE A 9 Slave transmit mode 1 2 3 4 5 6 7 8 9 A 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 TEND TRS ICDRT Data 1 Data 2 Data 3 ICDRS Data 1 Data 2 ICDRR User processing [2] Write data (data 1) to ICDRT [2] Write data (data 2) to ICDRT [2] Write data (data 3) to ICDRT Figure 17.9 Slave Transmit Mode Operation Timing 1 Rev.1.00 Jun. 07, 2006 Page 839 of 1102 REJ09B0294-0100 Section 17 I2C Bus Interface 2 (IIC2) Slave transmit mode SCL (Master output) SDA (Master output) SCL (Slave output) SDA (Slave output) TDRE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 A 1 2 3 4 5 6 7 8 9 A/A Slave receive mode TEND TRS ICDRT ICDRS Data n ICDRR User processing [3] Clear TEND [4] Clear TRS and read ICDRR (dummy read) [5] Clear TDRE Figure 17.10 Slave Transmit Mode Operation Timing 2 Rev.1.00 Jun. 07, 2006 Page 840 of 1102 REJ09B0294-0100 Section 17 I2C Bus Interface 2 (IIC2) 17.4.5 Slave Receive Operation In slave receive mode, the master device outputs the transmit clock and the transmit data, and the slave device returns an acknowledge signal. Figures 17.11 and 17.12 show the operation timings in slave receive mode. The reception procedure and operations in slave receive mode are described below. 1. Set the ICR bit in the corresponding register to 1. Then, set the ICE bit in ICCRA to 1. Set the ACKBT bit in ICIER and perform other initial settings. Set the MST and TRS bits in ICCRA to select slave receive mode and wait until the slave address matches. 2. When the slave address matches in the first frame following detection of the start condition, the slave address outputs the level specified by ACKBT in ICIER to SDA, at the rising of the ninth clock pulse. At the same time, RDRF in ICSR is set to read ICDRR (dummy read). (Since the read data shows the slave address and R/W, it is not used). 3. Read ICDRR every time RDRF is set. If the eighth clock pulse falls while RDRF is 1, SCL is fixed to a low level until ICDRR is read. The change of the acknowledge (ACKBT) setting before reading ICDRR to be returned to the master device is reflected in the next transmit frame. 4. The last byte data is read by reading ICDRR. SCL (Master output) SDA (Master output) SCL (Slave output) SDA (Slave output) RDRF A A 9 1 2 3 4 5 6 7 8 9 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 ICDRS Data 1 Data 2 ICDRR User processing Data 1 [2] Read ICDRR (dummy read) [2] Read ICDRR Figure 17.11 Slave Receive Mode Operation Timing 1 Rev.1.00 Jun. 07, 2006 Page 841 of 1102 REJ09B0294-0100 Section 17 I2C Bus Interface 2 (IIC2) SCL (Master output) SDA (Master output) SCL (Slave output) SDA (Slave output) 9 1 2 3 4 5 6 7 8 9 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 A A RDRF ICDRS Data 1 Data 2 ICDRR User processing [3] Set ACKBT [3] Read ICDRR Data 1 [4] Read ICDRR Figure 17.12 Slave Receive Mode Operation Timing 2 17.4.6 Noise Canceler The logic levels at the SCL and SDA pins are routed through the noise cancelers before being latched internally. Figure 17.13 shows a block diagram of the noise canceler circuit. The noise canceler consists of two cascaded latches and a match detector. The signal input to SCL (or SDA) is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. If they do not agree, the previous value is held. Sampling clock Sampling clock SCL input or SDA input C D Q D C Q Latch Latch Compare match detection circuit Internal SCL or internal SDA System clock period Sampling clock Figure 17.13 Block Diagram of Noise Canceler Rev.1.00 Jun. 07, 2006 Page 842 of 1102 REJ09B0294-0100 Section 17 I2C Bus Interface 2 (IIC2) 17.4.7 Example of Use 2 Sample flowcharts in respective modes that use the I C bus interface are shown in figures 17.14 to 17.17. Start Initial settings Read BBSY in ICCRB No [1] BBSY = 0? Yes Set MST = 1 and TRS = 1 in ICCRA Write BBSY = 1 and SCP = 0 Write the transmit data in ICDRT Read TEND in ISCR No [5] TEND = 1? [2] [3] [1] [2] [3] [4] [5] [6] [7] Detect the state of the SCL and SDA lines Set to master transmit mode Issue the start condition Set the transmit data for the first byte (slave address + R/W) Wait for 1 byte of data to be transmitted Detect the acknowledge bit, transferred from the specified slave device Set the transmit data for the second and subsequent data (except for the last byte) Wait for ICDRT empty Set the last byte of transmit data [4] Yes Read ACKBR in ICIER [6] ACKBR = 0? Yes Transmit mode? Yes No No [8] [9] Master receive mode Write the transmit data to ICDRT Read TDRE in ICSR TDRE = 1? Yes No Last byte? Yes [7] [10] Wait for the completion of transmission of the last byte [8] [11] Clear the TEND flag [12] Clear the STOP flag [9] [13] Issue the stop condition [14] Wait for the creation of the stop condition Write the transmit data to ICDRT Read TEND in ICSR No [10] TEND = 1? Yes Clear TEND in ICSR Clear STOP in ICSR Write BBSY = 0 and SCP = 0 Read STOP in ICSR No [14] STOP = 1? Yes Set MST = 0 and TRS = 0 in ICCRA Clear TRDE in ICSR End [11] [12] [13] [15] Set to slave receive mode. Clear TDRE. [15] Figure 17.14 Sample Flowchart of Master Transmit Mode Rev.1.00 Jun. 07, 2006 Page 843 of 1102 REJ09B0294-0100 Section 17 I2C Bus Interface 2 (IIC2) Master receive mode Clear TEND in ICSR Set TRS = 0 (ICCRA) Clear TDRE in ICSR Set ACKBT = 0 (ICIER) Dummy read ICDRR Dummy read ICSR No RDRF = 1? Yes [4] [2] [3] [1] [1] [2] [3] [4] [5] [6] [7] Clear TEND, set to master receive mode, then clear TDRE*1*2 Set acknowledge to the transmitting device*1*2 Dummy read ICDRR*1*2 Wait for 1 byte of data to be received*2 Check if (last receive -1)*2 Read the receive data*2 Set acknowledge of the last byte. Disable continuous reception (RCVD = 1).*2 Read receive data of (last byte -1).*2 Wait for the last byte to be received Last receive -1? No Yes [5] [8] [6] Read ICDRR [9] [10] Clear the STOP flag Set ACKBT = 1 (ICIER) [7] [11] Issue the stop condition [12] Wait for the creation of stop condition Set RCVD = 1 (ICCRA) Read ICDRR Read RDRF in ICSR No [9] RDRF = 1? Yes [8] [13] Read the receive data of the last byte [14] Clear RCVD to 0 [15] Set to slave receive mode Clear STOP in ICSR Write BBSY = 0 and SCP = 0 Read STOP in ICSR No [10] [11] [12] STOP = 1? Yes Read ICDRR Set RCVD = 0 (ICCRA) Set MST = 0 (ICCRA) End Note: 1. 2. [13] [14] [15] Do not generate an interrupt during steps [1] to [3]. For one-byte reception, steps [2] to [6] do not need to be executed. After step [1], execute step [7]. In step [8], read ICDRR (dummy read). Figure 17.15 Sample Flowchart for Master Receive Mode Rev.1.00 Jun. 07, 2006 Page 844 of 1102 REJ09B0294-0100 Section 17 I2C Bus Interface 2 (IIC2) Slave transmit mode Clear AAS in ICSR [1] [1] Clear the AAS flag. [2] Set the transmit data for ICDRT (except the last byte). [2] [3] Wait for ICDRT empty. [4] Set the last byte of transmit data. [3] TDRE = 1? Yes No Last byte? Yes Write the transmit data to ICDRT Read TEND in ICSR No [5] TEND = 1? Yes Clear TEND in ICSR Set TRS = 0 (ICCRA) Dummy read ICDRR Clear TDRE in ICSR End [4] [6] Clear the TEND flag. [7] Set to slave receive mode. [8] Dummy read ICDRR to free the SCL line. [9] Clear the TDRE flag. [5] Wait for the last byte of data to be transmitted. Write the transmit data to ICDRT Read TRD in ICSR No [6] [7] [8] [9] Figure 17.16 Sample Flowchart for Slave Transmit Mode Rev.1.00 Jun. 07, 2006 Page 845 of 1102 REJ09B0294-0100 Section 17 I2C Bus Interface 2 (IIC2) Slave receive mode Clear AAS in ICSR Set ACKBT = 0 in ICIER Dummy read ICDRR Read RDRF in ICSR [1] [2] [3] [1] Clear the AAS flag.* [2] Set the acknowledge for the transmit device.* [3] Dummy read ICDRR* [4] Wait for 1 byte of data to be received* [5] Detect (last reception -1)* No RDRF = 1? Yes The last reception -1? [4] [6] Read the receive data.* [7] Set the acknowledge for the last byte.* Yes [5] [8] Read the receive data of (last byte -1).* [9] Wait for the reception of the last byte to be completed. No Read ICDRR [6] [10] Read the last byte of receive data. Set ACKBT = 1 in ICIER [7] Read ICDRR Read RDRF in ICSR [8] No [9] RDRF = 1? Yes Read ICDRR End [10] Note: * For one-byte reception, steps [2] to [6] do not need to be executed. After step [1], execute step [7]. In step [8], read ICDRR (dummy read). Figure 17.17 Sample Flowchart for Slave Receive Mode Rev.1.00 Jun. 07, 2006 Page 846 of 1102 REJ09B0294-0100 Section 17 I2C Bus Interface 2 (IIC2) 17.5 Interrupt Request There are six interrupt requests in this module; transmit data empty, transmit end, receive data full, NACK detection, STOP recognition, and arbitration lost. Table 17.3 shows the contents of each interrupt request. Table 17.3 Interrupt Requests Interrupt Request Transmit Data Empty Transmit End Receive Data Full Stop Recognition NACK Detection Arbitration Lost Abbreviation TXI TEI RXI STPI MAKI Interrupt Condition (TDRE = 1) (TIE = 1) (TEND = 1) (TEIE = 1) (RDRF = 1) (RIE = 1) (STOP = 1) (STIE = 1) {(NACKF = 1) + (AL = 1)} (NAKIE = 1) 17.6 Bit Synchronous Circuit This module has a possibility that the high-level period is shortened in the two states described below. In master mode, * When SCL is driven low by the slave device * When the rising speed of SCL is lowered by the load on the SCL line (load capacitance or pull-up resistance) Therefore, this module monitors SCL and communicates bit by bit in synchronization. Figure 17.18 shows the timing of the bit synchronous circuit, and table 17.4 shows the time when SCL output changes from low to Hi-Z and the period which SCL is monitored. Rev.1.00 Jun. 07, 2006 Page 847 of 1102 REJ09B0294-0100 Section 17 I2C Bus Interface 2 (IIC2) SCL monitor timing reference clock SCL VIH Internal SCL Figure 17.18 Timing of the Bit Synchronous Circuit Table 17.4 Time for Monitoring SCL CKS3 0 CKS2 0 1 1 0 1 Time for Monitoring SCL 7.5 tcyc 19.5 tcyc 17.5 tcyc 41.5 tcyc 17.7 Usage Notes 2 1. Confirm the ninth falling edge of the clock before issuing a stop or a repeated start condition. The ninth falling edge can be confirmed by monitoring the SCLO bit in the I C bus control register B (ICCRB). If a stop or a repeated start condition is issued at certain timing in either of the following cases, the stop or repeated start condition may be issued incorrectly. The rising time of the SCL signal exceeds the time given in section 17.6, Bit Synchronous Circuit, because of the load on the SCL bus (load capacitance or pull-up resistance). The bit synchronous circuit is activated because a slave device holds the SCL bus low during the eighth clock. 2. The WAIT bit in the I C bus mode register (ICMR) must be held 0. If the WAIT bit is set to 1, when a slave device holds the SCL signal low more than one transfer clock cycle during the eighth clock, the high level period of the ninth clock may be shorter than a given period. 2 Rev.1.00 Jun. 07, 2006 Page 848 of 1102 REJ09B0294-0100 Section 18 A/D Converter Section 18 A/D Converter This LSI includes a successive approximation type 10-bit A/D converter that allows up to eight analog input channels to be selected. Figure 18.1 shows a block diagram of the A/D converter. 18.1 Features * 10-bit resolution * Eight input channels * Conversion time: 7.6 s per channel (at 35-MHz operation) * Two kinds of operating modes Single mode: Single-channel A/D conversion Scan mode: Continuous A/D conversion on 1 to 4 channels, or 1 to 8 channels * Eight data registers A/D conversion results are held in a 16-bit data register for each channel * Sample and hold function * Three types of conversion start Conversion can be started by software, a conversion start trigger by the 16-bit timer pulse unit (TPU) or 8-bit timer (TMR), or an external trigger signal. * Interrupt source A/D conversion end interrupt (ADI) request can be generated. * Module stop state specifiable Rev.1.00 Jun. 07, 2006 Page 849 of 1102 REJ09B0294-0100 Section 18 A/D Converter Module data bus Bus interface ADDRG ADDRC ADDRD ADDRH ADCSR ADDRA ADDRB ADDRE ADDRF Internal data bus AVCC 10-bit A/D Successive approximation register Vref AVSS AN0 AN1 Multiplexer + - Comparator Sample-andhold circuit Control circuit AN2 AN3 AN4 AN5 AN6 AN7 ADCR ADTRG0 [Legend] ADCR: ADCSR: ADDRA: ADDRB: ADDRC: ADI0 interrupt signal Conversion start trigger from the TPU or TMR A/D control register A/D control/status register A/D data register A A/D data register B A/D data register C ADDRD: ADDRE: ADDRF: ADDRG: ADDRH: A/D data register D A/D data register E A/D data register F A/D data register G A/D data register H Figure 18.1 Block Diagram of A/D Converter Rev.1.00 Jun. 07, 2006 Page 850 of 1102 REJ09B0294-0100 Section 18 A/D Converter 18.2 Input/Output Pins Table 18.1 shows the pin configuration of the A/D converter. Table 18.1 Pin Configuration Pin Name Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 A/D external trigger input pin Analog power supply pin Analog ground pin Reference voltage pin Symbol AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 I/O Function Input Analog inputs Input Input Input Input Input Input Input ADTRG0 Input External trigger input for starting A/D conversion AVCC AVSS Vref Input Analog block power supply Input Analog block ground Input A/D conversion reference voltage 18.3 Register Descriptions The A/D converter has the following registers. * A/D data register A (ADDRA) * A/D data register B (ADDRB) * A/D data register C (ADDRC) * A/D data register D (ADDRD) * A/D data register E (ADDRE) * A/D data register F (ADDRF) * A/D data register G (ADDRG) * A/D data register H (ADDRH) * A/D control/status register (ADCSR) * A/D control register (ADCR) Rev.1.00 Jun. 07, 2006 Page 851 of 1102 REJ09B0294-0100 Section 18 A/D Converter 18.3.1 A/D Data Registers A to H (ADDRA to ADDRH) There are eight 16-bit read-only ADDR registers, ADDRA to ADDRH, used to store the results of A/D conversion. The ADDR registers, which store a conversion result for each channel, are shown in table 18.2. The converted 10-bit data is stored in bits 15 to 6. The lower 6-bit data is always read as 0. The data bus between the CPU and the A/D converter has a 16-bit width. The data can be read directly from the CPU. ADDR must not be accessed in 8-bit units and must be accessed in 16-bit units. Bit Bit Name Initial Value R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 15 14 13 12 11 10 9 8 7 6 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R Table 18.2 Analog Input Channels and Corresponding ADDR Registers Analog Input Channel AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 A/D Data Register Which Stores Conversion Result ADDRA ADDRB ADDRC ADDRD ADDRE ADDRF ADDRG ADDRH Rev.1.00 Jun. 07, 2006 Page 852 of 1102 REJ09B0294-0100 Section 18 A/D Converter 18.3.2 A/D Control/Status Register (ADCSR) ADCSR controls A/D conversion operations. Bit Bit Name Initial Value R/W 7 ADF 0 R/(W)* 6 ADIE 0 R/W 5 ADST 0 R/W 4 0 R 3 CH3 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W 0 CH0 0 R/W Note: * Only 0 can be written to this bit, to clear the flag. Bit 7 Bit Name ADF Initial Value 0 R/W Description R/(W)* A/D End Flag A status flag that indicates the end of A/D conversion. [Setting conditions] * * When A/D conversion ends in single mode When A/D conversion ends on all specified channels in scan mode When 0 is written after reading ADF = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) When the DMAC or DTC is activated by an ADI interrupt and ADDR is read [Clearing conditions] * * 6 ADIE 0 R/W A/D Interrupt Enable When this bit is set to 1, ADI interrupts by ADF are enabled. 5 ADST 0 R/W A/D Start Clearing this bit to 0 stops A/D conversion, and the A/D converter enters wait state. Setting this bit to 1 starts A/D conversion. In single mode, this bit is cleared to 0 automatically when A/D conversion on the specified channel ends. In scan mode, A/D conversion continues sequentially on the specified channels until this bit is cleared to 0 by software, a reset, or hardware standby mode. Rev.1.00 Jun. 07, 2006 Page 853 of 1102 REJ09B0294-0100 Section 18 A/D Converter Bit 4 3 2 1 0 Bit Name CH3 CH2 CH1 CH0 Initial Value 0 0 0 0 0 R/W R R/W R/W R/W R/W Description Reserved This is a read-only bit and cannot be modified. Channel Select 3 to 0 Selects analog input together with bits SCANE and SCANS in ADCR. * When SCANE = 0 and SCANS = X 0000: AN0 0001: AN1 0010: AN2 0011: AN3 0100: AN4 0101: AN5 0110: AN6 0111: AN7 1XXX: Setting prohibited * When SCANE = 1 and SCANS = 0 0000: AN0 0001: AN0 and AN1 0010: AN0 to AN2 0011: AN0 to AN3 0100: AN4 0101: AN4 and AN5 0110: AN4 to AN6 0111: AN4 to AN7 1XXX: Setting prohibited * When SCANE = 1 and SCANS = 1 0000: AN0 0001: AN0 and AN1 0010: AN0 to AN2 0011: AN0 to AN3 0100: AN0 to AN4 0101: AN0 to AN5 0110: AN0 to AN6 0111: AN0 to AN7 1XXX: Setting prohibited [Legend] X: Don't care Note: * Only 0 can be written to this bit, to clear the flag. Rev.1.00 Jun. 07, 2006 Page 854 of 1102 REJ09B0294-0100 Section 18 A/D Converter 18.3.3 A/D Control Register (ADCR) ADCR enables A/D conversion to be started by an external trigger input. Bit Bit Name Initial Value R/W 7 TRGS1 0 R/W 6 TRGS0 0 R/W 5 SCANE 0 R/W 4 SCANS 0 R/W 3 CKS1 0 R/W 2 CKS0 0 R/W 1 0 R 0 0 R Bit 7 6 Bit Name TRGS1 TRGS0 Initial Value 0 0 R/W R/W R/W Description Timer Trigger Select 1 and 0 These bits select enabling or disabling of the start of A/D conversion by a trigger signal. 00: A/D conversion start by external trigger is disabled 01: A/D conversion start by external trigger from TPU is enabled 10: A/D conversion start by external trigger from TMR is enabled 11: A/D conversion start by the ADTRG0 pin is enabled* 5 4 SCANE SCANS 0 0 R/W R/W Scan Mode These bits select the A/D conversion operating mode. 0X: Single mode 10: Scan mode. A/D conversion is performed continuously for channels 1 to 4. 11: Scan mode. A/D conversion is performed continuously for channels 1 to 8. 3 2 CKS1 CKS0 0 0 R/W R/W Clock Select 1 and 0 These bits set the A/D conversion time. Set bits CKS1 and CKS0 only while A/D conversion is stopped (ADST = 0). 00: A/D conversion time = 530 states (max) 01: A/D conversion time = 266 states (max) 10: A/D conversion time = 134 states (max) 11: A/D conversion time = 68 states (max) Rev.1.00 Jun. 07, 2006 Page 855 of 1102 REJ09B0294-0100 Section 18 A/D Converter Bit 1, 0 Bit Name Initial Value All 0 R/W R Description Reserved These are read-only bits and cannot be modified. [Legend] X: Don't care Note: * To set A/D conversion to start by the ADTRG pin, the DDR bit and ICR bit for the corresponding pin should be set to 0 and 1, respectively. For details, refer to section 9, I/O Ports. 18.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes: single mode and scan mode. When changing the operating mode or analog input channel, to prevent incorrect operation, first clear the ADST bit in ADCSR to 0 to halt A/D conversion. The ADST bit can be set to 1 at the same time as the operating mode or analog input channel is changed. 18.4.1 Single Mode In single mode, A/D conversion is to be performed only once on the analog input of the specified single channel. 1. A/D conversion for the selected channel is started when the ADST bit in ADCSR is set to 1 by software or an external trigger input. 2. When A/D conversion is completed, the A/D conversion result is transferred to the corresponding A/D data register of the channel. 3. When A/D conversion is completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. 4. The ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when A/D conversion ends. The A/D converter enters wait state. If the ADST bit is cleared to 0 during A/D conversion, A/D conversion stops and the A/D converter enters wait state. Rev.1.00 Jun. 07, 2006 Page 856 of 1102 REJ09B0294-0100 Section 18 A/D Converter Set* ADIE Set* ADST A/D conversion start Clear* ADF Clear* Set* Channel 0 (AN0) operation state Channel 1 (AN1) operation state Channel 2 (AN2) operation state Channel 3 (AN3) operation state ADDRA Waiting for conversion Waiting for conversion A/D conversion 1 Waiting for conversion A/D conversion 2 Waiting for conversion Waiting for conversion Waiting for conversion Reading A/D conversion result Reading A/D conversion result A/D conversion result 2 ADDRB ADDRC A/D conversion result 1 ADDRD Note: * indicates the timing of instruction execution by software. Figure 18.2 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) 18.4.2 Scan Mode In scan mode, A/D conversion is to be performed sequentially on the analog inputs of the specified channels up to four or eight channels. 1. When the ADST bit in ADCSR is set to 1 by software, TPU, TMR, or an external trigger input, A/D conversion starts on the first channel in the group. Consecutive A/D conversion on a maximum of four channels (SCANE and SCANS = B'10) or on a maximum of eight channels (SCANE and SCANS = B'11) can be selected. When consecutive A/D conversion is performed on four channels, A/D conversion starts on AN4 when CH3 and CH2 = B'01. When consecutive A/D conversion is performed on eight channels, A/D conversion starts on AN0 when CH3 = B'0. 2. When A/D conversion for each channel is completed, the A/D conversion result is sequentially transferred to the corresponding ADDR of each channel. Rev.1.00 Jun. 07, 2006 Page 857 of 1102 REJ09B0294-0100 Section 18 A/D Converter 3. When A/D conversion of all selected channels is completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. A/D conversion of the first channel in the group starts again. 4. The ADST bit is not cleared automatically, and steps [2] to [3] are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops and the A/D converter enters wait state. If the ADST bit is later set to 1, A/D conversion starts again from the first channel in the group. A/D conversion consecutive execution Set*1 ADST Clear*1 Clear*1 ADF Channel 0 (AN0) operation state Channel 1 (AN1) operation state Channel 2 (AN2) operation state Channel 3 (AN3) operation state ADDRA Waiting for conversion A/D conversion 1 A/D conversion time Waiting for conversion A/D conversion 2 A/D conversion 4 Waiting for conversion A/D conversion 5 Waiting for conversion Waiting for conversion Waiting for conversion A/D conversion 3 *2 Waiting for conversion Waiting for conversion Waiting for conversion Transfer A/D conversion result 1 A/D conversion result 4 ADDRB A/D conversion result 2 ADDRC A/D conversion result 3 ADDRD Notes: 1. indicates the timing of instruction execution by software. 2. Data being converted is ignored. Figure 18.3 Example of A/D Conversion (Scan Mode, Three Channels (AN0 to AN2) Selected) Rev.1.00 Jun. 07, 2006 Page 858 of 1102 REJ09B0294-0100 Section 18 A/D Converter 18.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (tD) passes after the ADST bit in ADCSR is set to 1, then starts A/D conversion. Figure 18.4 shows the A/D conversion timing. Table 18.3 indicates the A/D conversion time. As indicated in figure 18.4, the A/D conversion time (tCONV) includes tD and the input sampling time (tSPL). The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 18.3. In scan mode, the values given in table 18.3 apply to the first conversion time. The values given in table 18.4 apply to the second and subsequent conversions. In either case, bits CKS1 and CKS0 in ADCR should be set so that the conversion time is within the ranges indicated by the A/D conversion characteristics. (1) P Address (2) Write signal Input sampling timing ADF tD tSPL tCONV [Legend] (1): ADCSR write cycle (2): ADCSR address tD: A/D conversion start delay time tSPL: Input sampling time tCONV: A/D conversion time Figure 18.4 A/D Conversion Timing Rev.1.00 Jun. 07, 2006 Page 859 of 1102 REJ09B0294-0100 Section 18 A/D Converter Table 18.3 A/D Conversion Characteristics (Single Mode) CKS1 = 0 CKS0 = 0 Item A/D conversion start delay time A/D conversion time Symbol tD Min. Typ. Max. 18 515 127 33 530 CKS0 = 1 Min. Typ. Max. 10 259 63 17 266 CKS0 = 0 Min. Typ. Max. 6 131 31 9 134 CKS1 = 1 CKS0 = 1 Min. Typ. Max. 4 67 15 5 68 Input sampling time tSPL tCONV Note: Values in the table are the number of states. Table 18.4 A/D Conversion Characteristics (Scan Mode) CKS1 0 CKS0 0 1 1 0 1 Conversion Time (Number of States) 512 (Fixed) 256 (Fixed) 128 (Fixed) 64 (Fixed) 18.4.4 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to B'11 in ADCR, an external trigger is input from the ADTRG0 pin. A/D conversion starts when the ADST bit in ADCSR is set to 1 on the falling edge of the ADTRG0 pin. Other operations, in both single and scan modes, are the same as when the ADST bit has been set to 1 by software. Figure 18.5 shows the timing. P ADTRG0 Internal trigger signal ADST A/D conversion Figure 18.5 External Trigger Input Timing Rev.1.00 Jun. 07, 2006 Page 860 of 1102 REJ09B0294-0100 Section 18 A/D Converter 18.5 Interrupt Source The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. Setting the ADIE bit to 1 when the ADF bit in ADCSR is set to 1 after A/D conversion is completed enables ADI interrupt requests. The data transfer controller (DTC) can be activated by an ADI interrupt. Having the converted data read by the DTC in response to an ADI interrupt enables continuous conversion to be achieved without imposing a load on software. Table 18.5 A/D Converter Interrupt Source Name ADI0 Interrupt Source A/D conversion end Interrupt Flag ADF DTC Activation Possible DMAC Activation Possible 18.6 A/D Conversion Accuracy Definitions This LSI's A/D conversion accuracy definitions are given below. * Resolution The number of A/D converter digital output codes. * Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 18.6). * Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value B'0000000000 (H'000) to B'0000000001 (H'001) (see figure 18.7). * Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from B'1111111110 (H'3FE) to B'1111111111 (H'3FF) (see figure 18.7). * Nonlinearity error The error with respect to the ideal A/D conversion characteristic between the zero voltage and the full-scale voltage. Does not include the offset error, full-scale error, or quantization error (see figure 18.7). * Absolute accuracy The deviation between the digital value and the analog input value. Includes the offset error, full-scale error, quantization error, and nonlinearity error. Rev.1.00 Jun. 07, 2006 Page 861 of 1102 REJ09B0294-0100 Section 18 A/D Converter Digital output 111 110 101 100 011 010 001 000 Ideal A/D conversion characteristic Quantization error 1 2 1024 1024 1022 1023 FS 1024 1024 Analog input voltage Figure 18.6 A/D Conversion Accuracy Definitions Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic FS Analog input voltage Offset error Figure 18.7 A/D Conversion Accuracy Definitions Rev.1.00 Jun. 07, 2006 Page 862 of 1102 REJ09B0294-0100 Section 18 A/D Converter 18.7 18.7.1 Usage Notes Module Stop State Setting Operation of the A/D converter can be disabled or enabled using the module stop control register. The initial setting is for operation of the A/D converter to be halted. Register access is enabled by clearing the module stop state. For details, refer to section 23, Power-Down Modes. 18.7.2 Permissible Signal Source Impedance This LSI's analog input is designed so that the conversion accuracy is guaranteed for an input signal for which the signal source impedance is 10 k or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 10 k, charging may be insufficient and it may not be possible to guarantee the A/D conversion accuracy. However, if a large capacitance is provided externally for conversion in single mode, the input load will essentially comprise only the internal input resistance of 10 k, and the signal source impedance is ignored. However, since a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/s or greater) (see figure 18.8). When converting a high-speed analog signal or conversion in scan mode, a low-impedance buffer should be inserted. Sensor output impedance R 10 k Sensor input Low-pass filter C = 0.1 F (recommended) This LSI Equivalent circuit of the A/D converter 10 k Cin = 15 pF 20 pF Figure 18.8 Example of Analog Input Circuit 18.7.3 Influences on Absolute Accuracy Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute accuracy. Be sure to make the connection to an electrically stable GND such as AVss. Care is also required to insure that digital signals on the board do not interfere with filter circuits and filter circuits do not act as antennas. Rev.1.00 Jun. 07, 2006 Page 863 of 1102 REJ09B0294-0100 Section 18 A/D Converter 18.7.4 Setting Range of Analog Power Supply and Other Pins If the conditions shown below are not met, the reliability of the LSI may be adversely affected. * Analog input voltage range The voltage applied to analog input pin ANn during A/D conversion should be in the range AVss VAN Vref. * Relation between AVcc, AVss and Vcc, Vss As the relationship between AVcc, AVss and Vcc, Vss, set AVcc = Vcc 0.3 V and AVss = Vss. If the A/D converter is not used, set AVcc = Vcc and AVss = Vss. * Vref setting range The reference voltage at the Vref pin should be set in the range Vref AVcc. 18.7.5 Notes on Board Design In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. Digital circuitry must be isolated from the analog input pins (AN0 to AN7), analog reference power supply (Vref), and analog power supply (AVcc) by the analog ground (AVss). Also, the analog ground (AVss) should be connected at one point to a stable ground (Vss) on the board. 18.7.6 Notes on Noise Countermeasures A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (AN0 to AN7) should be connected between AVcc and AVss as shown in figure 18.9. Also, the bypass capacitors connected to AVcc and the filter capacitor connected to the AN0 to AN7 pins must be connected to AVss. If a filter capacitor is connected, the input currents at the AN0 to AN7 pins are averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding the circuit constants. Rev.1.00 Jun. 07, 2006 Page 864 of 1102 REJ09B0294-0100 Section 18 A/D Converter AVCC Vref Rin* 2 *1 *1 0.1 F AVSS Notes: Values are reference values. 1. 10 F 0.01 F 100 AN0 to AN7 2. Rin: Input impedance Figure 18.9 Example of Analog Input Protection Circuit Table 18.6 Analog Pin Specifications Item Analog input capacitance Permissible signal source impedance Min Max 20 5 Unit pF k 10 k AN0 to AN7 To A/D converter 20 pF Note: Values are reference values. Figure 18.10 Analog Input Pin Equivalent Circuit 18.7.7 A/D Input Hold Function in Software Standby Mode When this LSI enters software standby mode with A/D conversion enabled, the analog inputs are retained, and the analog power supply current is equal to as during A/D conversion. If the analog power supply current needs to be reduced in software standby mode, clear the ADST, TRGS1, and TRGS0 bits all to 0 to disable A/D conversion. Rev.1.00 Jun. 07, 2006 Page 865 of 1102 REJ09B0294-0100 Section 18 A/D Converter Rev.1.00 Jun. 07, 2006 Page 866 of 1102 REJ09B0294-0100 Section 19 D/A Converter Section 19 D/A Converter 19.1 Features * 8-bit resolution * Two output channels * Maximum conversion time of 10 s (with 20 pF load) * Output voltage of 0 V to Vref * D/A output hold function in software standby mode * Module stop state specifiable Module data bus Internal data bus Vref 8-bit D/A DA1 DA0 AVSS Control circuit [Legend] DADR0: D/A data register 0 DADR1: D/A data register 1 DACR01: D/A control register 01 Figure 19.1 Block Diagram of D/A Converter DACR01 DADR0 DADR1 AVCC Rev.1.00 Jun. 07, 2006 Page 867 of 1102 REJ09B0294-0100 Bus interface Section 19 D/A Converter 19.2 Input/Output Pins Table 19.1 shows the pin configuration of the D/A converter. Table 19.1 Pin Configuration Pin Name Analog power supply pin Analog ground pin Reference voltage pin Analog output pin 0 Analog output pin 1 Symbol AVCC AVSS Vref DA0 DA1 I/O Input Input Input Output Output Function Analog block power supply Analog block ground D/A conversion reference voltage Channel 0 analog output Channel 1 analog output 19.3 Register Descriptions The D/A converter has the following registers. * D/A data register 0 (DADR0) * D/A data register 1 (DADR1) * D/A control register 01 (DACR01) 19.3.1 D/A Data Registers 0 and 1 (DADR0 and DADR1) DADR0 and DADR1 are 8-bit readable/writable registers that store data to which D/A conversion is to be performed. Whenever an analog output is enabled, the values in DADR are converted and output to the analog output pins. Bit Bit Name Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 6 5 4 3 2 1 0 Rev.1.00 Jun. 07, 2006 Page 868 of 1102 REJ09B0294-0100 Section 19 D/A Converter 19.3.2 D/A Control Register 01 (DACR01) DACR01 controls the operation of the D/A converter. Bit Bit Name Initial Value R/W 7 DAOE1 0 R/W 6 DAOE0 0 R/W 5 DAE 0 R/W 4 1 R 3 1 R 2 1 R 1 1 R 0 1 R Bit 7 Bit Name DAOE1 Initial Value 0 R/W R/W Description D/A Output Enable 1 Controls D/A conversion and analog output. 0: Analog output of channel 1 (DA1) is disabled 1: D/A conversion of channel 1 is enabled. Analog output of channel 1 (DA1) is enabled. 6 DAOE0 0 R/W D/A Output Enable 0 Controls D/A conversion and analog output. 0: Analog output of channel 0 (DA0) is disabled 1: D/A conversion of channel 0 is enabled. Analog output of channel 0 (DA0) is enabled. 5 DAE 0 R/W D/A Enable Used together with the DAOE0 and DAOE1 bits to control D/A conversion. When this bit is cleared to 0, D/A conversion is controlled independently for channels 0 and 1. When this bit is set to 1, D/A conversion for channels 0 and 1 is controlled together. Output of conversion results is always controlled by the DAOE0 and DAOE1 bits. For details, see Table 19.2, Control of D/A Conversion. 4 to 0 All 1 R Reserved These are read-only bits and cannot be modified. Rev.1.00 Jun. 07, 2006 Page 869 of 1102 REJ09B0294-0100 Section 19 D/A Converter Table 19.2 Control of D/A Conversion Bit 5 DAE 0 Bit 7 DAOE1 0 Bit 6 DAOE0 0 1 Description D/A conversion is disabled. D/A conversion of channel 0 is enabled and D/A conversion of channel 1 is disabled. Analog output of channel 0 (DA0) is enabled and analog output of channel 1 (DA1) is disabled. 1 0 D/A conversion of channel 0 is disabled and D/A conversion of channel 1 is enabled. Analog output of channel 0 (DA0) is disabled and analog output of channel 1 (DA1) is enabled. 1 D/A conversion of channels 0 and 1 is enabled. Analog output of channels 0 and 1 (DA0 and DA1) is enabled. 1 0 0 D/A conversion of channels 0 and 1 is enabled. Analog output of channels 0 and 1 (DA0 and DA1) is disabled. 1 D/A conversion of channels 0 and 1 is enabled. Analog output of channel 0 (DA0) is enabled and analog output of channel 1 (DA1) is disabled. 1 0 D/A conversion of channels 0 and 1 is enabled. Analog output of channel 0 (DA0) is disabled and analog output of channel 1 (DA1) is enabled. 1 D/A conversion of channels 0 and 1 is enabled. Analog output of channels 0 and 1 (DA0 and DA1) is enabled. Rev.1.00 Jun. 07, 2006 Page 870 of 1102 REJ09B0294-0100 Section 19 D/A Converter 19.4 Operation The D/A converter includes D/A conversion circuits for two channels, each of which can operate independently. When the DAOE bit in DACR01 is set to 1, D/A conversion is enabled and the conversion result is output. An operation example of D/A conversion on channel 0 is shown below. Figure 19.2 shows the timing of this operation. 1. Write the conversion data to DADR0. 2. Set the DAOE0 bit in DACR01 to 1 to start D/A conversion. The conversion result is output from the analog output pin DA0 after the conversion time tDCONV has elapsed. The conversion result continues to be output until DADR0 is written to again or the DAOE0 bit is cleared to 0. The output value is expressed by the following formula: Contents of DADR/256 x Vref 3. If DADR0 is written to again, the conversion is immediately started. The conversion result is output after the conversion time tDCONV has elapsed. 4. If the DAOE0 bit is cleared to 0, analog output is disabled. DADR0 write cycle DACR01 write cycle DADR0 write cycle DACR01 write cycle P Address DADR0 Conversion data 1 Conversion data 2 DAOE0 DA0 High-impedance state tDCONV Conversion result 1 tDCONV Conversion result 2 [Legend] tDCONV: D/A conversion time Figure 19.2 Example of D/A Converter Operation Rev.1.00 Jun. 07, 2006 Page 871 of 1102 REJ09B0294-0100 Section 19 D/A Converter 19.5 19.5.1 Usage Notes Module Stop State Setting Operation of the D/A converter can be disabled or enabled using the module stop control register. The initial setting is for operation of the D/A converter to be halted. Register access is enabled by clearing the module stop state. For details, refer to section 23, Power-Down Modes. 19.5.2 D/A Output Hold Function in Software Standby Mode When this LSI enters software standby mode with D/A conversion enabled, the D/A outputs are retained, and the analog power supply current is equal to as during D/A conversion. If the analog power supply current needs to be reduced in software standby mode, clear the ADST, TRGS1, and TRGS0 bits all to 0 to disable D/A conversion. Rev.1.00 Jun. 07, 2006 Page 872 of 1102 REJ09B0294-0100 Section 20 RAM Section 20 RAM This LSI has a 40-kbyte on-chip high-speed static RAM. The RAM is connected to the CPU by a 32-bit data bus, enabling one-state access by the CPU to all byte data, word data, and longword data. The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control register (SYSCR). For details on SYSCR, refer to section 3.2.2, System Control Register (SYSCR). Product Classification Flash memory version H8SX/1663 H8SX/1664 RAM Size 40 kbytes RAM Addresses H'FF2000 to H'FFBFFF Rev.1.00 Jun. 07, 2006 Page 873 of 1102 REJ09B0294-0100 Section 20 RAM Rev.1.00 Jun. 07, 2006 Page 874 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) Section 21 Flash Memory (0.18-m F-ZTAT Version) The flash memory has the following features. Figure 21.1 is a block diagram of the flash memory. 21.1 * Size Features Product Classification ROM Size 384 kbytes 512 kbytes ROM Address H'000000 to H'05FFFF (modes 2, 6, 7) H'000000 to H'07FFFF (modes 2, 6, 7) H8SX/1663 H8SX/1664 R5F61663 R5F61664 * Programming/erasing interface by the download of on-chip program This LSI has a programming/erasing program. After downloading this program to the on-chip RAM, programming/erasing can be performed by setting the parameters. * Programming/erasing time Programming time: 3 ms (typ) for 128-byte simultaneous programming Erasing time: 2000 ms (typ) per 1 block (64 kbytes) * Number of programming The number of programming can be up to 100 times at the minimum. (1 to 100 times are guaranteed.) * Three on-board programming modes SCI boot mode: Using the on-chip SCI_4, the user MAT can be programmed/erased. In SCI boot mode, the bit rate between the host and this LSI can be adjusted automatically. Using the on-chip USB, the user MAT can be programmed/erased. USB boot mode: User program mode: Using a desired interface, the user MAT can be programmed/erased. * Off-board programming mode Programmer mode: Using a PROM programmer, the user MAT can be programmed/erased. * Programming/erasing protection Protection against programming/erasing of the flash memory can be set by hardware protection, software protection, or error protection. * Flash memory emulation function using the on-chip RAM Realtime emulation of the flash memory programming can be performed by overlaying parts of the flash memory (user MAT) area and the on-chip RAM. Rev.1.00 Jun. 07, 2006 Page 875 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) Internal address bus Internal data bus (32 bits) FCCS Module bus FPCS FECS FKEY FTDAR RAMER Flash memory Control unit Memory MAT unit User MAT: 384 kbytes (H8SX/1663) 512 kbytes (H8SX/1664) Mode pins Operating mode [Legend] FCCS: FPCS: FECS: FKEY: FTDAR: RAMER: Flash code control/status register Flash program code select register Flash erase code select register Flash key code register Flash transfer destination address register RAM emulation register Figure 21.1 Block Diagram of Flash Memory Rev.1.00 Jun. 07, 2006 Page 876 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) 21.2 Mode Transition Diagram When the mode pins are set in the reset state and reset start is performed, this LSI enters each operating mode as shown in figure 21.2. Although the flash memory can be read in user mode, it cannot be programmed or erased. The flash memory can be programmed or erased in boot mode, user program mode, and programmer mode. The differences between boot mode, user program mode, and programmer mode are shown in table 21.1. RES = 0 RES = 0 Programmer Reset state Programmer mode setting mode ROM disabled mode ROM disabled mode setting er Us m od RES =0 S RE =0 in ett es g US B bo ot m RE S I SC RE S = =0 bo ot mo od es 0 de g ttin se ett ing *2 User mode *1 User program mode SCI boot mode USB boot mode RAM emulation can be available On-board programming mode Notes: * In this LSI, the user program mode is defined as the period from the timing when a program concerning programming and erasure is started in user mode to the timing when the program is completed. 1. Programming and erasure is started. 2. Programming and erasure is completed. Figure 21.2 Mode Transition of Flash Memory Rev.1.00 Jun. 07, 2006 Page 877 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) Table 21.1 Differences between Boot Mode, User Program Mode, and Programmer Mode Item Programming/ erasing environment Programming/ erasing enable MAT Programming/ erasing control All erasure SCI boot Mode On-board programming * User MAT USB boot Mode On-board programming * User MAT User Program Mode On-board programming * User MAT Programmer Mode Off-board programming * User MAT Command O (Automatic) 1 Command O (Automatic) O* 1 Programming/ erasing interface O O From desired device via RAM O User MAT Command O (Automatic) Block division erasure O* x Via programmer x Program data transfer From host via SCI From host via USB RAM emulation Reset initiation MAT x Embedded program storage area Changing mode and reset x Embedded program storage area Changing mode and reset Transition to user mode Completing Programming/ 3 erasure* Notes: 1. All-erasure is performed. After that, the specified block can be erased. 2. In this LSI, the user programming mode is defined as the period from the timing when a program concerning programming and erasure is started to the timing when the program is completed. For details on a program concerning programming and erasure, see section 21.7.3, User Program Mode. Rev.1.00 Jun. 07, 2006 Page 878 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) 21.3 21.3.1 Block Structure Block Diagram of H8SX/1663 Figure 21.3 shows the block structure of the 384-kbyte user MAT. The heavy-line frames indicate the erase blocks. The thin-line frames indicate the programming units and the values inside the frames stand for the addresses. The user MAT is divided into five 64-kbyte blocks, one 32-kbyte block, and eight 4-kbyte blocks. The user MAT can be erased in these divided block units. Programming is done in 128-byte units starting from where the lower address is H'00 or H'80. RAM emulation can be performed in the eight 4-kbyte blocks. Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes EB0 Erase unit: 4 kbytes EB1 Erase unit: 4 kbytes EB2 Erase unit: 4 kbytes EB3 Erase unit: 4 kbytes EB4 Erase unit: 4 kbytes EB5 Erase unit: 4 kbytes EB6 Erase unit: 4 kbytes EB7 Erase unit: 4 kbytes EB8 Erase unit: 32 kbytes EB9 Erase unit: 64 kbytes EB10 H'000000 H'000001 H'000002 H'000F80 H'000F81 H'000F82 H'001000 H'001001 H'001002 H'001F80 H'001F81 H'001F82 H'002000 H'002001 H'002002 H'002F80 H'002F81 H'002F82 H'003000 H'003001 H'003002 H'003F80 H'003F81 H'003F82 H'004000 H'004001 H'004002 H'004F80 H'004F81 H'004F82 H'005000 H'005001 H'005002 H'005F80 H'005F81 H'005F82 H'006000 H'006001 H'006002 H'006F80 H'006F81 H'006F82 H'007000 H'007001 H'007002 H'007F80 H'007F81 H'007F82 H'008000 H'008001 H'008002 H'00FF80 H'00FF81 H'00FF82 H'010000 H'010001 H'010002 H'01FF80 H'01FF81 H'01FF82 H'020000 H'020001 H'020002 H'0AFF80 H'0AFF81 H'0AFF82 H'050000 H'050001 H'050002 H'05FF80 H'05FF81 H'05FF82 H'00007F H'000FFF H'00107F H'001FFF H'00207F H'002FFF H'00307F H'003FFF H'00407F H'004FFF H'00507F H'005FFF H'00607F H'006FFF H'00707F H'007FFF H'00807F H'00FFFF H'01007F H'01FFFF H'02007F EB13 Erase unit: 64 kbytes - - - - - - - - - - - - - - H'0AFFFF Programming unit: 128 bytes H'05007F -------------- H'05FFFF Figure 21.3 Block Structure of User MAT Rev.1.00 Jun. 07, 2006 Page 879 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) 21.3.2 Block Diagram of H8SX/1664 Figure 21.4 shows the block structure of the 512-kbyte user MAT. The heavy-line frames indicate the erase blocks. The thin-line frames indicate the programming units and the values inside the frames stand for the addresses. The user MAT is divided into seven 64-kbyte blocks, one 32-kbyte block, and eight 4-kbyte blocks. The user MAT can be erased in these divided block units. Programming is done in 128-byte units starting from where the lower address is H'00 or H'80. RAM emulation can be performed in the eight 4-kbyte blocks. Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes EB0 Erase unit: 4 kbytes EB1 Erase unit: 4 kbytes EB2 Erase unit: 4 kbytes EB3 Erase unit: 4 kbytes EB4 Erase unit: 4 kbytes EB5 Erase unit: 4 kbytes EB6 Erase unit: 4 kbytes EB7 Erase unit: 4 kbytes EB8 Erase unit: 32 kbytes EB9 Erase unit: 64 kbytes EB10 H'000000 H'000001 H'000002 H'000F80 H'000F81 H'000F82 H'001000 H'001001 H'001002 H'001F80 H'001F81 H'001F82 H'002000 H'002001 H'002002 H'002F80 H'002F81 H'002F82 H'003000 H'003001 H'003002 H'003F80 H'003F81 H'003F82 H'004000 H'004001 H'004002 H'004F80 H'004F81 H'004F82 H'005000 H'005001 H'005002 H'005F80 H'005F81 H'005F82 H'006000 H'006001 H'006002 H'006F80 H'006F81 H'006F82 H'007000 H'007001 H'007002 H'007F80 H'007F81 H'007F82 H'008000 H'008001 H'008002 H'00FF80 H'00FF81 H'00FF82 H'010000 H'010001 H'010002 H'01FF80 H'01FF81 H'01FF82 H'020000 H'020001 H'020002 H'0AFF80 H'0AFF81 H'0AFF82 H'070000 H'070001 H'070002 H'07FF80 H'07FF81 H'07FF82 H'00007F H'000FFF H'00107F H'001FFF H'00207F H'002FFF H'00307F H'003FFF H'00407F H'004FFF H'00507F H'005FFF H'00607F H'006FFF H'00707F H'007FFF H'00807F H'00FFFF H'01007F H'01FFFF H'02007F EB15 Erase unit: 64 kbytes - - - - - - - - - - - - - - H'0AFFFF Programming unit: 128 bytes H'07007F -------------- H'07FFFF Figure 21.4 Block Structure of User MAT Rev.1.00 Jun. 07, 2006 Page 880 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) 21.4 Programming/Erasing Interface Programming/erasing of the flash memory is done by downloading an on-chip programming/erasing program to the on-chip RAM and specifying the start address of the programming destination, the program data, and the erase block number using the programming/erasing interface registers and programming/erasing interface parameters. The procedure program for user program mode is made by the user. Figure 21.5 shows the procedure for creating the procedure program. For details, see section 21.7.3, User Program Mode. Start procedure program for programming/erasing Select on-chip program to be downloaded and specify destination Download on-chip program by setting VBR, FKEY, and SCO bit in FCCS Execute initialization (downloaded program execution) Programming (in 128-byte units) or erasing (in 1-block units) (downloaded program execution) Programming/erasing completed? Yes End procedure program No Figure 21.5 Procedure for Creating Procedure Program (1) Selection of On-Chip Program to be Downloaded This LSI has programming/erasing programs which can be downloaded to the on-chip RAM. The on-chip program to be downloaded is selected by the programming/erasing interface registers. The start address of the on-chip RAM where an on-chip program is downloaded is specified by the flash transfer destination address register (FTDAR). Rev.1.00 Jun. 07, 2006 Page 881 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) (2) Download of On-Chip Program The on-chip program is automatically downloaded by setting the flash key code register (FKEY) and the SCO bit in the flash code control/status register (FCCS) after initializing the vector base register (VBR). The memory MAT is replaced with the embedded program storage area during download. Since the memory MAT cannot be read during programming/erasing, the procedure program must be executed in a space other than the flash memory (for example, on-chip RAM). Since the download result is returned to the programming/erasing interface parameter, whether download is normally executed or not can be confirmed. The VBR contents can be changed after completion of download. (3) Initialization of Programming/Erasing A pulse with the specified period must be applied when programming or erasing. The specified pulse width is made by the method in which wait loop is configured by the CPU instruction. Accordingly, the operating frequency of the CPU needs to be set before programming/erasing. The operating frequency of the CPU is set by the programming/erasing interface parameter. (4) Execution of Programming/Erasing The start address of the programming destination and the program data are specified in 128-byte units when programming. The block to be erased is specified with the erase block number in erase-block units when erasing. Specifications of the start address of the programming destination, program data, and erase block number are performed by the programming/erasing interface parameters, and the on-chip program is initiated. The on-chip program is executed by using the JSR or BSR instruction and executing the subroutine call of the specified address in the on-chip RAM. The execution result is returned to the programming/erasing interface parameter. The area to be programmed must be erased in advance when programming flash memory. All interrupts are disabled during programming/erasing. (5) When Programming/Erasing is Executed Consecutively When processing does not end by 128-byte programming or 1-block erasure, consecutive programming/erasing can be realized by updating the start address of the programming destination and program data, or the erase block number. Since the downloaded on-chip program is left in the on-chip RAM even after programming/erasing completes, download and initialization are not required when the same processing is executed consecutively. Rev.1.00 Jun. 07, 2006 Page 882 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) 21.5 Input/Output Pins The flash memory is controlled through the input/output pins shown in table 21.2. Table 21.2 Pin Configuration Abbreviation RES EMLE MD3 to MD0 PM2 TxD4 RxD4 USD+, USD- VBUS PM3 PM4 I/O Input Input Input Input Output Input I/O Input Input Output Function Reset On-chip emulator enable pin (EMLE = 0 for flash memory programming/erasing) Set operating mode of this LSI SCI boot mode/USB boot mode setting (for boot mode setting by MD3 to MD0) Serial transmit data output (used in SCI boot mode) Serial receive data input (used in SCI boot mode) USB data I/O (used in USB boot mode) USB cable connection/disconnection detect (used in USB boot mode) USB bus power mode/self power mode setting (used in USB boot mode) D+ pull-up control (used in USB boot mode) Rev.1.00 Jun. 07, 2006 Page 883 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) 21.6 Register Descriptions The flash memory has the following registers. Programming/Erasing Interface Registers: * Flash code control/status register (FCCS) * Flash program code select register (FPCS) * Flash erase code select register (FECS) * Flash key code register (FKEY) * Flash transfer destination address register (FTDAR) Programming/Erasing Interface Parameters: * Download pass and fail result parameter (DPFR) * Flash pass and fail result parameter (FPFR) * Flash program/erase frequency parameter (FPEFEQ) * Flash multipurpose address area parameter (FMPAR) * Flash multipurpose data destination area parameter (FMPDR) * Flash erase block select parameter (FEBS) * RAM emulation register (RAMER) There are several operating modes for accessing the flash memory. Respective operating modes, registers, and parameters are assigned to the user MAT. The correspondence between operating modes and registers/parameters for use is shown in table 21.3. Rev.1.00 Jun. 07, 2006 Page 884 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) Table 21.3 Registers/Parameters and Target Modes Register/Parameter Programming/ erasing interface registers FCCS FPCS FECS FKEY FTDAR Programming/ erasing interface parameters DPFR FPFR Download O O O O O O Initialization O O Programming Erasure O O O O O O O Read RAM Emulation O FPEFEQ FMPAR FMPDR FEBS RAM emulation RAMER 21.6.1 Programming/Erasing Interface Registers The programming/erasing interface registers are 8-bit registers that can be accessed only in bytes. These registers are initialized by a power-on reset. (1) Flash Code Control/Status Register (FCCS) FCCS monitors errors during programming/erasing the flash memory and requests the on-chip program to be downloaded to the on-chip RAM. Bit Bit Name Initial Value R/W 7 1 R 6 0 R 5 0 R 4 FLER 0 R 3 0 R 2 0 R 1 0 R 0 SCO 0 (R)/W Rev.1.00 Jun. 07, 2006 Page 885 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) Bit 7 6 5 4 Initial Bit Name Value FLER 1 0 0 0 R/W R R R R Description Reserved These are read-only bits and cannot be modified. Flash Memory Error Indicates that an error has occurred during programming or erasing the flash memory. When this bit is set to 1, the flash memory enters the error protection state. When this bit is set to 1, high voltage is applied to the internal flash memory. To reduce the damage to the flash memory, the reset must be released after the reset input period (period of RES = 0) of at least 100 s. 0: Flash memory operates normally (Error protection is invalid) [Clearing condition] * At a power-on reset 1: An error occurs during programming/erasing flash memory (Error protection is valid) [Setting conditions] * * When an interrupt, such as NMI, occurs during programming/erasing. When the flash memory is read during programming/erasing (including a vector read and an instruction fetch). When the SLEEP instruction is executed during programming/erasing (including software standby mode). When a bus master other than the CPU, such as the DMAC and DTC, obtains bus mastership during programming/erasing. * * 3 to 1 All 0 R Reserved These are read-only bits and cannot be modified. Rev.1.00 Jun. 07, 2006 Page 886 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) Bit 0 Initial Bit Name Value SCO 0 R/W (R)/W* Description Source Program Copy Operation Requests the on-chip programming/erasing program to be downloaded to the on-chip RAM. When this bit is set to 1, the on-chip program which is selected by FPCS or FECS is automatically downloaded in the on-chip RAM area specified by FTDAR. In order to set this bit to 1, the RAM emulation mode must be canceled, H'A5 must be written to FKEY, and this operation must be executed in the on-chip RAM. Dummy read of FCCS must be executed twice immediately after setting this bit to 1. All interrupts must be disabled during download. This bit is cleared to 0 when download is completed. During program download initiated with this bit, particular processing which accompanies bankswitching of the program storage area is executed. Before a download request, initialize the VBR contents to H'00000000. After download is completed, the VBR contents can be changed. 0: Download of the programming/erasing program is not requested. [Clearing condition] * When download is completed 1: Download of the programming/erasing program is requested. [Setting conditions] (When all of the following conditions are satisfied) * * * Not in RAM emulation mode (the RAMS bit in RAMER is cleared to 0) H'A5 is written to FKEY Setting of this bit is executed in the on-chip RAM Note: * This is a write-only bit. This bit is always read as 0. Rev.1.00 Jun. 07, 2006 Page 887 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) (2) Flash Program Code Select Register (FPCS) FPCS selects the programming program to be downloaded. Bit Bit Name Initial Value R/W 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 PPVS 0 R/W Bit 7 to 1 0 Initial Bit Name Value PPVS All 0 0 R/W R R/W Description Reserved These are read-only bits and cannot be modified. Program Pulse Verify Selects the programming program to be downloaded. 0: Programming program is not selected. [Clearing condition] When transfer is completed 1: Programming program is selected. (3) Flash Erase Code Select Register (FECS) FECS selects the erasing program to be downloaded. Bit Bit Name Initial Value R/W 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 EPVB 0 R/W Bit 7 to 1 0 Initial Bit Name Value EPVB All 0 0 R/W R R/W Description Reserved These are read-only bits and cannot be modified. Erase Pulse Verify Block Selects the erasing program to be downloaded. 0: Erasing program is not selected. [Clearing condition] When transfer is completed 1: Erasing program is selected. Rev.1.00 Jun. 07, 2006 Page 888 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) (4) Flash Key Code Register (FKEY) FKEY is a register for software protection that enables to download the on-chip program and perform programming/erasing of the flash memory. Bit Bit Name Initial Value R/W 7 K7 0 R/W 6 K6 0 R/W 5 K5 0 R/W 4 K4 0 R/W 3 K3 0 R/W 2 K2 0 R/W 1 K1 0 R/W 0 K0 0 R/W Bit 7 6 5 4 3 2 1 0 Initial Bit Name Value K7 K6 K5 K4 K3 K2 K1 K0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Key Code When H'A5 is written to FKEY, writing to the SCO bit in FCCS is enabled. When a value other than H'A5 is written, the SCO bit cannot be set to 1. Therefore, the on-chip program cannot be downloaded to the on-chip RAM. Only when H'5A is written can programming/erasing of the flash memory be executed. When a value other than H'5A is written, even if the programming/erasing program is executed, programming/erasing cannot be performed. H'A5: Writing to the SCO bit is enabled. (The SCO bit cannot be set to 1 when FKEY is a value other than H'A5.) H'5A: Programming/erasing of the flash memory is enabled. (When FKEY is a value other than H'A5, the software protection state is entered.) H'00: Initial value Rev.1.00 Jun. 07, 2006 Page 889 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) (5) Flash Transfer Destination Address Register (FTDAR) FTDAR specifies the start address of the on-chip RAM at which to download an on-chip program. FTDAR must be set before setting the SCO bit in FCCS to 1. Bit Bit Name Initial Value R/W 7 TDER 0 R/W 6 TDA6 0 R/W 5 TDA5 0 R/W 4 TDA4 0 R/W 3 TDA3 0 R/W 2 TDA2 0 R/W 1 TDA1 0 R/W 0 TDA0 0 R/W Bit 7 Initial Bit Name Value TDER 0 R/W R/W Description Transfer Destination Address Setting Error This bit is set to 1 when an error has occurred in setting the start address specified by bits TDA6 to TDA0. A start address error is determined by whether the value set in bits TDA6 to TDA0 is within the range of H'00 to H'02 when download is executed by setting the SCO bit in FCCS to 1. Make sure that this bit is cleared to 0 before setting the SCO bit to 1 and the value specified by bits TDA6 to TDA0 should be within the range of H'00 to H'02. 0: The value specified by bits TDA6 to TDA0 is within the range. 1: The value specified by bits TDA6 to TDA0 is between H'03 and H'FF and download has stopped. 6 5 4 3 2 1 0 TDA6 TDA5 TDA4 TDA3 TDA2 TDA1 TDA0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W Transfer Destination Address Specifies the on-chip RAM start address of the download destination. A value between H'00 and H'02, and up to 4 kbytes can be specified as the start address of the on-chip RAM. H'00: H'01: H'02: H'FF9000 is specified as the start address. H'FFA000 is specified as the start address. H'FFB000 is specified as the start address. H'03 to H'7F: Setting prohibited. (Specifying a value from H'03 to H'7F sets the TDER bit to 1 and stops download of the on-chip program.) Rev.1.00 Jun. 07, 2006 Page 890 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) 21.6.2 Programming/Erasing Interface Parameters The programming/erasing interface parameters specify the operating frequency, storage place for program data, start address of programming destination, and erase block number, and exchanges the execution result. These parameters use the general registers of the CPU (ER0 and ER1) or the on-chip RAM area. The initial values of programming/erasing interface parameters are undefined at a power-on reset or a transition to software standby mode. Since registers of the CPU except for R0 are saved in the stack area during download of an onchip program, initialization, programming, or erasing, allocate the stack area before performing these operations (the maximum stack size is 128 bytes). The return value of the processing result is written in R0. The programming/erasing interface parameters are used in download control, initialization before programming or erasing, programming, and erasing. Table 21.4 shows the usable parameters and target modes. The meaning of the bits in the flash pass and fail result parameter (FPFR) varies in initialization, programming, and erasure. Table 21.4 Parameters and Target Modes Parameter DPFR FPFR FPEFEQ FMPAR FMPDR FEBS Download Initialization Programming Erasure R/W R/W R/W R/W R/W R/W R/W Initial Value Undefined Undefined Undefined Undefined Undefined Undefined Allocation On-chip RAM* R0L of CPU ER0 of CPU ER1 of CPU ER0 of CPU ER0 of CPU O O * O O O O O O O Note: A single byte of the start address of the on-chip RAM specified by FTDAR Download Control: The on-chip program is automatically downloaded by setting the SCO bit in FCCS to 1. The on-chip RAM area to download the on-chip program is the 4-kbyte area starting from the start address specified by FTDAR. Download is set by the programming/erasing interface registers, and the download pass and fail result parameter (DPFR) indicates the return value. Rev.1.00 Jun. 07, 2006 Page 891 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) Initialization before Programming/Erasing: The on-chip program includes the initialization program. A pulse with the specified period must be applied when programming or erasing. The specified pulse width is made by the method in which wait loop is configured by the CPU instruction. Accordingly, the operating frequency of the CPU must be set. The initial program is set as a parameter of the programming/erasing program which has been downloaded to perform these settings. Programming: When the flash memory is programmed, the start address of the programming destination on the user MAT and the program data must be passed to the programming program. The start address of the programming destination on the user MAT must be stored in general register ER1. This parameter is called the flash multipurpose address area parameter (FMPAR). The program data is always in 128-byte units. When the program data does not satisfy 128 bytes, 128-byte program data is prepared by filling the dummy code (H'FF). The boundary of the start address of the programming destination on the user MAT is aligned at an address where the lower eight bits (A7 to A0) are H'00 or H'80. The program data for the user MAT must be prepared in consecutive areas. The program data must be in a consecutive space which can be accessed using the MOV.B instruction of the CPU and is not in the flash memory space. The start address of the area that stores the data to be written in the user MAT must be set in general register ER0. This parameter is called the flash multipurpose data destination area parameter (FMPDR). For details on the programming procedure, see section 21.7.3, User Program Mode. Erasure: When the flash memory is erased, the erase block number on the user MAT must be passed to the erasing program which is downloaded. The erase block number on the user MAT must be set in general register ER0. This parameter is called the flash erase block select parameter (FEBS). One block is selected from the block numbers of 0 to 13 as the erase block number. For details on the erasing procedure, see section 21.7.3, User Program Mode. Rev.1.00 Jun. 07, 2006 Page 892 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) (1) Download Pass and Fail Result Parameter (DPFR: Single Byte of Start Address in OnChip RAM Specified by FTDAR) DPFR indicates the return value of the download result. The DPFR value is used to determine the download result. Bit Bit Name 7 6 5 4 3 2 SS 1 FK 0 SF Bit 7 to 3 2 Initial Bit Name Value SS R/W R/W Description Unused These bits return 0. Source Select Error Detect Only one type can be specified for the on-chip program which can be downloaded. When the program to be downloaded is not selected, more than two types of programs are selected, or a program which is not mapped is selected, an error occurs. 0: Download program selection is normal 1: Download program selection is abnormal 1 FK R/W Flash Key Register Error Detect Checks the FKEY value (H'A5) and returns the result. 0: FKEY setting is normal (H'A5) 1: FKEY setting is abnormal (value other than H'A5) 0 SF R/W Success/Fail Returns the download result. Reads back the program downloaded to the on-chip RAM and determines whether it has been transferred to the on-chip RAM. 0: Download of the program has ended normally (no error) 1: Download of the program has ended abnormally (error occurs) Rev.1.00 Jun. 07, 2006 Page 893 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) (2) Flash Pass and Fail Parameter (FPFR: General Register R0L of CPU) FPFR indicates the return values of the initialization, programming, and erasure results. The meaning of the bits in FPFR varies depending on the processing. (a) Initialization before programming/erasing FPFR indicates the return value of the initialization result. Bit Bit Name 7 6 5 4 3 2 1 FQ 0 SF Bit 7 to 2 1 Bit Name FQ Initial Value R/W R/W Description Unused These bits return 0. Frequency Error Detect Compares the specified CPU operating frequency with the operating frequencies supported by this LSI, and returns the result. 0: Setting of operating frequency is normal 1: Setting of operating frequency is abnormal 0 SF R/W Success/Fail Returns the initialization result. 0: Initialization has ended normally (no error) 1: Initialization has ended abnormally (error occurs) (b) Programming FPFR indicates the return value of the programming result. Bit Bit Name 7 6 MD 5 EE 4 FK 3 2 WD 1 WA 0 SF Bit 7 Bit Name Initial Value R/W Description Unused Returns 0. Rev.1.00 Jun. 07, 2006 Page 894 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) Bit 6 Bit Name MD Initial Value R/W R/W Description Programming Mode Related Setting Error Detect Detects the error protection state and returns the result. When the error protection state is entered, this bit is set to 1. Whether the error protection state is entered or not can be confirmed with the FLER bit in FCCS. For conditions to enter the error protection state, see section 21.8.3, Error Protection. 0: Normal operation (FLER = 0) 1: Error protection state, and programming cannot be performed (FLER = 1) 5 EE R/W Programming Execution Error Detect Writes 1 to this bit when the specified data could not be written because the user MAT was not erased. If this bit is set to 1, there is a high possibility that the user MAT has been written to partially. In this case, after removing the error factor, erase the user MAT. 0: Programming has ended normally 1: Programming has ended abnormally (programming result is not guaranteed) 4 FK R/W Flash Key Register Error Detect Checks the FKEY value (H'5A) before programming starts, and returns the result. 0: FKEY setting is normal (H'5A) 1: FKEY setting is abnormal (value other than H'5A) 3 2 WD R/W Unused Returns 0. Write Data Address Detect When an address not in the flash memory area is specified as the start address of the storage destination for the program data, an error occurs. 0: Setting of the start address of the storage destination for the program data is normal 1: Setting of the start address of the storage destination for the program data is abnormal Rev.1.00 Jun. 07, 2006 Page 895 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) Bit 1 Initial Bit Name Value WA R/W R/W Description Write Address Error Detect When the following items are specified as the start address of the programming destination, an error occurs. * An area other than flash memory * The specified address is not aligned with the 128byte boundary (lower eight bits of the address are other than H'00 and H'80) 0: Setting of the start address of the programming destination is normal 1: Setting of the start address of the programming destination is abnormal Success/Fail Returns the programming result. 0: Programming has ended normally (no error) 1: Programming has ended abnormally (error occurs) 0 SF R/W (c) Erasure FPFR indicates the return value of the erasure result. Bit Bit Name 7 6 MD 5 EE 4 FK 3 EB 2 1 0 SF Bit 7 6 Initial Bit Name Value MD R/W R/W Description Unused Returns 0. Erasure Mode Related Setting Error Detect Detects the error protection state and returns the result. When the error protection state is entered, this bit is set to 1. Whether the error protection state is entered or not can be confirmed with the FLER bit in FCCS. For conditions to enter the error protection state, see section 21.8.3, Error Protection. 0: Normal operation (FLER = 0) 1: Error protection state, and programming cannot be performed (FLER = 1) Rev.1.00 Jun. 07, 2006 Page 896 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) Bit 5 Initial Bit Name Value EE R/W R/W Description Erasure Execution Error Detect Returns 1 when the user MAT could not be erased or when the flash memory related register settings are partially changed. If this bit is set to 1, there is a high possibility that the user MAT has been erased partially. In this case, after removing the error factor, erase the user MAT. 0: Erasure has ended normally 1: Erasure has ended abnormally 4 FK R/W Flash Key Register Error Detect Checks the FKEY value (H'5A) before erasure starts, and returns the result. 0: FKEY setting is normal (H'5A) 1: FKEY setting is abnormal (value other than H'5A) 3 EB R/W Erase Block Select Error Detect Checks whether the specified erase block number is in the block range of the user MAT, and returns the result. 0: Setting of erase block number is normal 1: Setting of erase block number is abnormal 2, 1 0 SF R/W Unused These bits return 0. Success/Fail Indicates the erasure result. 0: Erasure has ended normally (no error) 1: Erasure has ended abnormally (error occurs) Rev.1.00 Jun. 07, 2006 Page 897 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) (3) Flash Program/Erase Frequency Parameter (FPEFEQ: General Register ER0 of CPU) FPEFEQ sets the operating frequency of the CPU. The operating frequency available in this LSI ranges from 8 MHz to 50 MHz. Bit Bit Name Bit Bit Name Bit Bit Name Bit Bit Name 31 23 15 F15 7 F7 30 22 14 F14 6 F6 29 21 13 F13 5 F5 28 20 12 F12 4 F4 27 19 11 F11 3 F3 26 18 10 F10 2 F2 25 17 9 F9 1 F1 24 16 8 F8 0 F0 Bit Initial Bit Name Value R/W R/W Description Unused These bits should be cleared to 0. Frequency Set These bits set the operating frequency of the CPU. When the PLL multiplication function is used, set the multiplied frequency. The setting value must be calculated as follows: 1. The operating frequency shown in MHz units must be rounded in a number of three decimal places and be shown in a number of two decimal places. 2. The value multiplied by 100 is converted to the binary digit and is written to FPEFEQ (general register ER0). For example, when the operating frequency of the CPU is 35.000 MHz, the value is as follows: 1. The number of three decimal places of 35.000 is rounded. 2. The formula of 35.00 x 100 = 3500 is converted to the binary digit and B'0000 1101 1010 1100 (H'0DAC) is set to ER0. 31 to 16 15 to 0 F15 to F0 Rev.1.00 Jun. 07, 2006 Page 898 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) (4) Flash Multipurpose Address Area Parameter (FMPAR: General Register ER1 of CPU) FMPAR stores the start address of the programming destination on the user MAT. When an address in an area other than the flash memory is set, or the start address of the programming destination is not aligned with the 128-byte boundary, an error occurs. The error occurrence is indicated by the WA bit in FPFR. Bit Bit Name 31 MOA31 30 MOA30 29 MOA29 28 MOA28 27 MOA27 26 MOA26 25 MOA25 24 MOA24 Bit Bit Name 23 MOA23 22 MOA22 21 MOA21 20 MOA20 19 MOA19 18 MOA18 17 MOA17 16 MOA16 Bit Bit Name 15 MOA15 14 MOA14 13 MOA13 12 MOA12 11 MOA11 10 MOA10 9 MOA9 8 MOA8 Bit Bit Name 7 MOA7 6 MOA6 5 MOA5 4 MOA4 3 MOA3 2 MOA2 1 MOA1 0 MOA0 Bit 31 to 0 Initial Bit Name Value MOA31 to MOA0 R/W R/W Description These bits store the start address of the programming destination on the user MAT. Consecutive 128-byte programming is executed starting from the specified start address of the user MAT. Therefore, the specified start address of the programming destination becomes a 128-byte boundary, and MOA6 to MOA0 are always cleared to 0. Rev.1.00 Jun. 07, 2006 Page 899 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) (5) Flash Multipurpose Data Destination Parameter (FMPDR: General Register ER0 of CPU) FMPDR stores the start address in the area which stores the data to be programmed in the user MAT. When the storage destination for the program data is in flash memory, an error occurs. The error occurrence is indicated by the WD bit in FPFR. Bit Bit Name 31 MOD31 30 MOD30 29 MOD29 28 MOD28 27 MOD27 26 MOD26 25 MOD25 24 MOD24 Bit Bit Name 23 MOD23 22 MOD22 21 MOD21 20 MOD20 19 MOD19 18 MOD18 17 MOD17 16 MOD16 Bit Bit Name 15 MOD15 14 MOD14 13 MOD13 12 MOD12 11 MOD11 10 MOD10 9 MOD9 8 MOD8 Bit Bit Name 7 MOD7 6 MOD6 5 MOD5 4 MOD4 3 MOD3 2 MOD2 1 MOD1 0 MOD0 Bit 31 to 0 Initial Bit Name Value MOD31 to MOD0 R/W R/W Description These bits store the start address of the area which stores the program data for the user MAT. Consecutive 128-byte data is programmed to the user MAT starting from the specified start address. Rev.1.00 Jun. 07, 2006 Page 900 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) (6) Flash Erase Block Select Parameter (FEBS: General Register ER0 of CPU) * H8SX/1663 FEBS specifies the erase block number. Settable values range from 0 to 13 (H'0000 to H'000D). A value of 0 corresponds to block EB0 and a value of 13 corresponds to block EB13. An error occurs when a value over the range (from 0 to 13) is set. * H8SX/1664 FEBS specifies the erase block number. Settable values range from 0 to 15 (H'0000 to H'000F). A value of 0 corresponds to block EB0 and a value of 15 corresponds to block EB15. An error occurs when a value over the range (from 0 to 15) is set. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W 15 R/W 14 R/W 13 R/W 12 R/W 11 R/W 10 R/W 9 R/W 8 R/W 23 R/W 22 R/W 21 R/W 20 R/W 19 R/W 18 R/W 17 R/W 16 31 30 29 28 27 26 25 24 Rev.1.00 Jun. 07, 2006 Page 901 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) 21.6.3 RAM Emulation Register (RAMER) RAMER specifies the user MAT area overlaid with part of the on-chip RAM (H'FFA000 to H'FFAFFF) when performing emulation of programming the user MAT. RAMER should be set in user mode or user program mode. To ensure dependable emulation, the memory MAT to be emulated must not be accessed immediately after changing the RAMER contents. When accessed at such a timing, correct operation is not guaranteed. Bit Bit Name Initial Value R/W 7 0 R 6 0 R 5 0 R 4 0 R 3 RAMS 0 R/W 2 RAM2 0 R/W 1 RAM1 0 R/W 0 RAM0 0 R/W Bit 7 to 4 3 Initial Bit Name Value RAMS 0 0 R/W R R/W Description Reserved These are read-only bits and cannot be modified. RAM Select Selects the function which emulates the flash memory using the on-chip RAM. 0: Disables RAM emulation function 1: Enables RAM emulation function (all blocks of the user MAT are protected against programming and erasing) 2 1 0 RAM2 RAM1 RAM0 0 0 0 R/W R/W R/W Flash Memory Area Select These bits select the user MAT area overlaid with the on-chip RAM when RAMS = 1. The following areas correspond to the 4-kbyte erase blocks. 000: H'000000 to H'000FFF (EB0) 001: H'001000 to H'001FFF (EB1) 010: H'002000 to H'002FFF (EB2) 011: H'003000 to H'003FFF (EB3) 100: H'004000 to H'004FFF (EB4) 101: H'005000 to H'005FFF (EB5) 110: H'006000 to H'006FFF (EB6) 111: H'007000 to H'007FFF (EB7) Rev.1.00 Jun. 07, 2006 Page 902 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) 21.7 On-Board Programming Mode When the mode pins (MD0, MD1, MD2, and MD3) are set to on-board programming mode and the reset start is executed, a transition is made to on-board programming mode in which the onchip flash memory can be programmed/erased. On-board programming mode has three operating modes: SCI boot mode by PM2 setting, USB boot mode, and user program mode. Table 21.5 shows the pin setting for each operating mode. For details on the state transition of each operating mode for flash memory, see Figure 21.2. Table 21.5 On-Board Programming Mode Setting Mode Setting SCI boot mode USB boot mode User program mode 1 1 EMLE 0 MD3 0 MD2 0 MD1 1 MD0 0 PM2 0 1 21.7.1 SCI Boot Mode SCI boot mode executes programming/erasing of the user MAT by means of the control command and program data transmitted from the externally connected host via the on-chip SCI_4. In SCI boot mode, the tool for transmitting the control command and program data, and the program data must be prepared in the host. The serial communication mode is set to asynchronous mode. The system configuration in SCI boot mode is shown in figure 21.6. Interrupts are ignored in SCI boot mode. Configure the user system so that interrupts do not occur. This LSI PM2 MD3 to MD0 0 0010 Host Control command, program data Software for analyzing control commands (on-chip) Flash memory Programming tool and program data Response RxD4 SCI_4 TxD4 On-chip RAM Figure 21.6 System Configuration in SCI Boot Mode Rev.1.00 Jun. 07, 2006 Page 903 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) (1) Serial Interface Setting by Host The SCI_4 is set to asynchronous mode, and the serial transmit/receive format is set to 8-bit data, one stop bit, and no parity. When a transition to SCI boot mode is made, the boot program embedded in this LSI is initiated. When the boot program is initiated, this LSI measures the low period of asynchronous serial communication data (H'00) transmitted consecutively by the host, calculates the bit rate, and adjusts the bit rate of the SCI_4 to match that of the host. When bit rate adjustment is completed, this LSI transmits 1 byte of H'00 to the host as the bit adjustment end sign. When the host receives this bit adjustment end sign normally, it transmits 1 byte of H'55 to this LSI. When reception is not executed normally, initiate boot mode again. The bit rate may not be adjusted within the allowable range depending on the combination of the bit rate of the host and the system clock frequency of this LSI. Therefore, the transfer bit rate of the host and the system clock frequency of this LSI must be as shown in table 21.6. Start bit D0 D1 D2 D3 D4 D5 D6 D7 Stop bit Measure low period (9 bits) (data is H'00) High period of at least 1 bit Figure 21.7 Automatic-Bit-Rate Adjustment Operation Table 21.6 System Clock Frequency for Automatic-Bit-Rate Adjustment Bit Rate of Host 9,600 bps 19,200 bps System Clock Frequency of This LSI 8 to 18 MHz 8 to 18 MHz Rev.1.00 Jun. 07, 2006 Page 904 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) (2) State Transition Diagram The state transition after SCI boot mode is initiated is shown in figure 21.8. (Bit rate adjustment) H'00, ..., H'00 reception Boot mode initiation (reset by boot mode) H'00 transmission (adjustment completed) Bit rate adjustment H'55 re ion cept 1. Inquiry command reception 2. Wait for inquiry setting command Inquiry command response Processing of inquiry setting command 3. All user MAT erasure 4. Wait for inquiry programming/erasing command (Era Read/check command reception Processing of read/check command Command response (Er com asure sur s ma e co nd electio mp rec letio ept n n) ion ) (Erase-block specification) Wait for inquiry programming/erasing command (Programming completion) (Program selection command reception) (Program data transmission) Wait for inquiry programming/erasing command Figure 21.8 SCI Boot Mode State Transition Diagram Rev.1.00 Jun. 07, 2006 Page 905 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) 1. After SCI boot mode is initiated, the bit rate of the SCI_4 is adjusted with that of the host. 2. Inquiry information about the size, configuration, start address, and support status of the user MAT is transmitted to the host. 3. After inquiries have finished, all user MAT are automatically erased. 4. When the program preparation notice is received, the state of waiting for program data is entered. The start address of the programming destination and program data must be transmitted after the programming command is transmitted. When programming is finished, the start address of the programming destination must be set to H'FFFFFFFF and transmitted. Then the state of waiting for program data is returned to the state of waiting for programming/erasing command. When the erasure preparation notice is received, the state of waiting for erase block data is entered. The erase block number must be transmitted after the erasing command is transmitted. When the erasure is finished, the erase block number must be set to H'FF and transmitted. Then the state of waiting for erase block data is returned to the state of waiting for programming/erasing command. Erasure must be executed when the specified block is programmed without a reset start after programming is executed in SCI boot mode. When programming can be executed by only one operation, all blocks are erased before entering the state of waiting for programming/erasing command or another command. Thus, in this case, the erasing operation is not required. The commands other than the programming/erasing command perform sum check, blank check (erasure check), and memory read of the user MAT and acquisition of current status information. Memory read of the user MAT can only read the data programmed after all user MAT has automatically been erased. No other data can be read. Rev.1.00 Jun. 07, 2006 Page 906 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) 21.7.2 USB Boot Mode USB boot mode executes programming/erasing of the user MAT by means of the control command and program data transmitted from the externally connected host via the USB. In USB boot mode, the tool for transmitting the control command and program data, and the program data must be prepared in the host. The system configuration in USB boot mode is shown in figure 21.9. Interrupts are ignored in USB boot mode. Configure the user system so that interrupts do not occur. Host or self-power HUB PM4 Software for analyzing control commands (on-chip) This LSI PM2 MD3 to MD0 1 0010 Flash memory 1.5 k Rs Programming tool and program data Rs Data transmission/ reception VBUS PM3 USB+ USBUSB On-chip RAM 0: Self power setting 1: Bus power setting Figure 21.9 System Configuration in USB Boot Mode Rev.1.00 Jun. 07, 2006 Page 907 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) (1) Features * Bus power mode and self power mode are selectable. * The PM4 pin supports the D+ pull-up control connection. * For enumeration information, refer to table 21.7. Table 21.7 Enumeration Information USB standard Transfer mode Maximum power consumption Ver.2.0 (Full speed) Transfer mode Control (in, out), Bulk (in, out) For self power mode (PM3 = 0) For bus power mode (PM3 = 1) Endpoint configuration EP0 Control (in out) 8 bytes Configuration 1 InterfaceNumber0 AlternateSetting0 EP1 Bulk (out) 64 bytes EP2 Bulk (in) 64 bytes 100 mA 500 mA Rev.1.00 Jun. 07, 2006 Page 908 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) (2) State Transition Diagram The state transition after USB boot mode is initiated is shown in figure 21.10. Boot mode initiation (reset by boot mode) H'55 rece ption Enumeration 1. Inquiry command reception 2. Wait for inquiry setting command Inquiry command response Processing of inquiry setting command 3. All user MAT erasure 4. Wait for inquiry programming/erasing command (Era Read/check command reception Processing of read/check command Command response (Er com asure sur s ma e co nd electio mp rec letio ept n n) ion ) (Erase-block specification) Wait for inquiry programming/erasing command (Programming completion) (Program selection command reception) (Program data transmission) Wait for inquiry programming/erasing command Figure 21.10 USB Boot Mode State Transition Diagram Rev.1.00 Jun. 07, 2006 Page 909 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) 1. After a transition to the USB boot mode is made, the boot program embedded in this LSI is initialized. This LSI performs enumeration to the host after the USB boot program is initialized. 2. Inquiry information about the size, configuration, start address, and support status of the user MAT is transmitted to the host. 3. After inquiries have finished, all user MAT are automatically erased. 4. After all user MAT are automatically erased, the state of waiting for programming/erasing command is entered. When the programming command is received, the state shifts to the state of waiting for programming data. The same applies to erasing. In addition to the commands for programming/erasing, there are commands for performing sum check, blank check (erasure check), and memory read of the user MAT, and acquiring the current status information. (3) Notes on USB Boot Mode Execution * The clock of 48 MHz needs to be supplied to the USB module. Set the external clock frequency and clock pulse generator so as to supply 48 MHz as the clock for the USB (cku). For details, refer to section 22, Clock Pulse Generator. * Use the PM4 pin for the D+ pull-up control connection. * For the stable supply of the power during the flash memory programming and erasing, the cable should not be connected via the bus powered HUB. * If the bus powered HUB is disconnected during the flash memory programming and erasing, permanent damage to the LSI may result. * If the USB bus in the bus power mode enters the suspend mode, this does not make the transition to the software standby mode in the power-down state. Rev.1.00 Jun. 07, 2006 Page 910 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) 21.7.3 User Program Mode Programming/erasing of the user MAT is executed by downloading an on-chip program. The programming/erasing flow is shown in figure 21.11. Since high voltage is applied to the internal flash memory during programming/erasing, a transition to the reset state or hardware standby mode must not be made during programming/erasing. A transition to the reset state or hardware standby mode during programming/erasing may damage the flash memory. If a reset is input, the reset must be released after the reset input period (period of RES = 0) of at least 100 s. Programming/erasing start 1. Exit RAM emulation mode beforehand. Download is not allowed in emulation mode. 2. When the program data is adjusted in emulation mode, select the download destination specified by FTDAR carefully. Make sure that the download area does not overlap the emulation area. 3. Programming/erasing is executed only in the on-chip RAM. 4. After programming/erasing is finished, protect the flash memory by the hardware protection. When programming, program data is prepared Programming/erasing procedure program is transferred to the on-chip RAM and executed Programming/erasing end Figure 21.11 Programming/Erasing Flow Rev.1.00 Jun. 07, 2006 Page 911 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) (1) On-Chip RAM Address Map when Programming/Erasing is Executed Parts of the procedure program that is made by the user, like download request, programming/erasing procedure, and decision of the result, must be executed in the on-chip RAM. Since the on-chip program to be downloaded is embedded in the on-chip RAM, make sure the onchip program and procedure program do not overlap. Figure 21.12 shows the area of the on-chip program to be downloaded. DPFR (Return value: 1 byte) System use area (15 bytes) Area to be downloaded (size: 4 kbytes) Unusable area during programming/erasing Programming/erasing program entry Initialization program entry Initialization + programming program or Initialization + erasing program RAM emulation area or area that can be used by user Area that can be used by user FTDAR setting + 4 kbytes FTDAR setting + 16 bytes FTDAR setting FTDAR setting + 32 bytes H'FFBFFF Figure 21.12 RAM Map when Programming/Erasing is Executed Rev.1.00 Jun. 07, 2006 Page 912 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) (2) Programming Procedure in User Program Mode The procedures for download of the on-chip program, initialization, and programming are shown in figure 21.13. Start programming procedure program Select on-chip program to be downloaded and specify download destination by FTDAR Set FKEY to H'A5 1 Disable interrupts and bus master operation other than CPU Set FKEY to H'5A 2. Set parameters to ER1 and ER0 (FMPAR and FMPDR) Programming JSR FTDAR setting + 16 FPFR = 1? Yes 1. 9. 10. Set SCO to 1 after initializing VBR and execute download Download 3. 11. Clear FKEY to 0 4. Programming 12. 13. No Clear FKEY and programming error processing 14. DPFR = 0? Yes Set the FPEFEQ parameter Initialization 5. No Download error processing 6. 7. No Initialization JSR FTDAR setting + 32 Required data programming is completed? Yes FPFR = 0? Yes 8. No Initialization error processing Clear FKEY to 0 End programming procedure program 15. 1 Figure 21.13 Programming Procedure in User Program Mode Rev.1.00 Jun. 07, 2006 Page 913 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) The procedure program must be executed in an area other than the flash memory to be programmed. Setting the SCO bit in FCCS to 1 to request download must be executed in the onchip RAM. The area that can be executed in the steps of the procedure program (on-chip RAM, user MAT, and external space) is shown in section 21.7.4, On-Chip Program and Storable Area for Program Data. The following description assumes that the area to be programmed on the user MAT is erased and that program data is prepared in the consecutive area. The program data for one programming operation is always 128 bytes. When the program data exceeds 128 bytes, the start address of the programming destination and program data parameters are updated in 128-byte units and programming is repeated. When the program data is less than 128 bytes, invalid data is filled to prepare 128-byte program data. If the invalid data to be added is H'FF, the program processing time can be shortened. 1. Select the on-chip program to be downloaded and the download destination. When the PPVS bit in FPCS is set to 1, the programming program is selected. Several programming/erasing programs cannot be selected at one time. If several programs are selected, a download error is returned to the SS bit in the DPFR parameter. The on-chip RAM start address of the download destination is specified by FTDAR. 2. Write H'A5 in FKEY. If H'A5 is not written to FKEY, the SCO bit in FCCS cannot be set to 1 to request download of the on-chip program. 3. After initializing VBR to H'00000000, set the SCO bit to 1 to execute download. To set the SCO bit to 1, all of the following conditions must be satisfied. RAM emulation mode has been canceled. H'A5 is written to FKEY. Setting the SCO bit is executed in the on-chip RAM. When the SCO bit is set to 1, download is started automatically. Since the SCO bit is cleared to 0 when the procedure program is resumed, the SCO bit cannot be confirmed to be 1 in the procedure program. The download result can be confirmed by the return value of the DPFR parameter. To prevent incorrect decision, before setting the SCO bit to 1, set one byte of the on-chip RAM start address specified by FTDAR, which becomes the DPFR parameter, to a value other than the return value (e.g. H'FF). Since particular processing that is accompanied by bank switching as described below is performed when download is executed, initialize the VBR contents to H'00000000. Dummy read of FCCS must be performed twice immediately after the SCO bit is set to 1. The user-MAT space is switched to the on-chip program storage area. After the program to be downloaded and the on-chip RAM start address specified by FTDAR are checked, they are transferred to the on-chip RAM. FPCS, FECS, and the SCO bit in FCCS are cleared to 0. Rev.1.00 Jun. 07, 2006 Page 914 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) The return value is set in the DPFR parameter. After the on-chip program storage area is returned to the user-MAT space, the procedure program is resumed. After that, VBR can be set again. The values of general registers of the CPU are held. During download, no interrupts can be accepted. However, since the interrupt requests are held, when the procedure program is resumed, the interrupts are requested. To hold a level-detection interrupt request, the interrupt must continue to be input until the download is completed. Allocate a stack area of 128 bytes at the maximum in the on-chip RAM before setting the SCO bit to 1. If access to the flash memory is requested by the DMAC or DTC during download, the operation cannot be guaranteed. Make sure that an access request by the DMAC or DTC is not generated. 4. FKEY is cleared to H'00 for protection. 5. The download result must be confirmed by the value of the DPFR parameter. Check the value of the DPFR parameter (one byte of start address of the download destination specified by FTDAR). If the value of the DPFR parameter is H'00, download has been performed normally. If the value is not H'00, the source that caused download to fail can be investigated by the description below. If the value of the DPFR parameter is the same as that before downloading, the setting of the start address of the download destination in FTDAR may be abnormal. In this case, confirm the setting of the TDER bit in FTDAR. If the value of the DPFR parameter is different from that before downloading, check the SS bit or FK bit in the DPFR parameter to confirm the download program selection and FKEY setting, respectively. 6. The operating frequency of the CPU is set in the FPEFEQ parameter for initialization. The settable operating frequency of the FPEFEQ parameter ranges from 8 to 50 MHz. When the frequency is set otherwise, an error is returned to the FPFR parameter of the initialization program and initialization is not performed. For details on setting the frequency, see section 21.6.2 (3), Flash Program/Erase Frequency Parameter (FPEFEQ: General Register ER0 of CPU). Rev.1.00 Jun. 07, 2006 Page 915 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) 7. Initialization is executed. The initialization program is downloaded together with the programming program to the on-chip RAM. The entry point of the initialization program is at the address which is 32 bytes after #DLTOP (start address of the download destination specified by FTDAR). Call the subroutine to execute initialization by using the following steps. MOV.L #DLTOP+32,ER2 JSR NOP @ER2 ; Set entry address to ER2 ; Call initialization routine The general registers other than ER0 or ER1 are held in the initialization program. R0L is a return value of the FPFR parameter. Since the stack area is used in the initialization program, a stack area of 128 bytes at the maximum must be allocated in RAM. Interrupts can be accepted during execution of the initialization program. Make sure the program storage area and stack area in the on-chip RAM and register values are not overwritten. 8. The return value in the initialization program, the FPFR parameter is determined. 9. All interrupts and the use of a bus master other than the CPU are disabled during programming/erasing. The specified voltage is applied for the specified time when programming or erasing. If interrupts occur or the bus mastership is moved to other than the CPU during programming/erasing, causing a voltage exceeding the specifications to be applied, the flash memory may be damaged. Therefore, interrupts are disabled by setting bit 7 (I bit) in the condition code register (CCR) to B'1 in interrupt control mode 0 and by setting bits 2 to 0 (I2 to I0 bits) in the extend register (EXR) to B'111 in interrupt control mode 2. Accordingly, interrupts other than NMI are held and not executed. Configure the user system so that NMI interrupts do not occur. The interrupts that are held must be executed after all programming completes. When the bus mastership is moved to other than the CPU, such as to the DMAC or DTC, the error protection state is entered. Therefore, make sure the DMAC does not acquire the bus. 10. FKEY must be set to H'5A and the user MAT must be prepared for programming. Rev.1.00 Jun. 07, 2006 Page 916 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) 11. The parameters required for programming are set. The start address of the programming destination on the user MAT (FMPAR parameter) is set in general register ER1. The start address of the program data storage area (FMPDR parameter) is set in general register ER0. Example of FMPAR parameter setting: When an address other than one in the user MAT area is specified for the start address of the programming destination, even if the programming program is executed, programming is not executed and an error is returned to the FPFR parameter. Since the program data for one programming operation is 128 bytes, the lower eight bits of the address must be H'00 or H'80 to be aligned with the 128-byte boundary. Example of FMPDR parameter setting: When the storage destination for the program data is flash memory, even if the programming routine is executed, programming is not executed and an error is returned to the FPFR parameter. In this case, the program data must be transferred to the on-chip RAM and then programming must be executed. 12. Programming is executed. The entry point of the programming program is at the address which is 16 bytes after #DLTOP (start address of the download destination specified by FTDAR). Call the subroutine to execute programming by using the following steps. MOV.L JSR NOP #DLTOP+16,ER2 @ER2 ; Set entry address to ER2 ; Call programming routine The general registers other than ER0 or ER1 are held in the programming program. R0L is a return value of the FPFR parameter. Since the stack area is used in the programming program, a stack area of 128 bytes at the maximum must be allocated in RAM. 13. The return value in the programming program, the FPFR parameter is determined. 14. Determine whether programming of the necessary data has finished. If more than 128 bytes of data are to be programmed, update the FMPAR and FMPDR parameters in 128-byte units, and repeat steps 11 to 14. Increment the programming destination address by 128 bytes and update the programming data pointer correctly. If an address which has already been programmed is written to again, not only will a programming error occur, but also flash memory will be damaged. 15. After programming finishes, clear FKEY and specify software protection. If this LSI is restarted by a reset immediately after programming has finished, secure the reset input period (period of RES = 0) of at least 100 s. Rev.1.00 Jun. 07, 2006 Page 917 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) (3) Erasing Procedure in User Program Mode The procedures for download of the on-chip program, initialization, and erasing are shown in figure 21.14. Start erasing procedure program Select on-chip program to be downloaded and specify download destination by FTDAR 1 1. Disable interrupts and bus master operation other than CPU Set FKEY to H'5A Set FKEY to H'A5 Download Set SCO to 1 after initializing VBR and execute download Set FEBS parameter Erasing JSR FTDAR setting + 16 FPFR = 1 ? Yes 2. Clear FKEY to 0 Erasing 3. 4. No DPFR = 0? Yes Set the FPEFEQ parameter Initialization JSR FTDAR setting + 32 FPFR = 0 ? Yes 1 No Download error processing No Clear FKEY and erasing error processing Required block erasing is completed? Yes Clear FKEY to 0 5. Initialization 6. No Initialization error processing End erasing procedure program Figure 21.14 Erasing Procedure in User Program Mode Rev.1.00 Jun. 07, 2006 Page 918 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) The procedure program must be executed in an area other than the user MAT to be erased. Setting the SCO bit in FCCS to 1 to request download must be executed in the on-chip RAM. The area that can be executed in the steps of the procedure program (on-chip RAM, user MAT, and external space) is shown in section 21.7.4, On-Chip Program and Storable Area for Program Data. For the downloaded on-chip program area, see figure 21.12. One erasure processing erases one block. For details on block divisions, refer to figures 21.3 and 21.4. To erase two or more blocks, update the erase block number and repeat the erasing processing for each block. 1. Select the on-chip program to be downloaded and the download destination. When the PPVS bit in FPCS is set to 1, the programming program is selected. Several programming/erasing programs cannot be selected at one time. If several programs are selected, a download error is returned to the SS bit in the DPFR parameter. The on-chip RAM start address of the download destination is specified by FTDAR. For the procedures to be carried out after setting FKEY, see section 21.7.3 (2), Programming Procedure in User Program Mode. 2. Set the FEBS parameter necessary for erasure. Set the erase block number (FEBS parameter) of the user MAT in general register ER0. If a value other than an erase block number of the user MAT is set, no block is erased even though the erasing program is executed, and an error is returned to the FPFR parameter. 3. Erasure is executed. Similar to as in programming, the entry point of the erasing program is at the address which is 16 bytes after #DLTOP (start address of the download destination specified by FTDAR). Call the subroutine to execute erasure by using the following steps. MOV.L #DLTOP+16, ER2 JSR NOP @ER2 ; Set entry address to ER2 ; Call erasing routine * * * The general registers other than ER0 or ER1 are held in the erasing program. R0L is a return value of the FPFR parameter. Since the stack area is used in the erasing program, a stack area of 128 bytes at the maximum must be allocated in RAM. 4. The return value in the erasing program, the FPFR parameter is determined. 5. Determine whether erasure of the necessary blocks has finished. If more than one block is to be erased, update the FEBS parameter and repeat steps 2 to 5. 6. After erasure completes, clear FKEY and specify software protection. If this LSI is restarted by a power-on reset immediately after erasure has finished, secure the reset input period (period of RES = 0) of at least 100 s. Rev.1.00 Jun. 07, 2006 Page 919 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) (4) Procedure of Erasing, Programming, and RAM Emulation in User Program Mode By changing the on-chip RAM start address of the download destination in FTDAR, the erasing program and programming program can be downloaded to separate on-chip RAM areas. Figure 21.15 shows a repeating procedure of erasing, programming, and RAM emulation. Start procedure program Set FTDAR to H'00 (specify download destination to H'FF9000) Download erasing program Initialize erasing program Set FTDAR to H'02 (specify download destination H'FFB000) Download programming program 1 Erasing program download Emulation/Erasing/Programming Make a transition to RAM emulation mode and tuning parameters in on-chip RAM Exit emulation mode Erase relevant block (execute erasing program) Set FMPDR to H'FFA000 and program relevant block (execute programming program) Programming program download Confirm operation Initialize programming program No 1 End ? Yes End procedure program Figure 21.15 Repeating Procedure of Erasing, Programming, and RAM Emulation in User Program Mode In Figure 21.15, since RAM emulation is performed, the erasing/programming program is downloaded to avoid the 4-kbyte on-chip RAM area (H'FFA000 to H'FFAFFF). Download and initialization are performed only once at the beginning. Note the following when executing the procedure program. * Be careful not to overwrite data in the on-chip RAM with overlay settings. In addition to the programming program area, erasing program area, and RAM emulation area, areas for the procedure programs, work area, and stack area are reserved in the on-chip RAM. Do not make settings that will overwrite data in these areas. Rev.1.00 Jun. 07, 2006 Page 920 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) * Be sure to initialize both the programming program and erasing program. When the FPEFEQ parameter is initialized, also initialize both the erasing program and programming program. Initialization must be executed for both entry addresses: #DLTOP (start address of download destination for erasing program) + 32 bytes, and #DLTOP (start address of download destination for programming program) + 32 bytes. 21.7.4 On-Chip Program and Storable Area for Program Data In the descriptions in this manual, the on-chip programs and program data storage areas are assumed to be in the on-chip RAM. However, they can be executed from part of the flash memory which is not to be programmed or erased as long as the following conditions are satisfied. * The on-chip program is downloaded to and executed in the on-chip RAM specified by FTDAR. Therefore, this on-chip RAM area is not available for use. * Since the on-chip program uses a stack area, allocate 128 bytes at the maximum as a stack area. * Download requested by setting the SCO bit in FCCS to 1 should be executed from the on-chip RAM because it will require switching of the memory MATs. * In an operating mode in which the external address space is not accessible, such as single-chip mode, the required procedure programs, NMI handling vector table, and NMI handling routine should be transferred to the on-chip RAM before programming/erasing starts (download result is determined). * The flash memory is not accessible during programming/erasing. Programming/erasing is executed by the program downloaded to the on-chip RAM. Therefore, the procedure program that initiates operation, the NMI handling vector table, and the NMI handling routine should be stored in the on-chip RAM other than the flash memory. * After programming/erasing starts, access to the flash memory should be inhibited until FKEY is cleared. The reset input state (period of RES = 0) must be set to at least 100 s when the operating mode is changed and the reset start executed on completion of programming/erasing. Transitions to the reset state are inhibited during programming/erasing. When the reset signal is input, a reset input state (period of RES = 0) of at least 100 s is needed before the reset signal is released. * When the program data storage area is within the flash memory area, an error will occur even when the data stored is normal program data. Therefore, the data should be transferred to the on-chip RAM to place the address that the FMPDR parameter indicates in an area other than the flash memory. Rev.1.00 Jun. 07, 2006 Page 921 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) In consideration of these conditions, the areas in which the program data can be stored and executed are determined by the combination of the processing contents, operating mode, and bank structure of the memory MATs, as shown in tables 21.8 to 21.10. Table 21.8 Executable Memory MAT Operating Mode Processing Contents Programming Erasing User Program Mode See Table 21.9 See Table 21.10 Table 21.9 Usable Area for Programming in User Program Mode Storable/Executable Area Selected MAT Embedded Program User MAT Storage MAT O O O O O O O O O O O O O O O O O O Item Storage area for program data Operation for selecting on-chip program to be downloaded Operation for writing H'A5 to FKEY Execution of writing 1 to SCO bit in FCCS (download) Operation for clearing FKEY Decision of download result Operation for download error Operation for setting initialization parameter Execution of initialization Decision of initialization result Operation for initialization error NMI handling routine Operation for disabling interrupts Operation for writing H'5A to FKEY Operation for setting programming parameter Execution of programming Decision of programming result Operation for programming error Operation for clearing FKEY Note: * On-Chip RAM O O O O O O O O O O O O O O O O O O O User MAT x* O O x O O O O x O O x O O x x x x x Transferring the program data to the on-chip RAM beforehand enables this area to be used. Rev.1.00 Jun. 07, 2006 Page 922 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) Table 21.10 Usable Area for Erasure in User Program Mode Storable/Executable Area Selected MAT Embedded Program User MAT Storage MAT O O O O O O O O O O O O O O O O O O Item Operation for selecting on-chip program to be downloaded Operation for writing H'A5 to FKEY Execution of writing 1 to SCO bit in FCCS (download) Operation for clearing FKEY Decision of download result Operation for download error Operation for setting initialization parameter Execution of initialization Decision of initialization result Operation for initialization error NMI handling routine Operation for disabling interrupts Operation for writing H'5A to FKEY Operation for setting erasure parameter Execution of erasure Decision of erasure result Operation for erasure error Operation for clearing FKEY On-Chip RAM O O O O O O O O O O O O O O O O O O User MAT O O x O O O O x O O x O O x x x x x Rev.1.00 Jun. 07, 2006 Page 923 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) 21.8 Protection There are three types of protection against the flash memory programming/erasing: hardware protection, software protection, and error protection. 21.8.1 Hardware Protection Programming and erasure of the flash memory is forcibly disabled or suspended by hardware protection. In this state, download of an on-chip program and initialization are possible. However, programming or erasure of the user MAT cannot be performed even if the programming/erasing program is initiated, and the error in programming/erasing is indicated by the FPFR parameter. Table 21.11 Hardware Protection Function to be Protected Item Reset protection Description * The programming/erasing interface registers are initialized in the reset state (including a reset by the WDT) and the programming/erasing protection state is entered. The reset state will not be entered by a reset using the RES pin unless the RES pin is held low until oscillation has settled after a power is initially supplied. In the case of a reset during operation, hold the RES pin low for the RES pulse width given in the AC characteristics. If a reset is input during programming or erasure, data in the flash memory is not guaranteed. In this case, execute erasure and then execute programming again. Download O Programming/ Erasing O * Rev.1.00 Jun. 07, 2006 Page 924 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) 21.8.2 Software Protection The software protection protects the flash memory against programming/erasing by disabling download of the programming/erasing program, using the key code, and by the RAMER setting. Table 21.12 Software Protection Function to be Protected Item Description Download Programming/ Erasing O Protection The programming/erasing protection state is O by SCO bit entered when the SCO bit in FCCS is cleared to 0 to disable download of the programming/erasing programs. Protection The programming/erasing protection state is by FKEY entered because download and programming/erasing are disabled unless the required key code is written in FKEY. Emulation protection O O The programming/erasing protection state is O entered when the RAMS bit in the RAM emulation register (RAMER) is set to 1. O 21.8.3 Error Protection Error protection is a mechanism for aborting programming or erasure when a CPU runaway occurs or operations not according to the programming/erasing procedures are detected during programming/erasing of the flash memory. Aborting programming or erasure in such cases prevents damage to the flash memory due to excessive programming or erasing. If an error occurs during programming/erasing of the flash memory, the FLER bit in FCCS is set to 1 and the error protection state is entered. * When an interrupt request, such as NMI, occurs during programming/erasing. * When the flash memory is read from during programming/erasing (including a vector read or an instruction fetch). * When a SLEEP instruction is executed (including software-standby mode) during programming/erasing. * When a bus master other than the CPU, such as the DMAC and DTC, obtains bus mastership during programming/erasing. Rev.1.00 Jun. 07, 2006 Page 925 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) Error protection is canceled by a reset. Note that the reset should be released after the reset input period of at least 100s has passed. Since high voltages are applied during programming/erasing of the flash memory, some voltage may remain after the error protection state has been entered. For this reason, it is necessary to reduce the risk of damaging the flash memory by extending the reset input period so that the charge is released. The state-transition diagram in figure 21.16 shows transitions to and from the error protection state. Programming/erasing mode Read disabled Programming/erasing enabled FLER = 0 RES = 0 Reset (hardware protection) Read disabled Programming/erasing disabled FLER = 0 Er (S ror oc oft cu wa rre d by S= RE 0 re Error occurrence sta nd RES = 0 Programming/erasing interface register is in its initial state. ) Error-protection mode Read enabled Programming/erasing disabled FLER = 1 Software standby mode Error-protection mode (software standby) Read disabled Programming/erasing disabled FLER = 1 Programming/erasing interface register is in its initial state. Cancel software standby mode Figure 21.16 Transitions to Error Protection State Rev.1.00 Jun. 07, 2006 Page 926 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) 21.9 Flash Memory Emulation Using RAM For realtime emulation of the data written to the flash memory using the on-chip RAM, the onchip RAM area can be overlaid with several flash memory blocks (user MAT) using the RAM emulation register (RAMER). The overlaid area can be accessed from both the user MAT area specified by RAMER and the overlaid RAM area. The emulation can be performed in user mode and user program mode. Figure 21.17 shows an example of emulating realtime programming of the user MAT. Emulation program start Set RAMER Write tuning data to overlaid RAM area Execute application program No Tuning OK? Yes Cancel setting in RAMER Program emulation block in user MAT Emulation program end Figure 21.17 RAM Emulation Flow Rev.1.00 Jun. 07, 2006 Page 927 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) Figure 21.18 shows an example of overlaying flash memory block area EB0. This area can be accessed via both the on-chip RAM and flash memory area. H'00000 H'01000 H'02000 H'03000 H'04000 H'05000 H'06000 H'07000 H'08000 Flash memory user MAT EB8 to EB13*1 *2 H'5FFFF H'FFBFFF On-chip RAM EB0 EB1 EB2 EB3 EB4 EB5 EB6 EB7 H'FF6000 H'FFA000 H'FFAFFF Notes: 1. 2. EB8 to EB15 in the H8SX/1664. H'7FFFF in the H8SX/1664. Figure 21.18 Address Map of Overlaid RAM Area (H8SX/1663) The flash memory area that can be emulated is the one area selected by bits RAM2 to RAM0 in RAMER from among the eight blocks, EB0 to EB7, of the user MAT. To overlay a part of the on-chip RAM with block EB0 for realtime emulation, set the RAMS bit in RAMER to 1 and bits RAM2 to RAM0 to B'000. For programming/erasing the user MAT, the procedure programs including a download program of the on-chip program must be executed. At this time, the download area should be specified so that the overlaid RAM area is not overwritten by downloading the on-chip program. Since the area in which the tuned data is stored is overlaid with the download area when FTDAR = H'01, the tuned data must be saved in an unused area beforehand. Rev.1.00 Jun. 07, 2006 Page 928 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) Figure 21.19 shows an example of the procedure to program the tuned data in block EB0 of the user MAT. H'00000 H'01000 H'02000 H'03000 H'04000 H'05000 H'06000 H'07000 H'08000 Flash memory user MAT EB8 to EB13*1 *2 H'5FFFF Notes: 1. 2. Download area Tuned data area Area for programming/ erasing program etc. EB0 EB1 EB2 EB3 EB4 EB5 EB6 EB7 (1) Exit RAM emulation mode. (2) Transfer user-created programming/erasing procedure program. (3) Download the on-chip programming/erasing program to the area specified by FTDAR. FTDAR setting should avoid the tuned data area. (4) Program after erasing, if necessary. Specified by FTDAR H'FFA000 H'FFAFFF H'FFB000 H'FFBFFF EB8 to EB15 in the H8SX/1664. H'7FFFF in the H8SX/1664. Figure 21.19 Programming Tuned Data (H8SX/1663) 1. After tuning program data is completed, clear the RAMS bit in RAMER to 0 to cancel the overlaid RAM. 2. Transfer the user-created procedure program to the on-chip RAM. 3. Start the procedure program and download the on-chip program to the on-chip RAM. The start address of the download destination should be specified by FTDAR so that the tuned data area does not overlay the download area. 4. When block EB0 of the user MAT has not been erased, the programming program must be downloaded after block EB0 is erased. Specify the tuned data saved in the FMPAR and FMPDR parameters and then execute programming. Note: Setting the RAMS bit to 1 makes all the blocks of the user MAT enter the programming/erasing protection state (emulation protection state) regardless of the setting of the RAM2 to RAM0 bits. Under this condition, the on-chip program cannot be downloaded. When data is to be actually programmed and erased, clear the RAMS bit to 0. Rev.1.00 Jun. 07, 2006 Page 929 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) 21.10 Programmer Mode Along with its on-board programming mode, this LSI also has a programmer mode as a further mode for the writing and erasing of programs and data. In programmer mode, a general-purpose PROM programmer that supports the device types shown in table 21.13 can be used to write programs to the on-chip ROM without any limitation. Table 21.13 Device Types Supported in Programmer Mode Target Memory Product MAT Classification User MAT H8SX/1663 H8SX/1664 ROM Size 384 kbytes 512 kbytes Device Type FZTAT512V3A 21.11 Standard Serial Communication Interface Specifications for Boot Mode The boot program initiated in boot mode performs serial communication using the host and onchip SCI_4. The serial communication interface specifications are shown below. The boot program has three states. 1. Bit-rate-adjustment state In this state, the boot program adjusts the bit rate to achieve serial communication with the host. Initiating boot mode enables starting of the boot program and entry to the bit-rateadjustment state. The program receives the command from the host to adjust the bit rate. After adjusting the bit rate, the program enters the inquiry/selection state. 2. Inquiry/selection state In this state, the boot program responds to inquiry commands from the host. The device name, clock mode, and bit rate are selected. After selection of these settings, the program is made to enter the programming/erasing state by the command for a transition to the programming/erasing state. The program transfers the libraries required for erasure to the onchip RAM and erases the user MATs before the transition. 3. Programming/erasing state Programming and erasure by the boot program take place in this state. The boot program is made to transfer the programming/erasing programs to the on-chip RAM by commands from the host. Sum checks and blank checks are executed by sending these commands from the host. Rev.1.00 Jun. 07, 2006 Page 930 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) These boot program states are shown in figure 21.20. Reset Bit-rate-adjustment state Inquiry/ response wait Transition to programming/erasing Response Inquiry Operations for inquiry and selection Operations for response Operations for erasing user MATs Programming/ erasing wait Programming Operations for programming Erasing Operations for erasing Operations for checking Checking Figure 21.20 Boot Program States Rev.1.00 Jun. 07, 2006 Page 931 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) (1) Bit-Rate-Adjustment State The bit rate is calculated by measuring the period of transfer of a low-level byte (H'00) from the host. The bit rate can be changed by the command for a new bit rate selection. After the bit rate has been adjusted, the boot program enters the inquiry and selection state. The bit-rate-adjustment sequence is shown in figure 21.21. Host Boot program H'00 (30 times maximum) Measuring the 1-bit length H'00 (completion of adjustment) H'55 H'E6 (boot response) (H'FF (error)) Figure 21.21 Bit-Rate-Adjustment Sequence (2) Communications Protocol After adjustment of the bit rate, the protocol for serial communications between the host and the boot program is as shown below. 1. One-byte commands and one-byte responses These one-byte commands and one-byte responses consist of the inquiries and the ACK for successful completion. 2. n-byte commands or n-byte responses These commands and responses are comprised of n bytes of data. These are selections and responses to inquiries. The program data size is not included under this heading because it is determined in another command. 3. Error response The error response is a response to inquiries. It consists of an error response and an error code and comes two bytes. 4. Programming of 128 bytes The size is not specified in commands. The size of n is indicated in response to the programming unit inquiry. Rev.1.00 Jun. 07, 2006 Page 932 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) 5. Memory read response This response consists of four bytes of data. One-byte command or one-byte response n-byte Command or n-byte response Command or response Data Size Command or response Checksum Error response Error code Error response 128-byte programming Address Command Data (n bytes) Checksum Memory read response Size Response Data Checksum Figure 21.22 Communication Protocol Format * Command (one byte): Commands including inquiries, selection, programming, erasing, and checking * Response (one byte): Response to an inquiry * Size (one byte): The amount of data for transmission excluding the command, amount of data, and checksum * Checksum (one byte): The checksum is calculated so that the total of all values from the command byte to the SUM byte becomes H'00. * Data (n bytes): Detailed data of a command or response * Error response (one byte): Error response to a command * Error code (one byte): Type of the error * Address (four bytes): Address for programming * Data (n bytes): Data to be programmed (the size is indicated in the response to the programming unit inquiry.) * Size (four bytes): Four-byte response to a memory read Rev.1.00 Jun. 07, 2006 Page 933 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) (3) Inquiry and Selection States The boot program returns information from the flash memory in response to the host's inquiry commands and sets the device code, clock mode, and bit rate in response to the host's selection command. Table 21.14 lists the inquiry and selection commands. Table 21.14 Inquiry and Selection Commands Command H'20 H'10 H'21 H'11 H'22 Command Name Supported device inquiry Device selection Clock mode inquiry Clock mode selection Multiplication ratio inquiry Description Inquiry regarding device codes Selection of device code Inquiry regarding numbers of clock modes and values of each mode Indication of the selected clock mode Inquiry regarding the number of frequencymultiplied clock types, the number of multiplication ratios, and the values of each multiple Inquiry regarding the maximum and minimum values of the main clock and peripheral clocks Inquiry regarding the a number of user MATs and the start and last addresses of each MAT Inquiry regarding the number of blocks and the start and last addresses of each block Inquiry regarding the unit of program data Selection of new bit rate Erasing of user MAT, and entry to programming/ erasing state Inquiry into the operated status of the boot program H'23 H'25 H'26 H'27 H'3F H'40 H'4F Operating clock frequency inquiry User MAT information inquiry Block for erasing information Inquiry Programming unit inquiry New bit rate selection Transition to programming/erasing state Boot program status inquiry Rev.1.00 Jun. 07, 2006 Page 934 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) The selection commands, which are device selection (H'10), clock mode selection (H'11), and new bit rate selection (H'3F), should be sent from the host in that order. When two or more selection commands are sent at once, the last command will be valid. All of these commands, except for the boot program status inquiry command (H'4F), will be valid until the boot program receives the programming/erasing transition (H'40). The host can choose the needed commands and make inquiries while the above commands are being transmitted. H'4F is valid even after the boot program has received H'40. (a) Supported Device Inquiry The boot program will return the device codes of supported devices and the product code in response to the supported device inquiry. Command H'20 * Command, H'20, (one byte): Inquiry regarding supported devices Response H'30 Number of characters *** SUM Size Number of devices Product name Device code * Response, H'30, (one byte): Response to the supported device inquiry * Size (one byte): Number of bytes to be transmitted, excluding the command, size, and checksum, that is, the amount of data contributes by the number of devices, characters, device codes and product names * Number of devices (one byte): The number of device types supported by the boot program * Number of characters (one byte): The number of characters in the device codes and boot program's name * Device code (four bytes): ASCII code of the supporting product * Product name (n bytes): Type name of the boot program in ASCII-coded characters * SUM (one byte): Checksum The checksum is calculated so that the total number of all values from the command byte to the SUM byte becomes H'00. Rev.1.00 Jun. 07, 2006 Page 935 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) (b) Device Selection The boot program will set the supported device to the specified device code. The program will return the selected device code in response to the inquiry after this setting has been made. Command H'10 Size Device code SUM * Command, H'10, (one byte): Device selection * Size (one byte): Amount of device-code data This is fixed at 4 * Device code (four bytes): Device code (ASCII code) returned in response to the supported device inquiry * SUM (one byte): Checksum Response H'06 * Response, H'06, (one byte): Response to the device selection command ACK will be returned when the device code matches. Error response H'90 ERROR * Error response, H'90, (one byte): Error response to the device selection command ERROR : (one byte): Error code H'11: Sum check error H'21: Device code error, that is, the device code does not match (c) Clock Mode Inquiry The boot program will return the supported clock modes in response to the clock mode inquiry. Command H'21 * Command, H'21, (one byte): Inquiry regarding clock mode Response H'31 Size Mode *** SUM * Response, H'31, (one byte): Response to the clock-mode inquiry * Size (one byte): Amount of data that represents the modes * Mode (one byte): Values of the supported clock modes (i.e. H'01 means clock mode 1.) * SUM (one byte): Checksum Rev.1.00 Jun. 07, 2006 Page 936 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) (d) Clock Mode Selection The boot program will set the specified clock mode. The program will return the selected clockmode information after this setting has been made. The clock-mode selection command should be sent after the device-selection commands. Command H'11 Size Mode SUM * Command, H'11, (one byte): Selection of clock mode * Size (one byte): Amount of data that represents the modes * Mode (one byte): A clock mode returned in reply to the supported clock mode inquiry. * SUM (one byte): Checksum Response H'06 * Response, H'06, (one byte): Response to the clock mode selection command ACK will be returned when the clock mode matches. Error Response H'91 ERROR * Error response, H'91, (one byte) : Error response to the clock mode selection command * ERROR : (one byte): Error code H'11: Checksum error H'22: Clock mode error, that is, the clock mode does not match. Even if the clock mode numbers are H'00 and H'01 by a clock mode inquiry, the clock mode must be selected using these respective values. Rev.1.00 Jun. 07, 2006 Page 937 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) (e) Multiplication Ratio Inquiry The boot program will return the supported multiplication and division ratios. Command H'22 * Command, H'22, (one byte): Inquiry regarding multiplication ratio Response H'32 Number of multiplication ratios *** SUM Size Multiplication ratio Number of types *** * Response, H'32, (one byte): Response to the multiplication ratio inquiry * Size (one byte): The amount of data that represents the number of clock sources and multiplication ratios and the multiplication ratios * Number of types (one byte): The number of supported multiplied clock types (e.g. when there are two multiplied clock types, which are the main and peripheral clocks, the number of types will be H'02.) * Number of multiplication ratios (one byte): The number of multiplication ratios for each type (e.g. the number of multiplication ratios to which the main clock can be set and the peripheral clock can be set.) * Multiplication ratio (one byte) Multiplication ratio: The value of the multiplication ratio (e.g. when the clock-frequency multiplier is four, the value of multiplication ratio will be H'04.) Division ratio: The inverse of the division ratio, i.e. a negative number (e.g. when the clock is divided by two, the value of division ratio will be H'FE. H'FE = D'-2) The number of multiplication ratios returned is the same as the number of multiplication ratios and as many groups of data are returned as there are types. * SUM (one byte): Checksum Rev.1.00 Jun. 07, 2006 Page 938 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) (f) Operating Clock Frequency Inquiry The boot program will return the number of operating clock frequencies, and the maximum and minimum values. Command H'23 * Command, H'23, (one byte): Inquiry regarding operating clock frequencies Response H'33 Size Number of operating clock frequencies Maximum value of operating clock frequency Minimum value of operating clock frequency *** SUM * Response, H'33, (one byte): Response to operating clock frequency inquiry * Size (one byte): The number of bytes that represents the minimum values, maximum values, and the number of frequencies. * Number of operating clock frequencies (one byte): The number of supported operating clock frequency types (e.g. when there are two operating clock frequency types, which are the main and peripheral clocks, the number of types will be H'02.) * Minimum value of operating clock frequency (two bytes): The minimum value of the multiplied or divided clock frequency. The minimum and maximum values of the operating clock frequency represent the values in MHz, valid to the hundredths place of MHz, and multiplied by 100. (e.g. when the value is 17.00 MHz, it will be 2000, which is H'07D0.) * Maximum value (two bytes): Maximum value among the multiplied or divided clock frequencies. There are as many pairs of minimum and maximum values as there are operating clock frequencies. * SUM (one byte): Checksum Rev.1.00 Jun. 07, 2006 Page 939 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) (g) User MAT Information Inquiry The boot program will return the number of user MATs and their addresses. Command H'25 * Command, H'25, (one byte): Inquiry regarding user MAT information Response H'35 Size Number of areas Last address area Start address area *** SUM * Response, H'35, (one byte): Response to the user MAT information inquiry * Size (one byte): The number of bytes that represents the number of areas, area-start address and area-last address * Number of areas (one byte): The number of consecutive user MAT areas When the user MAT areas are consecutive, the number of areas is H'01. * Area-start address (four bytes): Start address of the area * Area-last address (four bytes): Last address of the area There are as many groups of data representing the start and last addresses as there are areas. * SUM (one byte): Checksum (h) Erased Block Information Inquiry The boot program will return the number of erased blocks and their addresses. Command H'26 * Command, H'26, (two bytes): Inquiry regarding erased block information Response H'36 Size Number of blocks Block last address Block start address *** SUM * Response, H'36, (one byte): Response to the number of erased blocks and addresses * Size (three bytes): The number of bytes that represents the number of blocks, block-start addresses, and block-last addresses. * Number of blocks (one byte): The number of erased blocks * Block start address (four bytes): Start address of a block Rev.1.00 Jun. 07, 2006 Page 940 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) * Block last Address (four bytes): Last address of a block There are as many groups of data representing the start and last addresses as there are areas. * SUM (one byte): Checksum (i) Programming Unit Inquiry The boot program will return the programming unit used to program data. Command H'27 * Command, H'27, (one byte): Inquiry regarding programming unit Response H'37 Size Programming unit SUM * Response, H'37, (one byte): Response to programming unit inquiry * Size (one byte): The number of bytes that indicate the programming unit, which is fixed to 2 * Programming unit (two bytes): A unit for programming This is the unit for reception of programming. * SUM (one byte): Checksum (j) New Bit-Rate Selection The boot program will set a new bit rate and return the new bit rate. This selection should be sent after sending the clock mode selection command. Command H'3F Number of multiplication ratios SUM Size Multiplication ratio 1 Bit rate Multiplication ratio 2 Input frequency * Command, H'3F, (one byte): Selection of new bit rate * Size (one byte): The number of bytes that represents the bit rate, input frequency, number of multiplication ratios, and multiplication ratio * Bit rate (two bytes): New bit rate One hundredth of the value (e.g. when the value is 19200 bps, it will be 192, which is H'00C0.) * Input frequency (two bytes): Frequency of the clock input to the boot program This is valid to the hundredths place and represents the value in MHz multiplied by 100. (E.g. when the value is 20.00 MHz, it will be 2000, which is H'07D0.) * Number of multiplication ratios (one byte): The number of multiplication ratios to which the device can be set. Rev.1.00 Jun. 07, 2006 Page 941 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) * Multiplication ratio 1 (one byte) : The value of multiplication or division ratios for the main operating frequency Multiplication ratio (one byte): The value of the multiplication ratio (e.g. when the clock frequency is multiplied by four, the multiplication ratio will be H'04.) Division ratio: The inverse of the division ratio, as a negative number (e.g. when the clock frequency is divided by two, the value of division ratio will be H'FE. H'FE = D'-2) * Multiplication ratio 2 (one byte): The value of multiplication or division ratios for the peripheral frequency Multiplication ratio (one byte): The value of the multiplication ratio (e.g. when the clock frequency is multiplied by four, the multiplication ratio will be H'04.) (Division ratio: The inverse of the division ratio, as a negative number (E.g. when the clock is divided by two, the value of division ratio will be H'FE. H'FE = D'-2) * SUM (one byte): Checksum Response H'06 * Response, H'06, (one byte): Response to selection of a new bit rate When it is possible to set the bit rate, the response will be ACK. Error Response H'BF ERROR * Error response, H'BF, (one byte): Error response to selection of new bit rate * ERROR: (one byte): Error code H'11: H'24: H'25: H'26: H'27: Sum checking error Bit-rate selection error The rate is not available. Error in input frequency This input frequency is not within the specified range. Multiplication-ratio error The ratio does not match an available ratio. Operating frequency error The frequency is not within the specified range. Rev.1.00 Jun. 07, 2006 Page 942 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) (4) Receive Data Check The methods for checking of receive data are listed below. 1. Input frequency The received value of the input frequency is checked to ensure that it is within the range of minimum to maximum frequencies which matches the clock modes of the specified device. When the value is out of this range, an input-frequency error is generated. 2. Multiplication ratio The received value of the multiplication ratio or division ratio is checked to ensure that it matches the clock modes of the specified device. When the value is out of this range, an inputfrequency error is generated. 3. Operating frequency error Operating frequency is calculated from the received value of the input frequency and the multiplication or division ratio. The input frequency is input to the LSI and the LSI is operated at the operating frequency. The expression is given below. Operating frequency = Input frequency x Multiplication ratio, or Operating frequency = Input frequency / Division ratio The calculated operating frequency should be checked to ensure that it is within the range of minimum to maximum frequencies which are available with the clock modes of the specified device. When it is out of this range, an operating frequency error is generated. 4. Bit rate To facilitate error checking, the value (n) of clock select (CKS) in the serial mode register (SMR), and the value (N) in the bit rate register (BRR), which are found from the peripheral operating clock frequency () and bit rate (B), are used to calculate the error rate to ensure that it is less than 4%. If the error is more than 4%, a bit rate error is generated. The error is calculated using the following expression: Error (%) = {[ x 106 (N + 1) x B x 64 x 2(2xn - 1) ] - 1} x 100 When the new bit rate is selectable, the rate will be set in the register after sending ACK in response. The host will send an ACK with the new bit rate for confirmation and the boot program will response with that rate. Confirmation H'06 * Confirmation, H'06, (one byte): Confirmation of a new bit rate Response H'06 * Response, H'06, (one byte): Response to confirmation of a new bit rate Rev.1.00 Jun. 07, 2006 Page 943 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) The sequence of new bit-rate selection is shown in figure 21.23. Host Setting a new bit rate H'06 (ACK) Waiting for one-bit period at the specified bit rate Boot program Setting a new bit rate H'06 (ACK) with the new bit rate H'06 (ACK) with the new bit rate Setting a new bit rate Figure 21.23 New Bit-Rate Selection Sequence (5) Transition to Programming/Erasing State The boot program will transfer the erasing program and erase the user MATs. On completion of this erasure, ACK will be returned and the program will enter the programming/erasing state. The host should select the device code, clock mode, and new bit rate with device selection, clockmode selection, and new bit-rate selection commands, and then send the command for the transition to programming/erasing state. These procedures should be carried out before sending of the programming selection command or program data. Command H'40 * Command, H'40, (one byte): Transition to programming/erasing state Response H'06 * Response, H'06, (one byte): Response to transition to programming/erasing state The boot program will send ACK when the user MATs have been erased by the transferred erasing program. Error Response H'C0 H'51 * Error code, H'51, (one byte): Erasing error An error occurred and erasure was not completed. Rev.1.00 Jun. 07, 2006 Page 944 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) (6) Command Error A command error will occur when a command is undefined, the order of commands is incorrect, or a command is unacceptable. Issuing a clock-mode selection command before a device selection or an inquiry command after the transition to programming/erasing state command, are examples. Error Response H'80 H'xx * Error response, H'80, (one byte): Command error * Command, H'xx, (one byte): Received command (7) Command Order The order for commands in the inquiry selection state is shown below. 1. A supported device inquiry (H'20) should be made to inquire about the supported devices. 2. The device should be selected from among those described by the returned information and set with a device-selection (H'10) command. 3. A clock-mode inquiry (H'21) should be made to inquire about the supported clock modes. 4. The clock mode should be selected from among those described by the returned information and set. 5. After selection of the device and clock mode, inquiries for other required information should be made, such as the multiplication-ratio inquiry (H'22) or operating frequency inquiry (H'23), which are needed for a new bit-rate selection. 6. A new bit rate should be selected with the new bit-rate selection (H'3F) command, according to the returned information on multiplication ratios and operating frequencies. 7. After selection of the device and clock mode, the information of the user MAT should be made to inquire about the user MATs information inquiry (H'25), erased block information inquiry (H'26), and programming unit inquiry (H'27). 8. After making inquiries and selecting a new bit rate, issue the transition to programming/erasing state command (H'40). The boot program will then enter the programming/erasing state. Rev.1.00 Jun. 07, 2006 Page 945 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) (8) Programming/Erasing State A programming selection command makes the boot program select the programming method, a 128-byte programming command makes it program the memory with data, and an erasing selection command and block erasing command make it erase the block. Table 21.15 lists the programming/erasing commands. Table 21.15 Programming/Erasing Commands Command H'43 H'50 H'48 H'58 H'52 H'4B H'4D H'4F Command Name User MAT programming selection 128-byte programming Erasing selection Block erasing Memory read User MAT sum check User MAT blank check Boot program status inquiry Description Transfers the user MAT programming program Programs 128 bytes of data Transfers the erasing program Erases a block of data Reads the contents of memory Checks the checksum of the user MAT Checks the blank data of the user MAT Inquires into the boot program's status * Programming Programming is executed by the programming selection and 128-byte programming commands. Firstly, the host should send the programming selection command After issuing the programming selection command, the host should send the 128-byte programming command. The 128-byte programming command that follows the selection command represents the data programmed according to the method specified by the selection command. When more than 128-byte data is programmed, 128-byte commands should repeatedly be executed. Sending a 128-byte programming command with H'FFFFFFFF as the address will stop the programming. On completion of programming, the boot program will wait for selection of programming or erasing. Where the sequence of programming operations that is executed includes programming with another method or of another MAT, the procedure must be repeated from the programming selection command. The sequence for the programming selection and 128-byte programming commands is shown in figure 21.24. Rev.1.00 Jun. 07, 2006 Page 946 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) Host Programming selection (H'43, H'44) Boot program Transfer of the programming program ACK 128-byte programming (address, data) Repeat ACK 128-byte programming (H'FFFFFFFF) ACK Programming Figure 21.24 Programming Sequence * Erasure Erasure is executed by the erasure selection and block erasure commands. Firstly, erasure is selected by the erasure selection command and the boot program then erases the specified block. The command should be repeatedly executed if two or more blocks are to be erased. Sending a block erasure command from the host with the block number H'FF will stop the erasure operating. On completion of erasing, the boot program will wait for selection of programming or erasing. The sequence for the erasure selection and block erasure commands is shown in figure 21.25. Host Preparation for erasure (H'48) Boot program Transfer of erasure program ACK Repeat Erasure (Erasure block number) ACK Erasure (H'FF) ACK Erasure Figure 21.25 Erasure Sequence Rev.1.00 Jun. 07, 2006 Page 947 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) (a) User MAT Programming Selection The boot program will transfer a program for user MAT programming selection. The data is programmed to the user MATs by the transferred program for programming. Command H'43 * Command, H'43, (one byte): User-program programming selection Response H'06 * Response, H'06, (one byte): Response to user-program programming selection When the programming program has been transferred, the boot program will return ACK. Error Response H'C3 ERROR * Error response : H'C3 (1 byte): Error response to user-program programming selection * ERROR : (1 byte): Error code H'54: Selection processing error (transfer error occurs and processing is not completed) (b) 128-Byte Programming The boot program will use the programming program transferred by the programming selection to program the user MATs in response to 128-byte programming. Command H'50 Data *** SUM Address *** * Command, H'50, (one byte): 128-byte programming * Programming Address (four bytes): Start address for programming Multiple of the size specified in response to the programming unit inquiry (i.e. H'00, H'01, H'00, H'00 : H'01000000) * Program data (128 bytes): Data to be programmed The size is specified in the response to the programming unit inquiry. * SUM (one byte): Checksum Response H'06 * Response, H'06, (one byte): Response to 128-byte programming On completion of programming, the boot program will return ACK. Rev.1.00 Jun. 07, 2006 Page 948 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) Error Response H'D0 ERROR * Error response, H'D0, (one byte): Error response for 128-byte programming * ERROR: (one byte): Error code H'11: Checksum Error H'2A: Address error The address is not in the specified MAT. H'53: Programming error A programming error has occurred and programming cannot be continued. The specified address should match the unit for programming of data. For example, when the programming is in 128-byte units, the lower eight bits of the address should be H'00 or H'80. When there are less than 128 bytes of data to be programmed, the host should fill the rest with H'FF. Sending the 128-byte programming command with the address of H'FFFFFFFF will stop the programming operation. The boot program will interpret this as the end of the programming and wait for selection of programming or erasing. Command H'50 Address SUM * Command, H'50, (one byte): 128-byte programming * Programming Address (four bytes): End code is H'FF, H'FF, H'FF, H'FF. * SUM (one byte): Checksum Response H'06 * Response, H'06, (one byte): Response to 128-byte programming On completion of programming, the boot program will return ACK. Error Response H'D0 ERROR * Error Response, H'D0, (one byte): Error response for 128-byte programming * ERROR: (one byte): Error code H'11: Checksum error H'53: Programming error An error has occurred in programming and programming cannot be continued. Rev.1.00 Jun. 07, 2006 Page 949 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) (c) Erasure Selection The boot program will transfer the erasure program. User MAT data is erased by the transferred erasure program. Command H'48 * Command, H'48, (one byte): Erasure selection Response H'06 * Response, H'06, (one byte): Response for erasure selection After the erasure program has been transferred, the boot program will return ACK. Error Response H'C8 ERROR * ERROR: (one byte): Error code H'54: Selection processing error (transfer error occurs and processing is not completed) (d) Block Erasure The boot program will erase the contents of the specified block. Command H'58 Size Block number SUM * Command, H'58, (one byte): Erasure * Size (one byte): The number of bytes that represents the erase block number This is fixed to 1. * Block number (one byte): Number of the block to be erased * SUM (one byte): Checksum Response H'06 * Response, H'06, (one byte): Response to Erasure After erasure has been completed, the boot program will return ACK. Error Response H'D8 ERROR * Error Response, H'D8, (one byte): Response to Erasure * ERROR (one byte): Error code H'11: H'29: H'51: Sum check error Block number error Block number is incorrect. Erasure error An error has occurred during erasure. Rev.1.00 Jun. 07, 2006 Page 950 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) On receiving block number H'FF, the boot program will stop erasure and wait for a selection command. Command H'58 Size Block number SUM * Command, H'58, (one byte): Erasure * Size, (one byte): The number of bytes that represents the block number This is fixed to 1. * Block number (one byte): H'FF Stop code for erasure * SUM (one byte): Checksum Response H'06 * Response, H'06, (one byte): Response to end of erasure (ACK) When erasure is to be performed after the block number H'FF has been sent, the procedure should be executed from the erasure selection command. (e) Memory Read The boot program will return the data in the specified address. Command H'52 Size Area Read address SUM Read size * Command: H'52 (1 byte): Memory read * Size (1 byte): Amount of data that represents the area, read address, and read size (fixed at 9) * Area (1 byte) H'01: User MAT An address error occurs when the area setting is incorrect. * Read address (4 bytes): Start address to be read from * Read size (4 bytes): Size of data to be read * SUM (1 byte): Checksum Response H'52 Data SUM Read size *** * Response: H'52 (1 byte): Response to memory read * Read size (4 bytes): Size of data to be read * Data (n bytes): Data for the read size from the read address * SUM (1 byte): Checksum Rev.1.00 Jun. 07, 2006 Page 951 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) Error Response H'D2 ERROR * Error response: H'D2 (1 byte): Error response to memory read * ERROR: (1 byte): Error code H'11: Sum check error H'2A: Address error The read address is not in the MAT. H'2B: Size error The read size exceeds the MAT. (f) User-Program Sum Check The boot program will return the byte-by-byte total of the contents of the bytes of the user program. Command H'4B * Command, H'4B, (one byte): Sum check for user program Response H'5B Size Checksum of user program SUM * Response, H'5B, (one byte): Response to the sum check of the user program * Size (one byte): The number of bytes that represents the checksum This is fixed to 4. * Checksum of user boot program (four bytes): Checksum of user MATs The total of the data is obtained in byte units. * SUM (one byte): Sum check for data being transmitted (g) User MAT Blank Check The boot program will check whether or not all user MATs are blank and return the result. Command H'4D * Command, H'4D, (one byte): Blank check for user MATs Response H'06 * Response, H'06, (one byte): Response to the blank check for user MATs If the contents of all user MATs are blank (H'FF), the boot program will return ACK. Error Response H'CD H'52 * Error Response, H'CD, (one byte): Error response to the blank check of user MATs. * Error code, H'52, (one byte): Erasure has not been completed. Rev.1.00 Jun. 07, 2006 Page 952 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) (h) Boot Program State Inquiry The boot program will return indications of its present state and error condition. This inquiry can be made in the inquiry/selection state or the programming/erasing state. Command H'4F * Command, H'4F, (one byte): Response H'5F Size Inquiry regarding boot program's state ERROR SUM Status * Response, H'5F, (one byte): Response to boot program state inquiry * Size (one byte): The number of bytes. This is fixed to 2. * Status (one byte): State of the boot program * ERROR (one byte): Error status ERROR = 0 indicates normal operation. ERROR = 1 indicates error has occurred. * SUM (one byte): Sum check Table 21.16 Status Code Code H'11 H'12 H'13 H'1F H'31 H'3F H'4F H'5F Description Device selection wait Clock mode selection wait Bit rate selection wait Programming/erasing state transition wait (bit rate selection is completed) Programming state for erasure Programming/erasing selection wait (erasure is completed) Program data receive wait Erase block specification wait (erasure is completed) Rev.1.00 Jun. 07, 2006 Page 953 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) Table 21.17 Error Code Code H'00 H'11 H'12 H'21 H'22 H'24 H'25 H'26 H'27 H'29 H'2A H'2B H'51 H'52 H'53 H'54 H'80 H'FF Description No error Sum check error Program size error Device code mismatch error Clock mode mismatch error Bit rate selection error Input frequency error Multiplication ratio error Operating frequency error Block number error Address error Data length error Erasure error Erasure incomplete error Programming error Selection processing error Command error Bit-rate-adjustment confirmation error Rev.1.00 Jun. 07, 2006 Page 954 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) 21.12 Usage Notes 1. The initial state of the product at its shipment is in the erased state. For the product whose revision of erasing is undefined, we recommend to execute automatic erasure for checking the initial state (erased state) and compensating. 2. For the PROM programmer suitable for programmer mode in this LSI and its program version, refer to the instruction manual of the socket adapter. 3. If the socket, socket adapter, or product index does not match the specifications, too much current flows and the product may be damaged. 4. Use a PROM programmer that supports the device with 512-kbyte on-chip flash memory and 3.3-V programming voltage. Use only the specified socket adapter. 5. Do not remove the chip from the PROM programmer nor input a reset signal during programming/erasing in which a high voltage is applied to the flash memory. Doing so may damage the flash memory permanently. If a reset is input accidentally, the reset must be released after the reset input period of at least 100s. 6. The flash memory is not accessible until FKEY is cleared after programming/erasing starts. If the operating mode is changed and this LSI is restarted by a reset immediately after programming/erasing has finished, secure the reset input period (period of RES = 0) of at least 100s. Transition to the reset state during programming/erasing is inhibited. If a reset is input accidentally, the reset must be released after the reset input period of at least 100s. 7. At powering on or off the Vcc power supply, fix the RES pin to low and set the flash memory to hardware protection state. This power on/off timing must also be satisfied at a power-off and power-on caused by a power failure and other factors. 8. In on-board programming mode or programmer mode, programming of the 128-byte programming-unit block must be performed only once. Perform programming in the state where the programming-unit block is fully erased. 9. When the chip is to be reprogrammed with the programmer after execution of programming or erasure in on-board programming mode, it is recommended that automatic programming is performed after execution of automatic erasure. 10. To program the flash memory, the program data and program must be allocated to addresses which are higher than those of the external interrupt vector table and H'FF must be written to all the system reserved areas in the exception handling vector table. 11. The programming program that includes the initialization routine and the erasing program that includes the initialization routine are each 4 kbytes or less. Accordingly, when the CPU clock frequency is 35 MHz, the download for each program takes approximately 60 s at the maximum. Rev.1.00 Jun. 07, 2006 Page 955 of 1102 REJ09B0294-0100 Section 21 Flash Memory (0.18-m F-ZTAT Version) 12. A programming/erasing program for the flash memory used in a conventional F-ZTAT H8, H8S microcomputer which does not support download of the on-chip program by setting the SCO bit in FCCS to 1 cannot run in this LSI. Be sure to download the on-chip program to execute programming/erasing of the flash memory in this F-ZTAT H8SX microcomputer. 13. Unlike a conventional F-ZTAT H8 or H8S microcomputers, measures against a program crash are not taken by WDT while programming/erasing and downloading a programming/erasing program. When needed, measures should be taken by user. A periodic interrupt generated by the WDT can be used as the measures, as an example. In this case, the interrupt generation period should take into consideration time to program/erase the flash memory. 14. When downloading the programming/erasing program, do not clear the SCO bit in FCCS to 0 after immediately setting it to 1. Otherwise, download cannot be performed normally. Immediately after executing the instruction to set the SCO bit to 1, dummy read of the FCCS must be executed twice. 15. The contents of some registers are not saved in a programming/erasing program. When needed, save registers in the procedure program. Rev.1.00 Jun. 07, 2006 Page 956 of 1102 REJ09B0294-0100 Section 22 Clock Pulse Generator Section 22 Clock Pulse Generator This LSI has an on-chip clock pulse generator (CPG) that generates the system clock (I), peripheral module clock (P), external bus clock (B), 32K timer clock (SUBCK), and USB clock (cku). The clock pulse generator consists of a main clock oscillator, frequency divider, PLL (phaselocked loop) circuit, subclock oscillator, waveform generation circuit, and selector. Figure 22.1 is a block diagram of the clock pulse generator. The frequency divider, PLL circuit, and selector can change the clock frequency. Software changes the frequency through the setting of the system clock control register (SCKCR) and subclock control register (SUBCKCR). This LSI supports five clocks: a system clock provided to the CPU and bus masters, a peripheral module clock provided to the peripheral modules, an external bus clock provided to the external bus, a 32K timer clock, and a USB clock provided to the USB module. Frequencies of the peripheral module clock, the external bus clock, and the system clock can be set independently, although the peripheral module clock and the external bus clock operate with the frequency lower than the system clock frequency. The system clock, peripheral module clock, and external bus clock can be uniformly set to the 32.768 kHz subclock. The USB module requires the 48-MHz clock. Set the external clock frequency and the MD_CLK pin so that the USB clock (cku) frequency becomes 48 MHz. Note that the MD_CLK pin setting also changes the frequencies of the peripheral module clock, the external bus clock, and the system clock. Rev.1.00 Jun. 07, 2006 Page 957 of 1102 REJ09B0294-0100 Section 22 Clock Pulse Generator SCKCR SUBCKCR ICK2 to ICK0 CK32K cks Selector System clock (I) (to the CPU and bus masters) SCKCR MD_CLK EXTAL x 4 (2)* x 2 (1) x 1 (1/2) x 1/2 (setting prohibited) SUBCKCR PCK2 to PCK0 CK32K ckm Selector Peripheral module clock (P) (to peripheral modules) XTAL Main clock oscillator EXTAL PLL circuit Divider SCKCR SUBCKCR BCK2 to BCK0 CK32K ckb OSC1 Subclock oscillator OSC2 Selector Waveform generation circuit Subclock External bus clock (B) (to the B and SD pins) 32K timer clock (SUBCK) (to TM32K) EXTAL x 4 (3) Note: * Values in parentheses are setting values when MD_CLK = 1. cku USB clock (cku) (to USB) Figure 22.1 Block Diagram of Clock Pulse Generator Table 22.1 Selection of Clock Pulse Generator MD_CLK 0 1 EXTAL Input Clock Frequencies 8 MHz to 18 MHz 16 MHz I/P/B EXTAL x4, x2, x1, x1/2 EXTAL x2, x1, x1/2 USB Clock (cku) EXTAL x4 EXTAL x3 Rev.1.00 Jun. 07, 2006 Page 958 of 1102 REJ09B0294-0100 Section 22 Clock Pulse Generator 22.1 Register Description The clock pulse generator has the following registers. * System clock control register (SCKCR) * Subclock control register (SUBCKCR) 22.1.1 System Clock Control Register (SCKCR) SCKCR controls B output control and frequencies of the system, peripheral module, and external bus clocks. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 PSTOP1 0 R/W 7 0 R/W 14 PSTOP0 0 R/W 6 PCK2 0 R/W 13 0 R/W 5 PCK1 1 R/W 12 0 R/W 4 PCK0 0 R/W 11 0 R/W 3 0 R/W 10 ICK2 0 R/W 2 BCK2 0 R/W 9 ICK1 1 R/W 1 BCK1 1 R/W 8 ICK0 0 R/W 0 BCK0 0 R/W Bit 15 Bit Name PSTOP1 Initial Value 0 R/W R/W Description B Clock Output Enable Controls output on PA7. * Normal operation 0: output 1: Fixed high 14 PSTOP0 0 R/W Clock Output Enable Controls output (SD) on PB7. * Normal operation 0: output 1: Fixed high Rev.1.00 Jun. 07, 2006 Page 959 of 1102 REJ09B0294-0100 Section 22 Clock Pulse Generator Bit Bit Name Initial Value All 0 R/W R/W Description Reserved Although these bits are readable/writable, only 0 should be written to. 13 to 11 10 9 8 ICK2 ICK1 ICK0 0 1 0 R/W R/W R/W System Clock (I) Select These bits select the frequency of the system clock provided to the CPU, DMAC, and DTC. The ratio to the input clock is as follows: ICK (2:0) MD_CLK = 0 000: 001: 010: 011: 1XX: x4 x2 x1 x 1/2 Setting prohibited MD_CLK = 1 x2 x1 x 1/2 Setting prohibited The frequencies of the peripheral module clock and external bus clock change to the same frequency as the system clock if the frequency of the system clock is lower than that of the two clocks. 7 0 R/W Reserved Although this bit is readable/writable, only 0 should be written to. 6 5 4 PCK2 PCK1 PCK0 0 1 0 R/W R/W R/W Peripheral Module Clock (P) Select These bits select the frequency of the peripheral module clock. The ratio to the input clock is as follows: PCK (2:0) MD_CLK = 0 000: 001: 010: 011: 1XX: x4 x2 x1 x 1/2 Setting prohibited MD_CLK = 1 x2 x1 x 1/2 Setting prohibited The frequency of the peripheral module clock should be lower than that of the system clock. Though these bits can be set so as to make the frequency of the peripheral module clock higher than that of the system clock, the clocks will have the same frequency in reality. Rev.1.00 Jun. 07, 2006 Page 960 of 1102 REJ09B0294-0100 Section 22 Clock Pulse Generator Bit 3 Bit Name Initial Value 0 R/W R/W Description Reserved Although this bit is readable/writable, only 0 should be written to. 2 1 0 BCK2 BCK1 BCK0 0 1 0 R/W R/W R/W External Bus Clock (B) Select These bits select the frequency of the external bus clock. The ratio to the input clock is as follows: BCK (2:0) MD_CLK = 0 000: 001: 010: 011: 1XX: x4 x2 x1 x 1/2 Setting prohibited MD_CLK = 1 x2 x1 x 1/2 Setting prohibited The frequency of the external bus clock should be lower than that of the system clock. Though these bits can be set so as to make the frequency of the external bus clock higher than that of the system clock, the clocks will have the same frequency in reality. Note: X: Don't care 22.1.2 Subclock Control Register (SUBCKCR) SUBCKCR stops the main clock oscillator, selects the operating clock of the system clock, and selects the operating clock after a transition from software standby mode. Bit Bit Name Initial Value R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 EXSTP 0 R/W 1 WAKE32K 0 R/W 0 CS32K 0 R/W Rev.1.00 Jun. 07, 2006 Page 961 of 1102 REJ09B0294-0100 Section 22 Clock Pulse Generator Bit 7 6 5 4 3 2 Bit Name EXSTP Initial Value 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W Description Reserved These bits are always read as 0. The write value should always be 0. Main Clock Oscillation Stop 0: The main clock oscillator and PLL remain active during subclock operation, but are stopped in standby mode. The main clock oscillator and PLL are stopped during subclock operation. 1: 1 WAKE32K 0 R/W Wakeup Clock Select Selects the operating clock for use as the system clock after the transition from the subclock operation in software standby mode has been initiated by an interrupt. 0: 1: On leaving software standby mode, the main clock is the operating clock. On leaving software standby mode, the subclock is the operating clock. This setting is valid when bit 0 (CK32K) is set to 1. The system clock (I), peripheral module clock (P), and external bus clock (B) operate on the main clock. The system clock (I), peripheral module clock (P), and external bus clock (B) operate on the subclock. 0 CK32K 0 R/W Subclock Select 0: 1: When the OSC32STP bit in TCR32K is 1, 1 cannot be written to this bit. This bit is cleared to 0 when clearing software standby mode while the value of WAKE32K is 0. Dummy read of this bit must be performed twice immediately after this bit is written to. Rev.1.00 Jun. 07, 2006 Page 962 of 1102 REJ09B0294-0100 Section 22 Clock Pulse Generator 22.2 Oscillator Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. 22.2.1 Connecting Crystal Resonator A crystal resonator can be connected as the example in figure 22.2. Select the damping resistance Rd according to table 22.2. An AT-cut parallel-resonance type should be used. When providing the clock from the crystal resonator, the frequency should be in the range of 8 to 18 MHz. CL1 EXTAL XTAL Rd CL2 CL1 = CL2 = 10 pF to 22 pF Figure 22.2 Connection of Crystal Resonator (Example) Table 22.2 Damping Resistance Value Frequency (MHz) Rd () 8 200 12 0 16 0 18 0 Rev.1.00 Jun. 07, 2006 Page 963 of 1102 REJ09B0294-0100 Section 22 Clock Pulse Generator Figure 22.3 shows an equivalent circuit of the crystal resonator. Use a crystal resonator that has the characteristics shown in table 22.3. CL L XTAL Rs EXTAL AT-cut parallel-resonance type C0 Figure 22.3 Crystal Resonator Equivalent Circuit Table 22.3 Crystal Resonator Characteristics Frequency (MHz) RS Max. () C0 Max. (pF) 8 80 12 60 16 50 7 18 40 22.2.2 External Clock Input An external clock signal can be input as the examples in Figure 22.4. When the XTAL pin is left open, make the parasitic capacitance less than 10 pF. When the counter clock is input to the XTAL pin, put the external clock in high level during standby mode. EXTAL XTAL Open External clock input (a) XTAL pin left open EXTAL XTAL External clock input (b) Counter clock input on XTAL pin Figure 22.4 External Clock Input (Examples) Rev.1.00 Jun. 07, 2006 Page 964 of 1102 REJ09B0294-0100 Section 22 Clock Pulse Generator tEXH tEXL EXTAL Vcc x 0.5 tEXr tEXf Figure 22.5 External Clock Input Timing 22.3 PLL Circuit The PLL circuit has the function of multiplying the frequency of the clock from the oscillator by a factor of 4. The frequency multiplication rate is fixed. The phase difference is controlled so that the timing of the rising edge of the internal clock is the same as that of the EXTAL pin signal. 22.4 Frequency Divider The frequency divider divides the PLL clock to generate a 1/2, 1/4, or 1/8 clock. After the bits ICK2 to ICK0, PCK 2 to PCK0, and BCK2 to BCK0 are updated, this LSI operates with the updated frequency. 22.5 22.5.1 Subclock Oscillator Connecting 32.768 kHz Crystal Resonator To supply a clock to the subclock oscillator, connect a 32.768-kHz crystal resonator, as shown in figure 22.6. The usage notes given in section 22.6.3, Notes on Board Design, apply to the connection of this crystal resonator. C1 OSC1 C2 OSC2 C1 = C2 = 15 pF (typ.) Note: C1 and C2 are reference values that include the floating capacitance of the board. Figure 22.6 Connection Example of 32.768-kHz Crystal Resonator Rev.1.00 Jun. 07, 2006 Page 965 of 1102 REJ09B0294-0100 Section 22 Clock Pulse Generator Figure 22.7 shows an equivalent circuit for the 32.768-kHz crystal resonator. Ls Cs Rs OSC1 Co Co = 1.5 pF (typ.) Rs = 14 k (typ.) fw = 32.768 kHz OSC2 Figure 22.7 Equivalent Circuit for 32.768-kHz Crystal Resonator 22.5.2 Handling of Pins when the Subclock is Not to be Used If the subclock is not required, connect the OSC1 pin to Vss and leave the OSC2 pin open, as shown in figure 22.8. OSC1 OSC2 Open Figure 22.8 Pin Handling when Subclock is not Used Rev.1.00 Jun. 07, 2006 Page 966 of 1102 REJ09B0294-0100 Section 22 Clock Pulse Generator 22.6 22.6.1 Usage Notes Notes on Clock Pulse Generator 1. The following points should be noted since the frequency of (I: system clock, P: peripheral module clock, B: external bus clock) supplied to each module changes according to the setting of SCKCR. Select a clock division ratio that is within the operation guaranteed range of clock cycle time tcyc shown in the AC timing of electrical characteristics. The frequency should be set under the conditions of 8 MHz I 50 MHz, 8 MHz P 35 MHz, and 8 MHz B 50 MHz. 2. All the on-chip peripheral modules (except for the DMAC and DTC) operate on the P. Note therefore that the time processing of modules such as a timer and SCI differs before and after changing the clock division ratio. In addition, wait time for clearing software standby mode differs by changing the clock division ratio. For details, see section 23.7.3, Setting Oscillation Settling Time after Clearing Software Standby Mode. 3. The relationship among the system clock, peripheral module clock, and external bus clock is I P and I B. In addition, the system clock setting has the highest priority. Accordingly, P or B may have the frequency set by bits ICK2 to ICK0 regardless of the settings of bits PCK2 to PCK0 or BCK2 to BCK0. 4. Note that the frequency of will be changed in the middle of a bus cycle when setting SCKCR while executing the external bus cycle with the write-data-buffer function. 5. Figure 22.9 shows the clock modification timing. After a value is written to SCKCR, this LSI waits for the current bus cycle to complete. After the current bus cycle completes, each clock frequency will be modified within one cycle (worst case) of the external input clock . Rev.1.00 Jun. 07, 2006 Page 967 of 1102 REJ09B0294-0100 Section 22 Clock Pulse Generator One cycle (worst case) after the bus cycle completion External clock I Bus master CPU CPU CPU Operating clock specified in SCKCR Operating clock changed Figure 22.9 Clock Modification Timing 22.6.2 Notes on Resonator Since various characteristics related to the resonator are closely linked to the user's board design, thorough evaluation is necessary on the user's part, using the resonator connection examples shown in this section as a reference. As the parameters for the resonator will depend on the floating capacitance of the resonator and the mounting circuit, the parameters should be determined in consultation with the resonator manufacturer. The design must ensure that a voltage exceeding the maximum rating is not applied to the resonator pin. 22.6.3 Notes on Board Design When using the crystal resonator, place the crystal resonator and its load capacitors as close to the XTAL and EXTAL pins as possible. Other signal lines should be routed away from the oscillation circuit as shown in Figure 22.10 to prevent induction from interfering with correct oscillation. Inhibited CL2 XTAL EXTAL CL1 Signal A Signal B This LSI Figure 22.10 Note on Board Design for Oscillation Circuit Rev.1.00 Jun. 07, 2006 Page 968 of 1102 REJ09B0294-0100 Section 22 Clock Pulse Generator Figure 22.11 shows the external circuitry recommended for the PLL circuit. Separate PLLVcc and PLLVss from the other Vcc and Vss lines at the board power supply source, and be sure to insert bypass capacitors CPB and CB close to the pins. Rp: 100 PLLVCC CPB: 0.1 F* PLLVSS VCC CB: 0.1 F* VSS Note: * CB and CPB are laminated ceramic capacitors. Figure 22.11 Recommended External Circuitry for PLL Circuit Rev.1.00 Jun. 07, 2006 Page 969 of 1102 REJ09B0294-0100 Section 22 Clock Pulse Generator Rev.1.00 Jun. 07, 2006 Page 970 of 1102 REJ09B0294-0100 Section 23 Power-Down Modes Section 23 Power-Down Modes This LSI has power consumption reduction functions, such as multi-clock function, module stop function, and transition function to power-down mode. 23.1 Features * Multi-clock function * The frequency division ratio is settable independently for the system clock, peripheral module clock, and external bus clock. * The system clock, peripheral module clock, and external bus clock can be uniformly set to the 32.768 kHz subclock. * Module stop function The functions for each peripheral modules can be stopped to make a transition to a powerdown mode. * Transition function to power-down mode Transition to a power-down mode is possible to stop the CPU, peripheral modules, and oscillator. * Four power-down modes Sleep mode All-module-clock-stop mode Software standby mode Hardware standby mode Rev.1.00 Jun. 07, 2006 Page 971 of 1102 REJ09B0294-0100 Section 23 Power-Down Modes Table 23.1 shows conditions to shift to a power-down mode, states of the CPU and peripheral modules, and clearing method for each mode. After the reset state, since this LSI operates in normal program execution state, the modules, other than the DMAC and DTC are stopped. Table 23.1 Operating States Operating State Transition condition Cancellation method Oscillator Sleep Mode Control register + instruction Interrupt Functioning 6 All-Module-Clock- Software Standby Hardware Stop Mode Mode Standby Mode Control register + instruction Interrupt* 2 Control register + instruction Interrupt* Halted 5 Pin input Functioning Functioning* 6 Halted 6 Subclock oscillator Functioning* CPU Watchdog timer 8-bit timer 32K timer Peripheral modules I/O port Functioning* Halted Halted Halted Halted Halted Halted* Hi-Z 3 Halted (retained) Functioning Functioning Functioning Functioning Functioning Halted (retained) Functioning Functioning* Functioning Halted* 1 4 Halted (retained) Halted (retained) Halted (retained) Functioning Halted* 1 Retained Retained Notes: "Halted (retained)" in the table means that the internal register values are retained and internal operations are suspended. 1. SCI enters the reset state, and other peripheral modules retain their states. 2. External interrupt and some internal interrupts (8-bit timer, watchdog timer, and 32K timer) 3. All peripheral modules enter the reset state. 4. "Functioning" or "Halted" is selectable through the setting of bits MSTPA9 and MSTPA8 in MSTPCRA. However, pin output is disabled even when "Functioning" is selected. 5. External interrupt and 32K timer interrupt 6. "Functioning" or "Halted" is selectable through the setting of bit OSC32STP in TCR32K. Rev.1.00 Jun. 07, 2006 Page 972 of 1102 REJ09B0294-0100 Section 23 Power-Down Modes RES pin = low Reset state RES pin = high Main clock operation (CK32K = 0) STBY pin = high RES pin = low STBY pin = low Hardware standby mode SLEEP instruction *3 Program halted state SSBY = 1 Software standby mode Interrupt*2 All interrupts SSBY = 0 Sleep mode SSBY = 0, ACSE = 1 MSTPCR = H'F[C-F]FFFFFF All-module-clockstop mode SLEEP instruction*3 Program execution state SLEEP inst ruction* 3 Interrupt*1 CK32K = 0 Subclock operation (CK32K = 0) CK32K = 1 WAKE32K = 0 and Interrupt*2 SLEEP instruction Program halted state SSBY = 1 Software standby mode WAKE32K = 1 and Interrupt*2 All interrupts SSBY = 0 Sleep mode SLEEP instruction Program execution state SLEEP in struct ion SSBY = 0, ACSE = 1 MSTPCR = H'F[C-F]FFFFFF Interrupt*1 All-module-clockstop mode [Legend] Transition after exception handling Notes: 1. NMI, IRQ0 to IRQ11, 8-bit timer interrupts, watchdog timer interrupts, and 32K timer interrupts. Note that the 8-bit timer interrupt is valid when the MSTPCRA9 or MSTPCRA8 bit is cleared to 0 2. NMI, IRQ0 to IRQ11, and 32K timer interrupts. Note that IRQ is valid only when the corresponding bit in SSIER is set to 1. 3. The SLPIE bit is 0. Notes: * From any state, a transition to hardware standby mode occurs when STBY is driven low. * From any state except hardware syandby mode, a transition to the reset state occurs when RES is driven low. Figure 23.1 Mode Transitions 23.2 Register Descriptions The registers related to the power-down modes are shown below. For details on the system clock control register (SCKCR), refer to section 22.1.1, System Clock Control Register (SCKCR). * Standby control register (SBYCR) * Module stop control register A (MSTPCRA) * Module stop control register B (MSTPCRB) * Module stop control register C (MSTPCRC) Rev.1.00 Jun. 07, 2006 Page 973 of 1102 REJ09B0294-0100 Section 23 Power-Down Modes 23.2.1 Standby Control Register (SBYCR) SBYCR controls software standby mode. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 SSBY 0 R/W 7 SLPIE 0 R/W 14 OPE 1 R/W 6 0 R/W 13 0 R/W 5 0 R/W 12 STS4 0 R/W 4 0 R/W 11 STS3 1 R/W 3 0 R/W 10 STS2 1 R/W 2 0 R/W 9 STS1 1 R/W 1 0 R/W 8 STS0 1 R/W 0 0 R/W Bit 15 Bit Name SSBY Initial Value 0 R/W R/W Description Software Standby Specifies the transition mode after executing the SLEEP instruction 0: Shifts to sleep mode after the SLEEP instruction is executed 1: Shifts to software standby mode after the SLEEP instruction is executed This bit does not change when clearing the software standby mode by using external interrupts and shifting to normal operation. For clearing, write 0 to this bit. When the WDT is used as the watchdog timer, the setting of this bit is disabled. In this case, a transition is always made to sleep mode or all-module-clock-stop mode after the SLEEP instruction is executed. When the SLPIE bit is set to 1, this bit should be cleared to 0. Output Port Enable Specifies whether the output of the address bus and bus control signals (CS0 to CS7, AS, RD, HWR, and LWR) is retained or set to the high-impedance state in software standby mode. 0: In software standby mode, address bus and bus control signals are high-impedance 1: In software standby mode, address bus and bus control signals retain output state 14 OPE 1 R/W Rev.1.00 Jun. 07, 2006 Page 974 of 1102 REJ09B0294-0100 Section 23 Power-Down Modes Bit 13 Bit Name Initial Value 0 R/W R/W Description Reserved This bit is always read as 0. The write value should always be 0. 12 11 10 9 8 STS4 STS3 STS2 STS1 STS0 0 1 1 1 1 R/W R/W R/W R/W R/W Standby Timer Select 4 to 0 These bits select the time the MCU waits for the clock to settle when software standby mode is cleared by an external interrupt or when a transition is made from the subclock operation to the main clock operation. For a crystal resonator, refer to table 23.2 and make a selection according to the operating frequency so that the standby time is at least equal to the oscillation settling time. With an external clock, a PLL circuit settling time is necessary. Refer to table 23.2 to set the standby time. While oscillation is being settled, the timer is counted on the P clock frequency. Careful consideration is required in multi-clock mode. 00000: Reserved 00001: Reserved 00010: Reserved 00011: Reserved 00100: Reserved 00101: Standby time = 64 states 00110: Standby time = 512 states 00111: Standby time = 1024 states 01000: Standby time = 2048 states 01001: Standby time = 4096 states 01010: Standby time = 16384 states 01011: Standby time = 32768 states 01100: Standby time = 65536 states 01101: Standby time = 131072 states 01110: Standby time = 262144 states 01111: Standby time = 524288 states 1XXXX: Reserved Rev.1.00 Jun. 07, 2006 Page 975 of 1102 REJ09B0294-0100 Section 23 Power-Down Modes Bit 7 Bit Name SLPIE Initial Value 0 R/W R/W Description Sleep Instruction Exception Handling Enable Selects whether the execution of a SLEEP instruction initiates sleep instruction exception handling or a transition to the power-down state. 0: The execution of a SLEEP instruction does not initiate sleep instruction exception handling. 1: The execution of a SLEEP instruction initiates sleep instruction exception handling. After execution of the sleep instruction exception handling, this bit remains set to 1. Writing 0 clears this bit. 6 to 0 All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. [Legend] X: Don't care Note: With the F-ZTAT version, the flash memory settling time must be reserved. 23.2.2 Module Stop Control Registers A and B (MSTPCRA and MSTPCRB) MSTPCRA and MSTPCRB set the module stop function. Setting a bit to 1 makes the corresponding module enter the module stop state, while clearing the bit to 0 clears the module stop state. * MSTPCRA Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 ACSE 0 R/W 7 MSTPA7 1 R/W 14 MSTPA14 0 R/W 6 MSTPA6 1 R/W 13 MSTPA13 0 R/W 5 MSTPA5 1 R/W 12 MSTPA12 0 R/W 4 MSTPA4 1 R/W 11 MSTPA11 1 R/W 3 MSTPA3 1 R/W 10 MSTPA10 1 R/W 2 MSTPA2 1 R/W 9 MSTPA9 1 R/W 1 MSTPA1 1 R/W 8 MSTPA8 1 R/W 0 MSTPA0 1 R/W Rev.1.00 Jun. 07, 2006 Page 976 of 1102 REJ09B0294-0100 Section 23 Power-Down Modes * MSTPCRB Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 MSTPB15 1 R/W 7 MSTPB7 1 R/W 14 MSTPB14 1 R/W 6 MSTPB6 1 R/W 13 MSTPB13 1 R/W 5 MSTPB5 1 R/W 12 MSTPB12 1 R/W 4 MSTPB4 1 R/W 11 MSTPB11 1 R/W 3 MSTPB3 1 R/W 10 MSTPB10 1 R/W 2 MSTPB2 1 R/W 9 MSTPB9 1 R/W 1 MSTPB1 1 R/W 8 MSTPB8 1 R/W 0 MSTPB0 1 R/W * MSTPCRA Bit 15 Bit Name ACSE Initial Value 0 R/W R/W Module All-Module-Clock-Stop Mode Enable Enables/disables all-module-clock-stop mode for reducing current consumption by stopping the bus controller and I/O ports operations when the CPU executes the SLEEP instruction after the module stop state has been set for all the on-chip peripheral modules controlled by MSTPCR. 0: All-module-clock-stop mode disabled 1: All-module-clock-stop mode enabled 14 13 12 11 10 9 8 7 6 MSTPA14 0 MSTPA13 0 MSTPA12 0 MSTPA11 1 MSTPA10 1 MSTPA9 MSTPA8 MSTPA7 MSTPA6 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reserved DMA controller (DMAC) Data transfer controller (DTC) Reserved These bits are always read as 1. The write value should always be 1. 8-bit timer (TMR_3 and TMR_2) 8-bit timer (TMR_1 and TMR_0) Reserved These bits are always read as 1. The write value should always be 1. Rev.1.00 Jun. 07, 2006 Page 977 of 1102 REJ09B0294-0100 Section 23 Power-Down Modes Bit 5 4 Bit Name MSTPA5 MSTPA4 Initial Value 1 1 R/W R/W R/W Module D/A converter (channels 1 and 0) Reserved This bit is always read as 1. The write value should always be 1. 3 2 1 0 MSTPA3 MSTPA2 MSTPA1 MSTPA0 1 1 1 1 R/W R/W R/W R/W A/D converter (unit 0) Reserved These bits are always read as 1. The write value should always be 1. 16-bit timer pulse unit (TPU channels 5 to 0) * MSTPCRB Bit 15 14 13 12 11 Bit Name Initial Value R/W R/W R/W R/W R/W R/W Module Programmable pulse generator (PPG) Reserved These bits are always read as 1. The write value should always be 1. Serial communication interface_4 (SCI_4) Reserved This bit is always read as 1. The write value should always be 1. 10 9 8 7 6 5 4 3 2 1 0 MSTPB10 1 MSTPB9 MSTPB8 MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Serial communication interface_2 (SCI_2) Serial communication interface_1 (SCI_1) Serial communication interface_0 (SCI_0) I C bus Interface 1 (IIC_1) I C bus Interface 0 (IIC_0) Reserved These bits are always read as 1. The write value should always be 1. 2 2 MSTPB15 1 MSTPB14 1 MSTPB13 1 MSTPB12 1 MSTPB11 1 Rev.1.00 Jun. 07, 2006 Page 978 of 1102 REJ09B0294-0100 Section 23 Power-Down Modes 23.2.3 Module Stop Control Register C (MSTPCRC) When bits MSTPC4 to MSTPC0 are set to 1, the corresponding on-chip RAM stops. Do not set the corresponding MSTPC4 to MSTPC0 bits to 1 while accessing the on-chip RAM. Do not access the on-chip RAM while bits MSTPC4 to MSTPC0 are set to 1. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 MSTPC15 1 R/W 7 MSTPC7 0 R/W 14 MSTPC14 1 R/W 6 MSTPC6 0 R/W 13 MSTPC13 1 R/W 5 MSTPC5 0 R/W 12 MSTPC12 1 R/W 4 MSTPC4 0 R/W 11 MSTPC11 1 R/W 3 MSTPC3 0 R/W 10 MSTPC10 1 R/W 2 MSTPC2 0 R/W 9 MSTPC9 1 R/W 1 MSTPC1 0 R/W 8 MSTPC8 1 R/W 0 MSTPC0 0 R/W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Module Serial communication interface_5 (SCI_5), (IrDA) Serial communication interface_6 (SCI_6) 8-bit timer (TMR_4, TMR_5) 8-bit timer (TMR_6, TMR_7) Universal serial bus interface (USB) Cyclic redundancy check Reserved These bits are always read as 1. The write value should always be 1. Reserved These bits are always read as 0. The write value should always be 0. On-chip RAM_4 (H'FF2000 to H'FF3FFF) On-chip RAM_3 (H'FF4000 to H'FF5FFF) On-chip RAM_2 (H'FF6000 to H'FF7FFF) On-chip RAM_1 (H'FF8000 to H'FF9FFF) On-chip RAM_0 (H'FFA000 to H'FFBFFF) MSTPC15 1 MSTPC14 1 MSTPC13 1 MSTPC12 1 MSTPC11 1 MSTPC10 1 MSTPC9 MSTPC8 MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 1 1 0 0 0 0 0 0 0 0 Rev.1.00 Jun. 07, 2006 Page 979 of 1102 REJ09B0294-0100 Section 23 Power-Down Modes 23.3 23.3.1 Multi-Clock Function Switching of Main Clock When bits ICK2 to ICK0, PCK2 to PCK0, and BCK2 to BCK0 in SCKCR are set, the main clock frequency changes at the end of the bus cycle. The CPU and bus masters operate on the operating clock specified by bits ICK2 to ICK0. The peripheral modules operate on the operating clock specified by bits PCK2 to PCK0. The external bus clock operates on the operating clock specified by bits BCK2 to BCK0. Even if the frequencies specified by bits PCK2 to PCK0 and BCK2 to BCK0 are higher than the frequency specified by bits ICK2 to ICK0, the specified values are not reflected in the peripheral module and external bus clocks. The peripheral module and external bus clocks are restricted to the operating clock specified by bits ICK2 to ICK0. 23.3.2 Switching to Subclock When the CK32K bit in SUBCKCR is set to 1, a transition from the main clock operation to the subclock operation is made at the end of the bus cycle regardless of the SCKCR setting. In the subclock operation, the CPU, bus masters, peripheral modules, and all external buses operate on the 32.768-kHz subclock. When the CK32K bit in SUBCKCR is set to 0 in the subclock operation, a transition to the main clock operation is made at the end of the bus cycle. Since a transition from the subclock operation to the main clock operation is made via software standby mode, the oscillation settling time of the main clock must elapse. Set the oscillation settling time of the main clock with bits STS4 to STS0 in SBYCR. The main clock oscillator can be operated or stopped by the EXSTP bit in SUBCKCR in the subclock operation. When a transition is made from the subclock operation to the main clock operation with the main clock oscillator operating, the wait for the oscillation settling time of the main clock oscillator is not necessary. A transition to the main clock operation can be made in the minimum setting time with the setting of bits STS4 to STS0 in SBYCR. In the same way as in the main clock operation, if a SLEEP instruction is executed in the subclock operation while the SSBY bit in SBYCR is set to 1, this LSI enters software standby mode. When a transition is made to software standby mode in the subclock operation, the operating clock of the system clock after clearing of software standby mode can be selected with the WAKE32K bit in SUBCKCR. This LSI is placed in the subclock operation if the WAKE32K bit is 1, or placed in the main clock operation if the WAKE32K bit is 0. Rev.1.00 Jun. 07, 2006 Page 980 of 1102 REJ09B0294-0100 Section 23 Power-Down Modes 23.4 Module Stop Function Module stop function can be set for individual on-chip peripheral modules. When the corresponding MSTP bit in MSTPCRA, MSTPCRB, or MSTPCRC is set to 1, module operation stops at the end of the bus cycle and a transition is made to the module stop state. The CPU continues operating independently. When the corresponding MSTP bit is cleared to 0, the module stop state is cleared and the module starts operating at the end of the bus cycle. In the module stop state, the internal states of modules other than the SCI are retained. After the reset state is cleared, all modules other than the DMAC, DTC, and on-chip RAM are in the module stop state. The registers of the module for which the module stop state is selected cannot be read from or written to. 23.5 23.5.1 Sleep Mode Transition to Sleep Mode When the SLEEP instruction is executed when the SSBY bit in SBYCR is 0, the CPU enters sleep mode. In sleep mode, CPU operation stops but the contents of the CPU's internal registers are retained. Other peripheral functions do not stop. 23.5.2 Clearing Sleep Mode Sleep mode is exited by any interrupt, signals on the RES or STBY pin, and a reset caused by a watchdog timer overflow. 1. Clearing by interrupt When an interrupt occurs, sleep mode is exited and interrupt exception processing starts. Sleep mode is not exited if the interrupt is disabled, or interrupts other than NMI are masked by the CPU. 2. Clearing by RES pin Setting the RES pin level low selects the reset state. After the stipulated reset input duration, driving the RES pin high makes the CPU start the reset exception processing. Rev.1.00 Jun. 07, 2006 Page 981 of 1102 REJ09B0294-0100 Section 23 Power-Down Modes 3. Clearing by STBY pin When the STBY pin level is driven low, a transition is made to hardware standby mode. 4. Clearing by reset caused by watchdog timer overflow Sleep mode is exited by an internal reset caused by a watchdog timer overflow. 23.6 All-Module-Clock-Stop Mode When the ACSE bit is set to 1 and all modules controlled by MSTPCRA/MSTPCRB are stopped (MSTPCRA/MSTPCRB = H'FFFFFFFF), or all modules except for the 8-bit timer are stopped (MSTPCRA/MSTPCRB = H'F[C to F]FFFFFF), executing a SLEEP instruction with the SSBY bit in SBYCR cleared to 0 will cause all modules (except for the 8-bit timer*, watchdog timer, and 32K timer), the bus controller, and the I/O ports to stop operating, and to make a transition to allmodule-clock-stop mode at the end of the bus cycle. When further reduction in power consumption is necessary in all-module-clock-stop mode, stop the modules controlled by MSTPCRC (MSTPCRC[15 to 8] = H'FFFF). All-module-clock-stop mode is cleared by an external interrupt (NMI or IRQ0 to IRQ11 pins), RES pin, or an internal interrupt (8-bit timer*, watchdog timer, or 32K timer), and the CPU returns to the normal program execution state via the exception handling state. All-module-clockstop mode is not cleared if interrupts are disabled, if interrupts other than NMI are masked on the CPU side, or if the relevant interrupt is designated as a DTC activation source. When the STBY pin is driven low, a transition is made to hardware standby mode. Note: * Operation or halting of the 8-bit timer can be selected by bits MSTPA9 and MSTPA8 in MSTPCRA. Rev.1.00 Jun. 07, 2006 Page 982 of 1102 REJ09B0294-0100 Section 23 Power-Down Modes 23.7 23.7.1 Software Standby Mode Transition to Software Standby Mode If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, software standby mode is entered. In this mode, the CPU, on-chip peripheral functions, and oscillator all stop. However, the contents of the CPU's internal registers, on-chip RAM data, and the states of on-chip peripheral functions other than the SCI, and the states of the I/O ports, are retained. Whether the address bus and bus control signals are placed in the high-impedance state or retain the output state can be specified by the OPE bit in SBYCR. In this mode the oscillator stops, allowing power consumption to be significantly reduced. If the WDT is used as a watchdog timer, it is impossible to make a transition to software standby mode. The WDT should be stopped before the SLEEP instruction execution. 23.7.2 Clearing Software Standby Mode Software standby mode is cleared by an external interrupt (NMI pin, or pins IRQ0 to IRQ11*), internal interrupt (32K timer) or by means of the RES pin or STBY pin. 1. Clearing by interrupt When an NMI or IRQ0 to IRQ11* interrupt request signal is input, clock oscillation starts, and after the elapse of the time set in bits STS4 to STS0 in SBYCR, stable clocks are supplied to the entire LSI, software standby mode is cleared, and interrupt exception handling is started. When clearing software standby mode with an IRQ0 to IRQ11* interrupt, set the corresponding enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ0 to IRQ11* is generated. Software standby mode cannot be cleared if the interrupt has been masked on the CPU side or has been designated as a DTC activation source. Note: * By setting the SSIn bit in SSIER to 1, IRQ0 to IRQ11 can be used as a software standby mode clearing source. 2. Clearing by RES pin When the RES pin is driven low, clock oscillation is started. At the same time as clock oscillation starts, clocks are supplied to the entire LSI. Note that the RES pin must be held low until clock oscillation settles. When the RES pin goes high, the CPU begins reset exception handling. 3. Clearing by STBY pin When the STBY pin is driven low, a transition is made to hardware standby mode. Rev.1.00 Jun. 07, 2006 Page 983 of 1102 REJ09B0294-0100 Section 23 Power-Down Modes 23.7.3 Setting Oscillation Settling Time after Clearing Software Standby Mode Bits STS4 to STS0 in SBYCR should be set as described below. 1. Using a crystal resonator Set bits STS4 to STS0 so that the standby time is at least equal to the oscillation settling time. Table 23.2 shows the standby times for operating frequencies and settings of bits STS4 to STS0. 2. Using an external clock A PLL circuit settling time is necessary. Refer to table 23.2 to set the standby time. Table 23.2 Oscillation Settling Time Settings Standby STS4 STS3 STS2 STS1 STS0 Time 0 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 0 Reserved Reserved Reserved Reserved Reserved 64 512 1024 2048 4096 16384 32768 65536 131072 262144 524288 Reserved P* [MHz] 35 1.8 14.6 29.3 58.5 0.12 0.47 0.94 1.87 3.74 7.49 14.98 25 2.6 20.5 41.0 81.9 0.16 0.66 1.31 2.62 5.24 10.49 20.97 20 3.2 25.6 51.2 102.4 0.20 0.82 1.64 3.28 6.55 13.11 26.21 ms Unit s : Recommended time setting when using an external clock. : Recommended time setting when using a crystal resonator. Note: * P is the output from the peripheral module frequency divider. Rev.1.00 Jun. 07, 2006 Page 984 of 1102 REJ09B0294-0100 Section 23 Power-Down Modes P* [MHz] 13 4.9 39.4 78.8 157.5 0.32 1.26 2.52 5.04 10.08 20.16 40.33 10 6.4 51.2 102.4 204.8 0.41 1.64 3.28 6.55 13.11 26.21 52.43 8 8.0 64.0 128.0 256.0 0.51 2.05 4.10 8.19 16.38 32.77 65.54 ms Unit s Standby STS4 STS3 STS2 STS1 STS0 Time 0 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 0 Reserved Reserved Reserved Reserved Reserved 64 512 1024 2048 4096 16384 32768 65536 131072 262144 524288 Reserved : Recommended time setting when using an external clock. : Note: Recommended time setting when using a crystal resonator. * is the output from the peripheral module frequency divider. Rev.1.00 Jun. 07, 2006 Page 985 of 1102 REJ09B0294-0100 Section 23 Power-Down Modes 23.7.4 Software Standby Mode Application Example Figure 23.2 shows an example in which a transition is made to software standby mode at the falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI pin. In this example, an NMI interrupt is accepted with the NMIEG bit in INTCR cleared to 0 (falling edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set to 1, and a SLEEP instruction is executed, causing a transition to software standby mode. Software standby mode is then cleared at the rising edge on the NMI pin. Oscillator I NMI NMIEG SSBY NMI exception handling NMIEG = 1 SSBY = 1 Software standby mode (power-down mode) NMI exception handling Oscillation settling time tOSC2 SLEEP instruction Figure 23.2 Software Standby Mode Application Example Rev.1.00 Jun. 07, 2006 Page 986 of 1102 REJ09B0294-0100 Section 23 Power-Down Modes 23.8 23.8.1 Hardware Standby Mode Transition to Hardware Standby Mode When the STBY pin is driven low, a transition is made to hardware standby mode from any mode. In hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power consumption. As long as the prescribed voltage is supplied, on-chip RAM data is retained. I/O ports are set to the high-impedance state. In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before driving the STBY pin low. Do not change the state of the mode pins (MD2 to MD0) while this LSI is in hardware standby mode. 23.8.2 Clearing Hardware Standby Mode Hardware standby mode is cleared by means of the STBY pin and the RES pin. When the STBY pin is driven high while the RES pin is low, the reset state is entered and clock oscillation is started. Ensure that the RES pin is held low until clock oscillation settles (for details on the oscillation settling time, refer to table 23.2). When the RES pin is subsequently driven high, a transition is made to the program execution state via the reset exception handling state. 23.8.3 Hardware Standby Mode Timing Figure 23.3 shows an example of hardware standby mode timing. When the STBY pin is driven low after the RES pin has been driven low, a transition is made to hardware standby mode. Hardware standby mode is cleared by driving the STBY pin high, waiting for the oscillation settling time, then changing the RES pin from low to high. Oscillator RES STBY Oscillation settling time Reset exception handling Figure 23.3 Hardware Standby Mode Timing Rev.1.00 Jun. 07, 2006 Page 987 of 1102 REJ09B0294-0100 Section 23 Power-Down Modes 23.8.4 Timing Sequence at Power-On Figure 23.4 shows the timing sequence at power-on. At power-on, the RES pin must be driven low with the STBY pin driven high for a given time in order to clear the reset state. To enter hardware standby mode immediately after power-on, drive the STBY pin low after exiting the reset state. For details on clearing hardware standby mode, see section 23.8.3, Hardware Standby Mode Timing. 1 Power supply RES 2 STBY Reset state 3 Hardware standby mode Figure 23.4 Timing Sequence at Power-On Rev.1.00 Jun. 07, 2006 Page 988 of 1102 REJ09B0294-0100 Section 23 Power-Down Modes 23.9 Sleep Instruction Exception Handling Sleep instruction exception handling is exception handling initiated by the execution of a SLEEP instruction. Sleep instruction exception handling is always accepted while the program is in execution. When the SLPIE bit is set to 0, the execution of a SLEEP instruction does not initiate sleep instruction exception handling. Instead, the CPU enters the power-down state. After this, generation of an exception handling request that cancels the power-down state causes the powerdown state to be canceled, after which the CPU starts to handle the exception. When the SLPIE bit is set to 1, sleep instruction exception handling starts after the execution of a SLEEP instruction. Transitions to the power-down state are inhibited when sleep instruction exception handling is initiated, and the CPU immediately starts sleep instruction exception handling. When a SLEEP instruction is executed while the SLPIE bit is cleared to 0, a transition is made to the power-down state. The power-down state is canceled by a canceling factor interrupt (see figure 23.5). When a canceling factor interrupt is generated immediately before the execution of a SLEEP instruction, exception handling for the interrupt starts. When execution returns from the interrupt handling routine, the SLEEP instruction is executed to enter the power-down state. In this case, the power-down state is not canceled until the next canceling factor interrupt is generated (see figure 23.6). When the SLPIE bit is set to 1 in the handling routine for a canceling factor interrupt so that the execution of a SLEEP instruction will produce sleep instruction exception handling, the operation of the system is as shown in figure 23.7. Even if a canceling factor interrupt is generated immediately before the SLEEP instruction is executed, sleep instruction exception handling is initiated by execution of the SLEEP instruction. Therefore, the CPU executes the instruction that follows the SLEEP instruction after sleep instruction exception and exception service routine without shifting to the power-down state. When the SLPIE bit is set to 1 to start sleep exception handling, clear the SSBY bit in SBYCR to 0. Rev.1.00 Jun. 07, 2006 Page 989 of 1102 REJ09B0294-0100 Section 23 Power-Down Modes SLPIE = 0 Instruction before SLEEP instruction SLEEP instruction executed (SLPIE = 0) Power-down state Yes Canceling factor interrupt No Interrupt handling routine RTE instruction executed Transition by interrupt exception handling Instruction after SLEEP instruction Figure 23.5 When Canceling Factor Interrupt is Generated after SLEEP Instruction Execution SLPIE = 0 Instruction before SLEEP instruction Yes Canceling factor interrupt No Transition by interrupt exception handling Interrupt handling routine RTE instruction executed SLEEP instruction executed (SLPIE = 0) Return from the powerdown state after the next canceling factor interrupt is generated Power-down state Yes Canceling factor interrupt No Interrupt handling routine RTE instruction executed Transition by interrupt exception handling Instruction after SLEEP instruction Figure 23.6 When Canceling Factor Interrupt is Generated Immediately before SLEEP Instruction Execution (Sleep Instruction Exception Handling Not Initiated) Rev.1.00 Jun. 07, 2006 Page 990 of 1102 REJ09B0294-0100 Section 23 Power-Down Modes SLPIE = 0 Instruction before SLEEP instruction Yes Canceling factor interrupt No Transition by interrupt exception handling Interrupt handling routine RTE instruction executed SLPIE = 1 SSBY = 0 SLEEP instruction executed (SLPIE = 1) Sleep instruction exceotion handling Transition by sleep exception handling Vector Number 18 Exception service routine RTE instruction executed Instruction after SLEEP instruction Figure 23.7 When Canceling Factor Interrupt is Generated Immediately before SLEEP Instruction Execution (Sleep Instruction Exception Handling Initiated) Rev.1.00 Jun. 07, 2006 Page 991 of 1102 REJ09B0294-0100 Section 23 Power-Down Modes 23.10 Clock Output Control Output of the clock (B/SD) can be controlled by bits PSTOP1, and PSTOP0 in SCKCR, and DDR for the corresponding port. Bits PSTOP1 control the B clock output on the PA7 pin. Bit PSTOP0 controls the SD clock output on the PB7 pin. When bit PSTOP1 is set to 1, the B clock output stops at the end of the bus cycle and goes high. In the same way, bit PSTOP0 drives the SD clock output on the PB7 pin high. When DDR for the PA7 pin is cleared to 0, the B clock output is disabled and the pin becomes an input port. When the SDRAM interface is disabled, the PB7 pin can be used as I/O port. Tables 23.3 and 23.4 show the states of the pin in each processing state. Table 23.3 Pin (PA7) State in Each Processing State Register Setting Value DDR 0 1 1 PSTOP1 Normal Operating Sleep Mode State Hi-Z B output High Hi-Z B output High AllSoftware Standby ModuleMode ClockStop Mode OPE = 0 OPE = 1 Hi-Z B output High Hi-Z High High Hi-Z High High Hardware Standby Mode Hi-Z Hi-Z Hi-Z X 0 1 Table 23.4 Pin (PB7) State in Each Processing State (SDRAM Interface Enabled) Register Setting Value PSTOP0 Normal Operating Sleep Mode State AllSoftware Standby ModuleMode ClockStop Mode OPE = 0 OPE = 1 High High Hardware Standby Mode Hi-Z Hi-Z 0 1 SD output SD output SD output High High High High High Rev.1.00 Jun. 07, 2006 Page 992 of 1102 REJ09B0294-0100 Section 23 Power-Down Modes 23.11 Usage Notes 23.11.1 I/O Port Status In software standby mode, the I/O port states are retained. Therefore, there is no reduction in current consumption for the output current when a high-level signal is output. 23.11.2 Current Consumption during Oscillation Settling Standby Period Current consumption increases during the oscillation settling standby period. 23.11.3 Module Stop Mode of DMAC or DTC Depending on the operating state of the DMAC and DTC, bits MSTPA13 and MSTPA12 may not be set to 1, respectively. The module stop state setting for the DMAC or DTC should be performed only when the DMAC or DTC is not activated. For details, refer to section 7, DMA Controller (DMAC), and section 8, Data Transfer Controller (DTC). 23.11.4 On-Chip Peripheral Module Interrupts Relevant interrupt operations cannot be performed in the module stop state. Consequently, if the module stop state is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DMAC or DTC activation source. Interrupts should therefore be disabled before entering the module stop state. 23.11.5 Writing to MSTPCRA, MSTPCRB, and MSTPCRC MSTPCRA, MSTPCRB, and MSTPCRC should only be written to by the CPU. Rev.1.00 Jun. 07, 2006 Page 993 of 1102 REJ09B0294-0100 Section 23 Power-Down Modes Rev.1.00 Jun. 07, 2006 Page 994 of 1102 REJ09B0294-0100 Section 24 List of Registers Section 24 List of Registers The register list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. Register addresses (address order) * Registers are listed from the lower allocation addresses. * Registers are classified according to functional modules. * The number of Access Cycles indicates the number of states based on the specified reference clock. For details, refer to section 6.5.4, External Bus Interface. * Among the internal I/O register area, addresses not listed in the list of registers are undefined or reserved addresses. Undefined and reserved addresses cannot be accessed. Do not access these addresses; otherwise, the operation when accessing these bits and subsequent operations cannot be guaranteed. 2. Register bits * Bit configurations of the registers are listed in the same order as the register addresses. * Reserved bits are indicated by in the bit name column. * Space in the bit name field indicates that the entire register is allocated to either the counter or data. * For the registers of 16 or 32 bits, the MSB is listed first. * Byte configuration description order is subject to big endian. 3. Register states in each operating mode * Register states are listed in the same order as the register addresses. * For the initialized state of each bit, refer to the register description in the corresponding section. * The register states shown here are for the basic operating modes. If there is a specific reset for an on-chip peripheral module, refer to the section on that on-chip peripheral module. Rev.1.00 Jun. 07, 2006 Page 995 of 1102 REJ09B0294-0100 Section 24 List of Registers 24.1 Register Addresses (Address Order) Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Data Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8 8 8 8 8 8 Access Cycles (Read/Write) 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P Register Name Timer control register_4 Timer control register_5 Timer control/status register_4 Timer control/status register_5 Time constant registerA_4 Time constant registerA_5 Time constant registerB_4 Time constant registerB_5 Timer counter_4 Timer counter_5 Timer counter control register_4 Timer counter control register_5 CRC control register CRC data input register CRC data output register Timer control register_6 Timer control register_7 Timer control/status register_6 Timer control/status register_7 Time constant registerA_6 Time constant registerA_7 Time constant registerB_6 Time constant registerB_7 Timer counter_6 Timer counter_7 Timer counter control register_6 Timer counter control register_7 Interrupt flag register 0 Interrupt flag register 1 Interrupt flag register 2 Interrupt enable register 0 Interrupt enable register 1 Interrupt enable register 2 Abbreviation TCR_4 TCR_5 TCSR_4 TCSR_5 TCORA_4 TCORA_5 TCORB_4 TCORB_5 TCNT_4 TCNT_5 TCCR_4 TCCR_5 CRCCR CRCDIR CRCDOR TCR_6 TCR_7 TCSR_6 TCSR_7 TCORA_6 TCORA_7 TCORB_6 TCORB_7 TCNT_6 TCNT_7 TCCR_6 TCCR_7 IFR0 IFR1 IFR2 IER0 IER1 IER2 Address H'FEA40 H'FEA41 H'FEA42 H'FEA43 H'FEA44 H'FEA45 H'FEA46 H'FEA47 H'FEA48 H'FEA49 H'FEA4A H'FEA4B H'FEA4C H'FEA4D H'FEA4E H'FEA50 H'FEA51 H'FEA52 H'FEA53 H'FEA54 H'FEA55 H'FEA56 H'FEA57 H'FEA58 H'FEA59 H'FEA5A H'FEA5B H'FEE00 H'FEE01 H'FEE02 H'FEE04 H'FEE05 H'FEE06 Module TMR_4 TMR_5 TMR_4 TMR_5 TMR_4 TMR_5 TMR_4 TMR_5 TMR_4 TMR_5 TMR_4 TMR_5 CRC CRC CRC TMR_6 TMR_7 TMR_6 TMR_7 TMR_6 TMR_7 TMR_6 TMR_7 TMR_6 TMR_7 TMR_6 TMR_7 USB USB USB USB USB USB Rev.1.00 Jun. 07, 2006 Page 996 of 1102 REJ09B0294-0100 Section 24 List of Registers Access Cycles (Read/Write) 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/-- 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P Register Name Interrupt select register 0 Interrupt select register 1 Interrupt select register 2 EP0i data register EP0o data register EP0s data register EP1 data register EP2 data register EP3 data register EP0o receive data size register EP1 receive data size register Data status register FIFO clear register Endpoint stall register Trigger register DMA transfer setting register Configuration value register Control register Endpoint information register Transceiver testregister0 Transceiver testregister1 Port M data direction register Port M data register Port M register Port M input buffer control register Serial mode register_5 Bit rate register_5 Serial control register_5 Transmit data register_5 Serial status register_5 Receive data register_5 Smart card mode register_5 Serial extended mode register_5 IrDA control register Serial mode register_6 Abbreviation ISR0 ISR1 ISR2 EPDR0i EPDR0o EPDR0s EPDR1 EPDR2 EPDR3 EPSZ0o EPSZ1 DASTS FCLR EPSTL TRG DMA CVR CTLR EPIR TRNTREG00 TRNTREG1 PMDDR PMDR PORTM PMICR SMR_5 BRR_5 SCR_5 TDR_5 SSR_5 RDR_5 SCMR_5 SEMR_5 IrCR SMR_6 Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address H'FEE08 H'FEE09 H'FEE0A H'FEE0C H'FEE0D H'FEE0E H'FEE10 H'FEE14 H'FEE18 H'FEE24 H'FEE25 H'FEE27 H'FEE28 H'FEE2A H'FEE2C H'FEE2D H'FEE2E H'FEE2F H'FEE32 H'FEE44 H'FEE45 H'FEE50 H'FEE51 H'FEE52 H'FEE53 H'FF600 H'FF601 H'FF602 H'FF603 H'FF604 H'FF605 H'FF606 H'FF608 H'FF60C H'FF610 Module USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB I/O port I/O port I/O port I/O port SCI_5 SCI_5 SCI_5 SCI_5 SCI_5 SCI_5 SCI_5 SCI_5 SCI_5 SCI_6 Data Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Rev.1.00 Jun. 07, 2006 Page 997 of 1102 REJ09B0294-0100 Section 24 List of Registers Access Cycles (Read/Write) 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P Register Name Bit rate register_6 Serial control register_6 Transmit data register_6 Serial status register_6 Receive data register_6 Smart card mode register_6 Serial extended mode register_6 Timer control register Timer counter Port 1 data direction register Port 2 data direction register Port 3 data direction register Port 6 data direction register Port A data direction register Port B data direction register Port C data direction register Port D data direction register Port E data direction register Port F data direction register Port 1 input buffer control register Port 2 input buffer control register Port 3 input buffer control register Port 5 input buffer control register Port 6 input buffer control register Port A input buffer control register Port B input buffer control register Port C input buffer control register Port D input buffer control register Port E input buffer control register Port F input buffer control register Port H register Port I register Port H data register Port I data register Port H data direction register Port I data direction register Abbreviation BRR_6 SCR_6 TDR_6 SSR_6 RDR_6 SCMR_6 SEMR_6 TCR32K TCNT32K P1DDR P2DDR P3DDR P6DDR PADDR PBDDR PCDDR PDDDR PEDDR PFDDR P1ICR P2ICR P3ICR P5ICR P6ICR PAICR PBICR PCICR PDICR PEICR PFICR PORTH PORTI PHDR PIDR PHDDR PIDDR Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address H'FF611 H'FF612 H'FF613 H'FF614 H'FF615 H'FF616 H'FF618 H'FFABC H'FFABD H'FFB80 H'FFB81 H'FFB82 H'FFB85 H'FFB89 H'FFB8A H'FFB8B H'FFB8C H'FFB8D H'FFB8E H'FFB90 H'FFB91 H'FFB92 H'FFB94 H'FFB95 H'FFB99 H'FFB9A H'FFB9B H'FFB9C H'FFB9D H'FFB9E H'FFBA0 H'FFBA1 H'FFBA4 H'FFBA5 H'FFBA8 H'FFBA9 Module SCI_6 SCI_6 SCI_6 SCI_6 SCI_6 SCI_6 SCI_6 TM32K TM32K I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port Data Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Rev.1.00 Jun. 07, 2006 Page 998 of 1102 REJ09B0294-0100 Section 24 List of Registers Access Cycles (Read/Write) 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/3P 2P/3P 2P/3P 2P/3P 2P/3P 2P/3P 2P/3P 2P/3P 2P/3P 2P/3P 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I Register Name Port H input buffer control register Port I input buffer control register Port D pull-up MOS control register Port E pull-up MOS control register Port F pull-up MOS control register Port H pull-up MOS control register Port I pull-up MOS control register Port 2 open-drain control register Port F open-drain control register Port function control register 0 Port function control register 1 Port function control register 2 Port function control register 4 Port function control register 6 Port function control register 7 Port function control register 9 Port function control register B Port function control register C Software standby release IRQ enable register DMA source address register_0 DMA destination address register_0 DMA offset register_0 DMA transfer count register_0 DMA block size register_0 DMA mode control register_0 DMA address control register_0 DMA source address register_1 DMA destination address register_1 DMA offset register_1 DMA transfer count register_1 DMA block size register_1 DMA mode control register_1 DMA address control register_1 DMA source address register_2 DMA destination address register_2 Abbreviation PHICR PIICR PDPCR PEPCR PFPCR PHPCR PIPCR P2ODR PFODR PFCR0 PFCR1 PFCR2 PFCR4 PFCR6 PFCR7 PFCR9 PFCRB PFCRC SSIER DSAR_0 DDAR_0 DOFR_0 DTCR_0 DBSR_0 DMDR_0 DACR_0 DSAR_1 DDAR_1 DOFR_1 DTCR_1 DBSR_1 DMDR_1 DACR_1 DSAR_2 DDAR_2 Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address H'FFBAC H'FFBAD H'FFBB4 H'FFBB5 H'FFBB6 H'FFBB8 H'FFBB9 H'FFBBC H'FFBBD H'FFBC0 H'FFBC1 H'FFBC2 H'FFBC4 H'FFBC6 H'FFBC7 H'FFBC9 H'FFBCB H'FFBCC H'FFBCE H'FFC00 H'FFC04 H'FFC08 H'FFC0C H'FFC10 H'FFC14 H'FFC18 H'FFC20 H'FFC24 H'FFC28 H'FFC2C H'FFC30 H'FFC34 H'FFC38 H'FFC40 H'FFC44 Module I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port INTC DMAC_0 DMAC_0 DMAC_0 DMAC_0 DMAC_0 DMAC_0 DMAC_0 DMAC_1 DMAC_1 DMAC_1 DMAC_1 DMAC_1 DMAC_1 DMAC_1 DMAC_2 DMAC_2 Data Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Rev.1.00 Jun. 07, 2006 Page 999 of 1102 REJ09B0294-0100 Section 24 List of Registers Access Cycles (Read/Write) 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I Register Name DMA offset register_2 DMA transfer count register_2 DMA block size register_2 DMA mode control register_2 DMA address control register_2 DMA source address register_3 DMA destination address register_3 DMA offset register_3 DMA transfer count register_3 DMA block size register_3 DMA mode control register_3 DMA address control register_3 DMA module request select register_0 DMA module request select register_1 DMA module request select register_2 DMA module request select register_3 Interrupt priority register A Interrupt priority register B Interrupt priority register C Interrupt priority register D Interrupt priority register E Interrupt priority register F Interrupt priority register G Interrupt priority register H Interrupt priority register I Interrupt priority register K Interrupt priority register L Interrupt priority register Q Interrupt priority register R IRQ sense control register H IRQ sense control register L DTC vector base register Bus width control register Access state control register Wait control register A Wait control register B Abbreviation DOFR_2 DTCR_2 DBSR_2 DMDR_2 DACR_2 DSAR_3 DDAR_3 DOFR_3 DTCR_3 DBSR_3 DMDR_3 DACR_3 DMRSR_0 DMRSR_1 DMRSR_2 DMRSR_3 IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRK IPRL IPRQ IPRR ISCRH ISCRL DTCVBR ABWCR ASTCR WTCRA WTCRB Number of Bits 32 32 32 32 32 32 32 32 32 32 32 32 8 8 8 8 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 32 16 16 16 16 Address H'FFC48 H'FFC4C H'FFC50 H'FFC54 H'FFC58 H'FFC60 H'FFC64 H'FFC68 H'FFC6C H'FFC70 H'FFC74 H'FFC78 H'FFD20 H'FFD21 H'FFD22 H'FFD23 H'FFD40 H'FFD42 H'FFD44 H'FFD46 H'FFD48 H'FFD4A H'FFD4C H'FFD4E H'FFD50 H'FFD54 H'FFD56 H'FFD60 H'FFD62 H'FFD68 H'FFD6A H'FFD80 H'FFD84 H'FFD86 H'FFD88 H'FFD8A Module DMAC_2 DMAC_2 DMAC_2 DMAC_2 DMAC_2 DMAC_3 DMAC_3 DMAC_3 DMAC_3 DMAC_3 DMAC_3 DMAC_3 DMAC_0 DMAC_1 DMAC_2 DMAC_3 INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC BSC BSC BSC BSC BSC Data Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Rev.1.00 Jun. 07, 2006 Page 1000 of 1102 REJ09B0294-0100 Section 24 List of Registers Access Cycles (Read/Write) 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/2I 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P Register Name Read strobe timing control register CS assertion period control register Idle control register Bus control register1 Bus control register2 Endian control register SRAM mode control register Burst ROM interface control register Address/data multiplexed I/O control register DRAM control register DRAM access control register Synchronous DRAM control register Refresh control register Refresh timer counter Refresh time constant register RAM emulation register Mode control register System control register System clock control register Standby control register Module stop control register A Module stop control register B Module stop control register C Subclock control register Serial extended mode register_2 Serial mode register_4 Bit rate register_4 Serial control register_4 Transmit data register_4 Serial status register_4 Receive data register_4 Smart card mode register_4 Abbreviation RDNCR CSACR IDLCR BCR1 BCR2 ENDIANCR SRAMCR BROMCR MPXCR DRAMCR DRACCR SDCR REFCR RTCNT RTCOR RAMER MDCR SYSCR SCKCR SBYCR MSTPCRA MSTPCRB MSTPCRC SUBCKCR SEMR_2 SMR_4 BRR_4 SCR_4 TDR_4 SSR_4 RDR_4 SCMR_4 Number of Bits 16 16 16 16 8 8 16 16 16 16 16 16 16 8 8 8 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 Address H'FFD8C H'FFD8E H'FFD90 H'FFD92 H'FFD94 H'FFD95 H'FFD98 H'FFD9A H'FFD9C H'FFDA0 H'FFDA2 H'FFDA4 H'FFDA6 H'FFDA8 H'FFDA9 H'FFD9E H'FFDC0 H'FFDC2 H'FFDC4 H'FFDC6 H'FFDC8 H'FFDCA H'FFDCC H'FFDCF H'FFE84 H'FFE90 H'FFE91 H'FFE92 H'FFE93 H'FFE94 H'FFE95 H'FFE96 Module BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SCI_2 SCI_4 SCI_4 SCI_4 SCI_4 SCI_4 SCI_4 SCI_4 Data Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 Rev.1.00 Jun. 07, 2006 Page 1001 of 1102 REJ09B0294-0100 Section 24 List of Registers Access Cycles (Read/Write) 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P Register Name Flash code control/status register Flash program code select register Flash erase code select register Flash key code register Flash transfer destination address register I C bus control register A_0 I2C bus control register B_0 I C bus mode register_0 I2C bus interrupt enable register_0 I C bus status register_0 Slave address register_0 I C bus transmit data register_0 I C bus receive data register_0 I C bus control register A_1 I2C bus control register B_1 I C bus mode register_1 I2C bus interrupt enable register_1 I C bus status register_1 Slave address register_1 I2C bus transmit data register_1 I C bus receive data register_1 Timer control register_2 Timer control register_3 Timer control/status register_2 Timer control/status register_3 Time constant register A_2 Time constant register A_3 Time constant register B_2 Time constant register B_3 Timer counter_2 Timer counter_3 Timer counter control register_2 Timer counter control register_3 2 2 2 2 2 2 2 2 2 Abbreviation FCCS FPCS FECS FKEY FTDAR ICCRA_0 ICCRB_0 ICMR_0 ICIER_0 ICSR_0 SAR_0 ICDRT_0 ICDRR_0 ICCRA_1 ICCRB_1 ICMR_1 ICIER_1 ICSR_1 SAR_1 ICDRT_1 ICDRR_1 TCR_2 TCR_3 TCSR_2 TCSR_3 TCORA_2 TCORA_3 TCORB_2 TCORB_3 TCNT_2 TCNT_3 TCCR_2 TCCR_3 Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address H'FFDE8 H'FFDE9 H'FFDEA H'FFDEC H'FFDEE H'FFEB0 H'FFEB1 H'FFEB2 H'FFEB3 H'FFEB4 H'FFEB5 H'FFEB6 H'FFEB7 H'FFEB8 H'FFEB9 H'FFEBA H'FFEBB H'FFEBC H'FFEBD H'FFEBE H'FFEBF H'FFEC0 H'FFEC1 H'FFEC2 H'FFEC3 H'FFEC4 H'FFEC5 H'FFEC6 H'FFEC7 H'FFEC8 H'FFEC9 H'FFECA H'FFECB Module FLASH FLASH FLASH FLASH FLASH IIC2_0 IIC2_0 IIC2_0 IIC2_0 IIC2_0 IIC2_0 IIC2_0 IIC2_0 IIC2_1 IIC2_1 IIC2_1 IIC2_1 IIC2_1 IIC2_1 IIC2_1 IIC2_1 TMR_2 TMR_3 TMR_2 TMR_3 TMR_2 TMR_3 TMR_2 TMR_3 TMR_2 TMR_3 TMR_2 TMR_3 Data Width 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 16 16 16 16 Rev.1.00 Jun. 07, 2006 Page 1002 of 1102 REJ09B0294-0100 Section 24 List of Registers Access Cycles (Read/Write) 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2P/-- 2P/-- 2P/-- 2P/-- 2P/-- 2P/-- 2P/-- Register Name Timer control register_4 Timer mode register_4 Timer I/O control register_4 Timer interrupt enable register_4 Timer status register_4 Timer counter_4 Timer general register A_4 Timer general register B_4 Timer control register_5 Timer mode register_5 Timer I/O control register_5 Timer interrupt enable register_5 Timer status register_5 Timer counter_5 Timer general register A_5 Timer general register B_5 DTC enable register A DTC enable register B DTC enable register C DTC enable register D DTC enable register E DTC enable register G DTC enable register H DTC control register Interrupt control register CPU priority control register IRQ enable register IRQ status register Port 1 register Port 2 register Port 3 register Port 5 register Port 6 register Port A register Port B register Abbreviation TCR_4 TMDR_4 TIOR_4 TIER_4 TSR_4 TCNT_4 TGRA_4 TGRB_4 TCR_5 TMDR_5 TIOR_5 TIER_5 TSR_5 TCNT_5 TGRA_5 TGRB_5 DTCERA DTCERB DTCERC DTCERD DTCERE DTCERG DTCERH DTCCR INTCR CPUPCR IER ISR PORT1 PORT2 PORT3 PORT5 PORT6 PORTA PORTB Number of Bits 8 8 8 8 8 16 16 16 8 8 8 8 8 16 16 16 16 16 16 16 16 16 16 8 8 8 16 16 8 8 8 8 8 8 8 Address H'FFEE0 H'FFEE1 H'FFEE2 H'FFEE4 H'FFEE5 H'FFEE6 H'FFEE8 H'FFEEA H'FFEF0 H'FFEF1 H'FFEF2 H'FFEF4 H'FFEF5 H'FFEF6 H'FFEF8 H'FFEFA H'FFF20 H'FFF22 H'FFF24 H'FFF26 H'FFF28 H'FFF2C H'FFF2E H'FFF30 H'FFF32 H'FFF33 H'FFF34 H'FFF36 H'FFF40 H'FFF41 H'FFF42 H'FFF44 H'FFF45 H'FFF49 H'FFF4A Module TPU_4 TPU_4 TPU_4 TPU_4 TPU_4 TPU_4 TPU_4 TPU_4 TPU_5 TPU_5 TPU_5 TPU_5 TPU_5 TPU_5 TPU_5 TPU_5 INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC I/O port I/O port I/O port I/O port I/O port I/O port I/O port Data Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 Rev.1.00 Jun. 07, 2006 Page 1003 of 1102 REJ09B0294-0100 Section 24 List of Registers Access Cycles (Read/Write) 2P/-- 2P/-- 2P/-- 2P/-- 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P Register Name Port C register Port D register Port E register Port F register Port 1 data register Port 2 data register Port 3 data register Port 6 data register Port A data register Port B data register Port C data register Port D data register Port E data register Port F data register Serial mode register_2 Bit rate register_2 Serial control register_2 Transmit data register_2 Serial status register_2 Receive data register_2 Smart card mode register_2 D/A data register 0 D/A data register 1 D/A control register 01 PPG output control register PPG output mode register Next data enable register H Next data enable register L Output data register H Output data register L Next data register H* Next data register L* Next data register H* Next data register L* Abbreviation PORTC PORTD PORTE PORTF P1DR P2DR P3DR P6DR PADR PBDR PCDR PDDR PEDR PFDR SMR_2 BRR_2 SCR_2 TDR_2 SSR_2 RDR_2 SCMR_2 DADR0 DADR1 DACR01 PCR PMR NDERH NDERL PODRH PODRL NDRH NDRL NDRH NDRL Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address H'FFF4B H'FFF4C H'FFF4D H'FFF4E H'FFF50 H'FFF51 H'FFF52 H'FFF55 H'FFF59 H'FFF5A H'FFF5B H'FFF5C H'FFF5D H'FFF5E H'FFF60 H'FFF61 H'FFF62 H'FFF63 H'FFF64 H'FFF65 H'FFF66 H'FFF68 H'FFF69 H'FFF6A H'FFF76 H'FFF77 H'FFF78 H'FFF79 H'FFF7A H'FFF7B H'FFF7C H'FFF7D H'FFF7E H'FFF7F Module I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port SCI_2 SCI_2 SCI_2 SCI_2 SCI_2 SCI_2 SCI_2 D/A D/A D/A PPG PPG PPG PPG PPG PPG PPG PPG PPG PPG Data Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Rev.1.00 Jun. 07, 2006 Page 1004 of 1102 REJ09B0294-0100 Section 24 List of Registers Access Cycles (Read/Write) 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/3P 2P/3P 2P/3P 16 16 16 16 16 16 16 16 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P Register Name Serial mode register_0 Bit rate register_0 Serial control register_0 Transmit data register_0 Serial status register_0 Receive data register_0 Smart card mode register_0 Serial mode register_1 Bit rate register_1 Serial control register_1 Transmit data register_1 Serial status register_1 Receive data register_1 Smart card mode register_1 A/D data register A A/D data register B A/D data register C A/D data register D A/D data register E A/D data register F A/D data register G A/D data register H A/D control/status register A/D control register Timer control/status register Timer counter Reset control/status register Timer control register_0 Timer control register_1 Timer control/status register_0 Timer control/status register_1 Time constant register A_0 Time constant register A_1 Time constant register B_0 Time constant register B_1 Abbreviation SMR_0 BRR_0 SCR_0 TDR_0 SSR_0 RDR_0 SCMR_0 SMR_1 BRR_1 SCR_1 TDR_1 SSR_1 RDR_1 SCMR_1 ADDRA ADDRB ADDRC ADDRD ADDRE ADDRF ADDRG ADDRH ADCSR ADCR TCSR TCNT RSTCSR TCR_0 TCR_1 TCSR_0 TCSR_1 TCORA_0 TCORA_1 TCORB_0 TCORB_1 Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 Address H'FFF80 H'FFF81 H'FFF82 H'FFF83 H'FFF84 H'FFF85 H'FFF86 H'FFF88 H'FFF89 H'FFF8A H'FFF8B H'FFF8C H'FFF8D H'FFF8E H'FFF90 H'FFF92 H'FFF94 H'FFF96 H'FFF98 H'FFF9A H'FFF9C H'FFF9E H'FFFA0 H'FFFA1 H'FFFA4 H'FFFA5 H'FFFA7 H'FFFB0 H'FFFB1 H'FFFB2 H'FFFB3 H'FFFB4 H'FFFB5 H'FFFB6 H'FFFB7 Module SCI_0 SCI_0 SCI_0 SCI_0 SCI_0 SCI_0 SCI_0 SCI_1 SCI_1 SCI_1 SCI_1 SCI_1 SCI_1 SCI_1 A/D A/D A/D A/D A/D A/D A/D A/D A/D A/D WDT WDT WDT TMR_0 TMR_1 TMR_0 TMR_1 TMR_0 TMR_1 TMR_0 TMR_1 Data Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 16 16 Rev.1.00 Jun. 07, 2006 Page 1005 of 1102 REJ09B0294-0100 Section 24 List of Registers Access Cycles (Read/Write) 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P Register Name Timer counter_0 Timer counter_1 Timer counter control register_0 Timer counter control register_1 Timer start register Timer synchronous register Timer control register_0 Timer mode register_0 Timer I/O control register H_0 Timer I/O control register L_0 Timer interrupt enable register_0 Timer status register_0 Timer counter_0 Timer general register A_0 Timer general register B_0 Timer general register C_0 Timer general register D_0 Timer control register_1 Timer mode register_1 Timer I/O control register_1 Timer interrupt enable register_1 Timer status register_1 Timer counter_1 Timer general register A_1 Timer general register B_1 Timer control register_2 Timer mode register_2 Timer I/O control register_2 Timer interrupt enable register_2 Timer status register_2 Timer counter_2 Timer general register A_2 Timer general register B_2 Timer control register_3 Timer mode register_3 Abbreviation TCNT_0 TCNT_1 TCCR_0 TCCR_1 TSTR TSYR TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNT_0 TGRA_0 TGRB_0 TGRC_0 TGRD_0 TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNT_1 TGRA_1 TGRB_1 TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2 TGRA_2 TGRB_2 TCR_3 TMDR_3 Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 8 8 8 8 8 16 16 16 8 8 8 8 8 16 16 16 8 8 Address H'FFFB8 H'FFFB9 H'FFFBA H'FFFBB H'FFFBC H'FFFBD H'FFFC0 H'FFFC1 H'FFFC2 H'FFFC3 H'FFFC4 H'FFFC5 H'FFFC6 H'FFFC8 H'FFFCA H'FFFCC H'FFFCE H'FFFD0 H'FFFD1 H'FFFD2 H'FFFD4 H'FFFD5 H'FFFD6 H'FFFD8 H'FFFDA H'FFFE0 H'FFFE1 H'FFFE2 H'FFFE4 H'FFFE5 H'FFFE6 H'FFFE8 H'FFFEA H'FFFF0 H'FFFF1 Module TMR_0 TMR_1 TMR_0 TMR_1 TPU TPU TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_1 TPU_1 TPU_1 TPU_1 TPU_1 TPU_1 TPU_1 TPU_1 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_3 TPU_3 Data Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Rev.1.00 Jun. 07, 2006 Page 1006 of 1102 REJ09B0294-0100 Section 24 List of Registers Access Cycles (Read/Write) 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P Register Name Timer I/O control register H_3 Timer I/O control register L_3 Timer interrupt enable register_3 Timer status register_3 Timer counter_3 Timer general register A_3 Timer general register B_3 Timer general register C_3 Timer general register D_3 Abbreviation TIORH_3 TIORL_3 TIER_3 TSR_3 TCNT_3 TGRA_3 TGRB_3 TGRC_3 TGRD_3 Number of Bits 8 8 8 8 16 16 16 16 16 Address H'FFFF2 H'FFFF3 H'FFFF4 H'FFFF5 H'FFFF6 H'FFFF8 H'FFFFA H'FFFFC H'FFFFE Module TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 Data Width 16 16 16 16 16 16 16 16 16 Note: * When the same output trigger is specified for pulse output groups 2 and 3 by the PCR setting, the NDRH address is H'FFF7C. When different output triggers are specified, the NDRH addresses for pulse output groups 2 and 3 are H'FFF7E and H'FFF7C, respectively. Similarly, When the same output trigger is specified for pulse output groups 0 and 1 by the PCR setting, the NDRL address is H'FFF7D. When different output triggers are specified, the NDRL addresses for pulse output groups 0 and 1 are H'FFF7F and H'FFF7D, respectively. Rev.1.00 Jun. 07, 2006 Page 1007 of 1102 REJ09B0294-0100 Section 24 List of Registers 24.2 Register Bits Register addresses and bit names of the on-chip peripheral modules are described below. Each line covers eight bits, and 16-bit and 32-bit registers are shown as 2 or 4 lines, respectively. Register Abbreviation TCR_4 TCR_5 TCSR_4 TCSR_5 TCORA_4 TCORA_5 TCORB_4 TCORB_5 TCNT_4 TCNT_5 TCCR_4 TCCR_5 CRCCR CRCDIR CRCDOR TCR_6 TCR_7 TCSR_6 TCSR_7 TCORA_6 TCORA_7 TCORB_6 TCORB_7 TCNT_6 TCNT_7 TCCR_6 TCCR_7 IFR0 IFR1 IFR2 IER0 -- -- BRST -- -- BRST -- -- EP1 FULL -- -- EP1 FULL -- -- EP2 TR -- SURSS EP2 TR -- -- TMRIS TMRIS -- -- ICKS1 ICKS1 EP0i TR EP3 TS SETC EP0i TR ICKS0 ICKS0 EP0i TS VBUSF SETI EP0i TS CMIEB CMIEB CMFB CMFB CMIEA CMIEA CMFA CMFA OVIE OVIE OVF OVF CCLR1 CCLR1 ADTE -- CCLR0 CCLR0 OS3 OS3 CKS2 CKS2 OS2 OS2 CKS1 CKS1 OS1 OS1 CKS0 CKS0 OS0 OS0 TMR_6 TMR_7 TMR_6 TMR_7 TMR_6 TMR_7 TMR_6 TMR_7 TMR_6 TMR_7 TMR_6 TMR_7 USB -- -- DORCLR -- -- -- -- -- -- -- -- -- TMRIS TMRIS -- -- -- LMS ICKS1 ICKS1 G1 ICKS0 ICKS0 G0 Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 CMIEB CMIEB CMFB CMFB CMIEA CMIEA CMFA CMFA OVIE OVIE OVF OVF CCLR1 CCLR1 ADTE -- CCLR0 CCLR0 OS3 OS3 CKS2 CKS2 OS2 OS2 CKS1 CKS1 OS1 OS1 Bit 24/16/8/0 CKS0 CKS0 OS0 OS0 Module TMR_4 TMR_5 TMR_4 TMR_5 TMR_4 TMR_5 TMR_4 TMR_5 TMR_4 TMR_5 TMR_4 TMR_5 CRC EP2 EMPTY SETUP TS EP0o TS -- SURSF VBUS MN CFDN EP3 TR -- EP2 EMPTY SETUP TS EP0o TS Rev.1.00 Jun. 07, 2006 Page 1008 of 1102 REJ09B0294-0100 Section 24 List of Registers Register Abbreviation IER1 IER2 ISR0 ISR1 ISR2 EPDR0i EPDR0o EPDR0s EPDR1 EPDR2 EPDR3 EPSZ0o EPSZ1 DASTS FCLR EPSTL TRG DMA CVR CTLR EPIR TRNTREG0 TRNTREG1 PMDDR PMDR PORTM PMICR SMR_5* Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 -- SSRSME BRST -- -- D7 D7 D7 D7 D7 D7 -- -- -- -- -- -- -- CNFV1 -- D7 PTSTE -- -- -- -- -- C/A (GM) BRR_5 SCR_5* TDR_5 SSR_5* TDRE RDRF ORER FER (ERS) PER TEND MPB MPBT TIE RIE TE RE MPIE TEIE CKE1 CKE0 -- -- EP1 FULL -- -- D6 D6 D6 D6 D6 D6 -- -- -- EP3 CLR -- -- -- EP2 TR -- -- D5 D5 D5 D5 D5 D5 -- -- EP3 DE EP1 CLR -- -- SURSE -- CFDN EP3 TR -- EP3 TS SETCE EP0i TR EP3 TS SETCE D1 D1 D1 D1 D1 D1 -- -- -- EP0o CLR EP1STL EP0o RDFN Bit 24/16/8/0 VBUSF SETIE EP0i TS VBUSF SETIE D0 D0 D0 D0 D0 D0 -- -- EP0i DE EP0i CLR EP0STL EP0i PKTE Module USB EP2 EMPTY SETUP TS EP0o TS -- SURSE D4 D4 D4 D4 D4 D4 -- -- EP2 DE EP2 CLR -- -- CFDN D3 D3 D3 D3 D3 D3 -- -- -- -- EP3STL EP3 TR -- D2 D2 D2 D2 D2 D2 -- -- -- -- EP2STL EP0s RDFN PULLUP_E EP3 PKTE EP1 RDFN EP2 PKTE -- -- CNFV0 -- D6 -- -- -- -- -- -- CHR (BLK) -- INTV1 -- D5 -- -- -- -- -- -- PE (PE) -- INTV0 RWUPS D4 -- -- PM4DDR PM4DR PM4 PM4ICR O/E (O/E) -- -- RSME D3 EP2DMAE EP1DMAE ALTV1 ASCE D1 txse0 dpls PM1DDR PM1DR PM1 PM1ICR CKS1 ALTV0 -- D0 txdata dmns PM0DDR PM0DR PM0 PM0ICR CKS0 SCI_5 I/O port ALTV2 RWMD D2 SUSPEND txenl -- PM3DDR PM3DR PM3 PM3ICR STOP (BCP1) xver_data PM2DDR PM2DR PM2 PM2ICR MP (BCP0) Rev.1.00 Jun. 07, 2006 Page 1009 of 1102 REJ09B0294-0100 Section 24 List of Registers Register Abbreviation RDR_5 SCMR_5 SEMR_5 IrCR SMR_6* -- -- IrE C/A (GM) BRR_6 SCR_6* TDR_6 SSR_6* TDRE RDRF ORER FER (ERS) RDR_6 SCMR_6 SEMR_6 TCNT32K TCR32K P1DDR P2DDR P3DDR P6DDR PADDR PBDDR PCDDR PDDDR PEDDR PFDDR P1ICR P2ICR P3ICR P5ICR P6ICR PAICR PBICR PCICR PDICR PEICR -- P17DDR P27DDR P37DDR -- PA7DDR PB7DDR -- PD7DDR PE7DDR PF7DDR P17ICR P27ICR P37ICR P57ICR -- PA7ICR PB7ICR -- PD7ICR PE7ICR -- P16DDR P26DDR P36DDR -- PA6DDR PB6DDR -- PD6DDR PE6DDR PF6DDR P16ICR P26ICR P36ICR P56ICR -- PA6ICR PB6ICR -- PD6ICR PE6ICR TME P15DDR P25DDR P35DDR P65DDR PA5DDR PB5DDR -- PD5DDR PE5DDR PF5IDDR P15ICR P25ICR P35ICR P55ICR P65ICR PA5ICR PB5ICR -- PD5ICR PE5ICR -- P14DDR P24DDR P34DDR P64DDR PA4DDR PB4DDR -- PD4DDR PE4DDR PF4DDR P14ICR P24ICR P34ICR P54ICR P64ICR PA4ICR PB4ICR -- PD4ICR PE4ICR -- P13DDR P23DDR P33DDR P63DDR PA3DDR PB3DDR PC3DDR PD3DDR PE3DDR PF3DDR P13ICR P23ICR P33ICR P53ICR P63ICR PA3ICR PB3ICR PC3ICR PD3ICR PE3ICR OSC32STP Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 Bit 24/16/8/0 Module SCI_5 -- -- IrCKS2 CHR (BLK) -- -- IrCKS1 PE (PE) -- ABCS IrCKS0 O/E (O/E) SDIR ACS3 IrTxINV STOP (BCP1) SINV ACS2 IrRxINV MP (BCP0) -- ACS1 -- CKS1 SMIF ACS0 -- CKS0 SCI_6 TIE RIE TE RE MPIE TEIE CKE1 CKE0 PER TEND MPB MPBT -- -- -- -- -- -- -- ABCS SDIR ACS3 SINV ACS2 -- ACS1 SMIF ACS0 TM32K CKS1 P11DDR P21DDR P31DDR P61DDR PA1DDR PB1DDR -- PD1DDR PE1DDR PF1DDR P11ICR P21ICR P31ICR P51ICR P61ICR PA1ICR PB1ICR -- PD1ICR PE1ICR CKS0 P10DDR P20DDR P320DDR P60DDR PA0DDR PB0DDR -- PD0DDR PE0DDR PF0DDR P10ICR P20ICR P30ICR P50ICR P60ICR PA0ICR PB0ICR -- PD0ICR PE0ICR I/O port P12DDR P22DDR P32DDR P62DDR PA2DDR PB2DDR PC2DDR PD2DDR PE2DDR PF2DDR P12ICR P22ICR P32ICR P52ICR P62ICR PA2ICR PB2ICR PC2ICR PD2ICR PE2ICR Rev.1.00 Jun. 07, 2006 Page 1010 of 1102 REJ09B0294-0100 Section 24 List of Registers Register Abbreviation PFICR PORTH PORTI PHDR PIDR PHDDR PIDDR PHICR PIICR PDPCR PEPCR PFPCR PHPCR PIPCR P2ODR PFODR PFCR0 PFCR1 PFCR2 PFCR4 PFCR6 PFCR7 PFCR9 PFCRB PFCRC SSIER Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 PF7ICR PH7 PI7 PH7DR PI7DR PH7DDR PI7DDR PH7ICR PI7ICR PD7PCR PE7PCR PF7PCR PH7PCR PI7PCR P27ODR PF7ODR CS7E CS7SA -- A23E -- DMAS3A TPUMS5 -- ITS7 SSI15 SSI7 DSAR_0 PF6ICR PH6 PI6 PH6DR PI6DR PH6DDR PI6DDR PH6ICR PI6ICR PD6PCR PE6PCR PF6PCR PH6PCR PI6PCR P26ODR PF6ODR CS6E CS7SB CS2S A22E LHWROE DMAS3B TPUMS4 -- ITS6 -- SSI6 PF5ICR PH5 PI5 PH5DR PI5DR PH5DDR PI5DDR PH5ICR PI5ICR PD5PCR PE5PCR PF5PCR PH5PCR PI5PCR P25ODR PF5ODR CS5E CS6SA BSS A21E -- DMAS2A PF4ICR PH4 PI4 PH4DR PI4DR PH4DDR PI4DDR PH4ICR PI4ICR PD4PCR PE4PCR PF4PCR PH4PCR PI4PCR P24ODR PF4ODR CS4E CS6SB BSE A20E -- DMAS2B PF3ICR PH3 PI3 PH3DR PI3DR PH3DDR PI3DDR PH3ICR PI3ICR PD3PCR PE3PCR PF3PCR PH3PCR PI3PCR P23ODR PF3ODR CS3E CS5SA RDWRS A19E TCLKS DMAS1A PF2ICR PH2 PI2 PH2DR PI2DR PH2DDR PI2DDR PH2ICR PI2ICR PD2PCR PE2PCR PF2PCR PH2PCR PI2PCR P22ODR PF2ODR CS2E CS5SB RDWRE A18E -- DMAS1B PF1ICR PH1 PI1 PH1DR PI1DR PH1DDR PI1DDR PH1ICR PI1ICR PD1PCR PE1PCR PF1PCR PH1PCR PI1PCR P21ODR PF1ODR CS1E CS4SA ASOE A17E -- DMAS0A Bit 24/16/8/0 PF0ICR PH0 PI0 PH0DR PI0DR PH0DDR PI0DDR PH0ICR PI0ICR PD0PCR PE0PCR PF0PCR PH0PCR PI0PCR P20ODR PF0ODR CS0E CS4SB -- A16E -- DMAS0B Module I/O port TPUMS3A TPUMS3B TPUMS2A TPUMS2B TPUMS1A TPUMS1B -- ITS5 -- SSI5 -- ITS4 -- SSI4 ITS11 ITS3 SSI11 SSI3 ITS10 ITS2 SSI10 SSI2 ITS9 ITS1 SSI9 SSI1 ITS8 ITS0 SSI8 SSI0 DMAC_0 INTC DDAR_0 Rev.1.00 Jun. 07, 2006 Page 1011 of 1102 REJ09B0294-0100 Section 24 List of Registers Register Abbreviation DOFR_0 Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 Bit 24/16/8/0 Module DMAC_0 DTCR_0 DBSR_0 BKSZH31 BKSZH23 BKSZ15 BKSZ7 BKSZH30 BKSZH22 BKSZ14 BKSZ6 DACKE -- DTSZ0 DTF0 DIRS -- -- -- BKSZH29 BKSZH21 BKSZ13 BKSZ5 TENDE -- MDS1 DTA -- SAT1 -- -- BKSZH28 BKSZH20 BKSZ12 BKSZ4 -- -- MDS0 -- -- SAT0 SARA4 DARA4 BKSZH27 BKSZH19 BKSZ11 BKSZ3 DREQS ERRF TSEIE -- -- -- SARA3 DARA3 BKSZH26 BKSZH18 BKSZ10 BKSZ2 NRD -- -- DMAP2 RPTIE -- SARA2 DARA2 BKSZH25 BKSZH17 BKSZ9 BKSZ1 -- ESIF ESIE DMAP1 ARS1 DAT1 SARA1 DARA1 BKSZH24 BKSZH16 BKSZ8 BKSZ0 -- DTIF DTIE DMAP0 ARS0 DAT0 SARA0 DARA0 DMAC_1 DMDR_0 DTE ACT DTSZ1 DTF1 DACR_0 AMS -- SARIE DARIE DSAR_1 DDAR_1 DOFR_1 DTCR_1 Rev.1.00 Jun. 07, 2006 Page 1012 of 1102 REJ09B0294-0100 Section 24 List of Registers Register Abbreviation DBSR_1 Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 BKSZH31 BKSZH23 BKSZ15 BKSZ7 DMDR_1 DTE ACT DTSZ1 DTF1 DACR_1 AMS -- SARIE DARIE DSAR_2 BKSZH30 BKSZH22 BKSZ14 BKSZ6 DACKE -- DTSZ0 DTF0 DIRS -- -- -- BKSZH29 BKSZH21 BKSZ13 BKSZ5 TENDE -- MDS1 DTA -- SAT1 -- -- BKSZH28 BKSZH20 BKSZ12 BKSZ4 -- -- MDS0 -- -- SAT0 SARA4 DARA4 BKSZH27 BKSZH19 BKSZ11 BKSZ3 DREQS -- TSEIE -- -- -- SARA3 DARA3 BKSZH26 BKSZH18 BKSZ10 BKSZ2 NRD -- -- DMAP2 RPTIE -- SARA2 DARA2 BKSZH25 BKSZH17 BKSZ9 BKSZ1 -- ESIF ESIE DMAP1 ARS1 DAT1 SARA1 DARA1 Bit 24/16/8/0 Module BKSZH24 DMAC_1 BKSZH16 BKSZ8 BKSZ0 -- DTIF DTIE DMAP0 ARS0 DAT0 SARA0 DARA0 DMAC_2 DDAR_2 DOFR_2 DTCR_2 DBSR_2 BKSZH31 BKSZH23 BKSZ15 BKSZ7 BKSZH30 BKSZH22 BKSZ14 BKSZ6 DACKE -- DTSZ0 DTF0 BKSZH29 BKSZH21 BKSZ13 BKSZ5 TENDE -- MDS1 DTA BKSZH28 BKSZH20 BKSZ12 BKSZ4 -- -- MDS0 -- BKSZH27 BKSZH19 BKSZ11 BKSZ3 DREQS -- TSEIE -- BKSZH26 BKSZH18 BKSZ10 BKSZ2 NRD -- -- DMAP2 BKSZH25 BKSZH17 BKSZ9 BKSZ1 -- ESIF ESIE DMAP1 BKSZH24 BKSZH16 BKSZ8 BKSZ0 -- DTIF DTIE DMAP0 DMDR_2 DTE ACT DTSZ1 DTF1 Rev.1.00 Jun. 07, 2006 Page 1013 of 1102 REJ09B0294-0100 Section 24 List of Registers Register Abbreviation DACR_2 Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 AMS -- SARIE DARIE DSAR_3 DIRS -- -- -- -- SAT1 -- -- -- SAT0 SARA4 DARA4 -- -- SARA3 DARA3 RPTIE -- SARA2 DARA2 ARS1 DAT1 SARA1 DARA1 Bit 24/16/8/0 ARS0 DAT0 SARA0 DARA0 DMAC_3 Module DMAC_2 DDAR_3 DOFR_3 DTCR_3 DBSR_3 BKSZH31 BKSZH23 BKSZ15 BKSZ7 BKSZH30 BKSZH22 BKSZ14 BKSZ6 DACKE -- DTSZ0 DTF0 DIRS -- -- -- BKSZH29 BKSZH21 BKSZ13 BKSZ5 TENDE -- MDS1 DTA -- SAT1 -- -- BKSZH28 BKSZH20 BKSZ12 BKSZ4 -- -- MDS0 -- -- SAT0 SARA4 DARA4 BKSZH27 BKSZH19 BKSZ11 BKSZ3 DREQS -- TSEIE -- -- -- SARA3 DARA3 BKSZH26 BKSZH18 BKSZ10 BKSZ2 NRD -- -- DMAP2 RPTIE -- SARA2 DARA2 BKSZH25 BKSZH17 BKSZ9 BKSZ1 -- ESIF ESIE DMAP1 ARS1 DAT1 SARA1 DARA1 BKSZH24 BKSZH16 BKSZ8 BKSZ0 -- DTIF DTIE DMAP0 ARS0 DAT0 SARA0 DARA0 DMAC_0 DMAC_1 DMAC_2 DMAC_3 DMDR_3 DTE ACT DTSZ1 DTF1 DACR_3 AMS -- SARIE DARIE DMRSR_0 DMRSR_1 DMRSR_2 DMRSR_3 Rev.1.00 Jun. 07, 2006 Page 1014 of 1102 REJ09B0294-0100 Section 24 List of Registers Register Abbreviation IPRA Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 -- -- IPRB -- -- IPRC -- -- IPRD -- -- IPRE -- -- IPRF -- -- IPRG -- -- IPRH -- -- IPRI -- -- IPRK -- -- IPRL -- -- IPRQ -- -- IPRR -- -- ISCRH IRQ15SR IRQ11SR ISCRL IRQ7SR IRQ3SR DTCVBR IPRA14 IPRA6 IPRB14 IPRB6 IPRC14 IPRC6 -- -- -- -- -- IPRF6 IPRG14 IPRG6 IPRH14 IPRH6 IPRI14 IPRI6 IPRK14 IPRK6 IPRL14 IPRL6 -- IPRQ6 IPRR14 IPRR6 IRQ15SF IRQ11SF IRQ7SF IRQ3SF IPRA13 IPRA5 IPRB13 IPRB5 IPRC13 IPRC5 -- -- -- -- -- IPRF5 IPRG13 IPRG5 IPRH13 IPRH5 IPRI13 IPRI5 IPRK13 IPRK5 IPRL13 IPRL5 -- IPRQ5 IPRR13 IPRR5 -- IRQ10SR IRQ6SR IRQ2SR IPRA12 IPRA4 IPRB12 IPRB4 IPRC12 IPRC4 -- -- -- -- -- IPRF4 IPRG12 IPRG4 IPRH12 IPRH4 IPRI12 IPRI4 IPRK12 IPRK4 IPRL12 IPRL4 -- IPRQ4 IPRR12 IPRR4 -- IRQ10SF IRQ6SF IRQ2SF -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- IRQ9SR IRQ5SR IRQ1SR IPRA10 IPRA2 IPRB10 IPRB2 IPRC10 IPRC2 -- IPRD2 IPRE10 -- IPRF10 IPRF2 IPRG10 IPRG2 IPRH10 IPRH2 IPRI10 IPRI2 -- IPRK2 -- -- -- IPRQ2 IPRR10 IPRR2 -- IRQ9SF IRQ5SF IRQ1SF IPRA9 IPRA1 IPRB9 IPRB1 IPRC9 IPRC1 -- IPRD1 IPRE9 -- IPRF9 IPRF1 IPRG9 IPRG1 IPRH9 IPRH1 IPRI9 IPRI1 -- IPRK1 -- -- -- IPRQ1 IPRR9 IPRR1 -- IRQ8SR IRQ4SR IRQ0SR Bit 24/16/8/0 IPRA8 IPRA0 IPRB8 IPRB0 IPRC8 IPRC0 -- IPRD0 IPRE8 -- IPRF8 IPRF0 IPRG8 IPRG0 IPRH8 IPRH0 IPRI8 IPRI0 -- IPRK0 -- -- -- IPRQ0 IPRR8 IPRR0 -- IRQ8SF IRQ4SF IRQ0SF BSC Module INTC ABWCR ABWH7 ABWL7 ABWH6 ABWL6 ABWH5 ABWL5 ABWH4 ABWL4 ABWH3 ABWL3 ABWH2 ABWL2 ABWH1 ABWL1 ABWH0 ABWL0 Rev.1.00 Jun. 07, 2006 Page 1015 of 1102 REJ09B0294-0100 Section 24 List of Registers Register Abbreviation ASTCR Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 AST7 -- WTCRA -- -- WTCRB -- -- RDNCR RDN7 -- CSACR CSXH7 CSXT7 IDLCR IDLS3 IDLSEL7 BCR1 BRLE DKC BCR2 ENDIANCR SRAMCR -- LE7 BCSEL7 -- BROMCR BSRM0 BSRM1 MPXCR MPXE7 -- DRAMCR DRAME BE DRACCR -- -- SDCR MRSE CKSPE REFCR CMF RFSHE RTCNT RTCOR RAMER -- -- -- -- RAMS RAM2 RAM1 RAM0 AST6 -- W72 W52 W32 W12 RDN6 -- CSXH6 CSXT6 IDLS2 IDLSEL6 BREQOE -- -- LE6 BCSEL6 -- BSTS02 BSTS12 MPXE6 -- DTYPE RCDM -- -- -- -- CMIE RLW2 AST5 -- W71 W51 W31 W11 RDN5 -- CSXH5 CSXT5 IDLS1 IDLSEL5 -- -- -- LE5 BCSEL5 -- BSTS01 BSTS11 MPXE5 -- -- DDS TPC1 -- -- -- RCW1 RLW1 AST4 -- W70 W50 W30 W10 RDN4 -- CSXH4 CSXT4 IDLS0 IDLSEL4 -- -- IBCCS LE4 BCSEL4 -- BSTS00 BSTS10 MPXE4 -- -- -- TPC0 -- -- -- RCW0 RLW0 AST3 -- -- -- -- -- RDN3 -- CSXH3 CSXT3 IDLCB1 IDLSEL3 -- -- -- LE3 BCSEL3 -- -- -- MPXE3 -- OEE -- -- -- -- -- -- SLFRF AST2 -- W62 W42 W22 W02 RDN2 -- CSXH2 CSXT2 IDLCB0 IDLSEL2 -- -- -- LE2 BCSEL2 -- -- -- -- -- RAST -- -- -- -- -- RTCK2 TPCS2 AST1 -- W61 W41 W21 W01 RDN1 -- CSXH1 CSXT1 IDLCA1 IDLSEL1 WDBE -- -- -- BCSEL1 -- BSWD01 BSWD11 -- -- -- MXC1 RCD1 -- -- -- RTCK1 TPCS1 Bit 24/16/8/0 AST0 -- W60 W40 W20 W00 RDN0 -- CSXH0 CSXT0 IDLCA0 IDLSEL0 WAITE -- PWDBE -- BCSEL0 -- BSWD00 BSWD10 -- ADDEX CAST MXC0 RCD0 -- -- TRWL RTCK0 TPCS0 Module BSC Rev.1.00 Jun. 07, 2006 Page 1016 of 1102 REJ09B0294-0100 Section 24 List of Registers Register Abbreviation MDCR Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 MDS7 -- SYSCR -- -- SCKCR PSTOP1 -- SBYCR SSBY SLPIE MSTPCRA ACSE MSTPA7 MSTPCRB MSTPB15 MSTPB7 MSTPCRC MSTPC15 MSTPC7 SUBCKCR SEMR_2 SMR_4* BRR_4 SCR_4* TDR_4 SSR_4* RDR_4 SCMR_4 FCCS FPCS FECS FKEY FTDAR ICCRA_0 ICCRB_0 ICMR_0 ICIER_0 ICSR_0 SAR_0 -- -- -- -- K7 TDER ICE BBSY -- TIE TDRE SVA6 -- -- -- -- K6 TDA6 RCVD SCP WAIT TEIE TEND SVA5 -- -- -- -- K5 TDA5 MST SDAO -- RIE RDRF SVA4 -- FLER -- -- K4 TDA4 TRS -- -- NAKIE NACKF SVA3 SDIR -- -- -- K3 TDA3 CKS3 SCLO BCWP STIE STOP SVA2 SINV -- -- -- K2 TDA2 CKS2 -- BC2 ACKE AL SVA1 -- -- -- -- K1 TDA1 CKS1 IICRST BC1 ACKBR AAS SVA0 SMIF SCO PPVS EPVB K0 TDA0 CKS0 -- BC0 ACKBT ADZ -- IIC2_0 FLASH TDRE RDRF ORER FER (ERS) PER TEND MPB MPBT TIE RIE TE RE MPIE TEIE CKE1 CKE0 -- -- C/A (GM) -- -- -- -- PSTOP0 PCK2 OPE -- MSTPA14 MSTPA6 MSTPB14 MSTPB6 MSTPC14 MSTPC6 -- -- CHR (BLK) -- -- MACS -- -- PCK1 -- -- MSTPA13 MSTPA5 MSTPB13 MSTPB5 MSTPC13 MSTPC5 -- -- PE (PE) -- -- -- -- -- PCK0 STS4 -- MSTPA12 MSTPA4 MSTPB12 MSTPB4 MSTPC12 MSTPC4 -- -- O/E (O/E) MDS3 -- MDS2 -- MDS1 -- EXPE DTCMD ICK1 BCK1 STS1 -- MSTPA9 MSTPA1 MSTPB9 MSTPB1 MSTPC9 MSTPC1 WAKE32K ACS1 CKS1 Bit 24/16/8/0 MDS0 -- RAME -- ICK0 BCK0 STS0 -- MSTPA8 MSTPA0 MSTPB8 MSTPB0 MSTPC8 MSTPC0 CS32K ACS0 CKS0 SCI_2 SCI_4 Module SYSTEM FETCHMD -- -- -- -- STS3 -- MSTPA11 MSTPA3 MSTPB11 MSTPB3 MSTPC11 MSTPC3 -- ABCS STOP (BCP1) -- ICK2 BCK2 STS2 -- MSTPA10 MSTPA2 MSTPB10 MSTPB2 MSTPC10 MSTPC2 EXSTP ACS2 MP (BCP0) Rev.1.00 Jun. 07, 2006 Page 1017 of 1102 REJ09B0294-0100 Section 24 List of Registers Register Abbreviation ICDRT_0 ICDRR_0 ICCRA_1 ICCRB_1 ICMR_1 ICIER_1 ICSR_1 SAR_1 ICDRT_1 ICDRR_1 TCR_2 TCR_3 TCSR_2 TCSR_3 TCORA_2 TCORA_3 TCORB_2 TCORB_3 TCNT_2 TCNT_3 TCCR_2 TCCR_3 TCR_4 TMDR_4 TIOR_4 TIER_4 TSR_4 TCNT_4 -- -- -- -- IOB3 TTGE TCFD -- -- CCLR1 -- IOB2 -- -- -- -- CCLR0 -- IOB1 TCIEU TCFU -- -- CKEG1 -- IOB0 TCIEV TCFV TMRIS TMRIS CKEG0 MD3 IOA3 -- -- -- -- TPSC2 MD2 IOA2 -- -- ICKS1 ICKS1 TPSC1 MD1 IOA1 TGIEB TGFB ICKS0 ICKS0 TPSC0 MD0 IOA0 TGIEA TGFA CMIEB CMIEB CMFB CMFB CMIEA CMIEA CMFA CMFA OVIE OVIE OVF OVF CCLR1 CCLR1 ADTE -- CCLR0 CCLR0 OS3 OS3 CKS2 CKS2 OS2 OS2 CKS1 CKS1 OS1 OS1 CKS0 CKS0 OS0 OS0 TMR_2 TMR_3 TMR_2 TMR_3 TMR_2 TMR_3 TMR_2 TMR_3 TMR_2 TMR_3 TMR_2 TMR_3 TPU_4 ICE BBSY -- TIE TDRE SVA6 RCVD SCP WAIT TEIE TEND SVA5 MST SDAO -- RIE RDRF SVA4 TRS -- -- NAKIE NACKF SVA3 CKS3 SCLO BCWP STIE STOP SVA2 CKS2 -- BC2 ACKE AL SVA1 CKS1 IICRST BC1 ACKBR AAS SVA0 CKS0 -- BC0 ACKBT ADZ -- IIC2_1 Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 Bit 24/16/8/0 Module IIC2_0 TGRA_4 TGRB_4 Rev.1.00 Jun. 07, 2006 Page 1018 of 1102 REJ09B0294-0100 Section 24 List of Registers Register Abbreviation TCR_5 TMDR_5 TIOR_5 TIER_5 TSR_5 TCNT_5 Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 -- -- IOB3 TTGE TCFD CCLR1 -- IOB2 -- -- CCLR0 -- IOB1 TCIEU TCFU CKEG1 -- IOB0 TCIEV TCFV CKEG0 MD3 IOA3 -- -- TPSC2 MD2 IOA2 -- -- TPSC1 MD1 IOA1 TGIEB TGFB Bit 24/16/8/0 TPSC0 MD0 IOA0 TGIEA TGFA Module TPU_5 TGRA_5 TGRB_5 DTCERA DTCEA15 DTCEA7 DTCEA14 DTCEA6 -- DTCEB6 DTCEC14 DTCEC6 -- -- -- -- -- DTCEG6 DTCEH14 -- -- -- DTCP2 -- IRQ6E -- IRQ6F DTCEA13 DTCEA5 DTCEB13 DTCEB5 DTCEC13 DTCEC5 DTCED13 DTCED5 DTCEE13 -- -- -- -- -- -- INTM1 DTCP1 -- IRQ5E -- IRQ5F DTCEA12 DTCEA4 DTCEB12 DTCEB4 DTCEC12 DTCEC4 DTCED12 DTCED4 DTCEE12 -- -- -- -- -- RRS INTM0 DTCP0 -- IRQ4E -- IRQ4F DTCEA11 -- DTCEB11 DTCEB3 DTCEC11 DTCEC3 DTCED11 DTCED3 -- -- DTCEG11 -- -- -- RCHNE NMIEG IPSETE IRQ11E IRQ3E IRQ11F IRQ3F DTCEA10 -- DTCEB10 DTCEB2 DTCEC10 DTCEC2 DTCED10 DTCED2 -- -- DTCEG10 -- -- -- -- -- CPUP2 IRQ10E IRQ2E IRQ10F IRQ2F DTCEA9 -- DTCEB9 DTCEB1 DTCEC9 -- -- DTCED1 -- -- -- -- -- -- -- -- CPUP1 IRQ9E IRQ1E IRQ9F IRQ1F DTCEA8 -- DTCEB8 DTCEB0 DTCEC8 -- -- DTCED0 -- -- -- -- -- -- ERR -- CPUP0 IRQ8E IRQ0E IRQ8F IRQ0F INTC DTCERB DTCEB15 DTCEB7 DTCERC DTCEC15 DTCEC7 DTCERD -- -- DTCERE -- -- DTCERG -- DTCEG7 DTCERH DTCEH15 -- DTCCR INTCR CPUPCR IER -- -- CPUPCE IRQ15E IRQ7E ISR IRQ15F IRQ7F Rev.1.00 Jun. 07, 2006 Page 1019 of 1102 REJ09B0294-0100 Section 24 List of Registers Register Abbreviation PORT1 PORT2 PORT3 PORT5 PORT6 PORTA PORTB PORTC PORTD PORTE PORTF P1DR P2DR P3DR P6DR PADR PBDR PCDR PDDR PEDR PFDR SMR_2* BRR_2 SCR_2*1 TDR_2 SSR_2*1 RDR_2 SCMR_2 DADR0 DADR1 DACR01 DAOE1 DAOE0 DAE -- -- -- -- -- -- -- -- -- SDIR SINV -- SMIF D/A TDRE RDRF ORER FER (ERS) PER TEND MPB MPBT TIE RIE TE RE MPIE TEIE CKE1 CKE0 1 Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 P17 P27 P37 P57 -- PA7 PB7 -- PD7 PE7 PF7 P17DR P27DR P37DR -- PA7DR PB7DR -- PD7DR PE7DR PF7DR C/A (GM) P16 P26 P36 P56 -- PA6 PB6 -- PD6 PE6 PF6 P16DR P26DR P36DR -- PA6DR PB6DR -- PD6DR PE6DR PF6DR CHR (BLK) P15 P25 P35 P55 P65 PA5 PB5 -- PD5 PE5 PF5 P15DR P25DR P35DR P65DR PA5DR PB5DR -- PD5DR PE5DR PF5DR PE (PE) P14 P24 P34 P54 P64 PA4 PB4 -- PD4 PE4 PF4 P14DR P24DR P34DR P64DR PA4DR PB4DR -- PD4DR PE4DR PF4DR O/E (O/E) P13 P23 P33 P53 P63 PA3 PB3 PC3 PD3 PE3 PF3 P13DR P23DR P33DR P63DR PA3DR PB3DR PC3DR PD3DR PE3DR PF3DR STOP (BCP1) P12 P22 P32 P52 P62 PA2 PB2 PC2 PD2 PE2 PF2 P12DR P22DR P32DR P62DR PA2DR PB2DR PC2DR PD2DR PE2DR PF2DR MP (BCP0) P11 P21 P31 P51 P61 PA1 PB1 -- PD1 PE1 PF1 P11DR P21DR P31DR P61DR PA1DR PB1DR -- PD1DR PE1DR PF1DR CKS1 Bit 24/16/8/0 P10 P20 P30 P50 P60 PA0 PB0 -- PD0 PE0 PF0 P10DR P20DR P30DR P60DR PA0DR PB0DR -- PD0DR PE0DR PF0DR CKS0 Module I/O port SCI_2 Rev.1.00 Jun. 07, 2006 Page 1020 of 1102 REJ09B0294-0100 Section 24 List of Registers Register Abbreviation PCR PMR NDERH NDERL PODRH PODRL NDRH* NDRL* 2 Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 G3CMS1 G3INV NDER15 NDER7 POD15 POD7 NDR15 NDR7 -- -- G3CMS0 G2INV NDER14 NDER6 POD14 POD6 NDR14 NDR6 -- -- CHR (BLK) G2CMS1 G1INV NDER13 NDER5 POD13 POD5 NDR13 NDR5 -- -- PE (PE) G2CMS0 G0INV NDER12 NDER4 POD12 POD4 NDR12 NDR4 -- -- O/E (O/E) G1CMS1 G3NOV NDER11 NDER3 POD11 POD3 NDR11 NDR3 NDR11 NDR3 STOP (BCP1) G1CMS0 G2NOV NDER10 NDER2 POD10 POD2 NDR10 NDR2 NDR10 NDR2 MP (BCP0) G0CMS1 G1NOV NDER9 NDER1 POD9 POD1 NDR9 NDR1 NDR9 NDR1 CKS1 Bit 24/16/8/0 G0CMS0 G0NOV NDER8 NDER0 POD8 POD0 NDR8 NDR0 NDR8 NDR0 CKS0 Module PPG 2 NDRH* NDRL* 2 2 SMR_0* BRR_0 1 C/A (GM) SCI_0 SCR_0*1 TDR_0 SSR_0*1 RDR_0 SCMR_0 SMR_1*1 BRR_1 SCR_1*1 TDR_1 SSR_1*1 RDR_1 SCMR_1 ADDRA TIE RIE TE RE MPIE TEIE CKE1 CKE0 TDRE RDRF ORER FER (ERS) PER TEND MPB MPBT -- C/A (GM) -- CHR (BLK) -- PE (PE) -- O/E (O/E) SDIR STOP (BCP1) SINV MP (BCP0) -- CKS1 SMIF CKS0 SCI_1 TIE RIE TE RE MPIE TEIE CKE1 CKE0 TDRE RDRF ORER FER (ERS) PER TEND MPB MPBT -- -- -- -- SDIR SINV -- SMIF A/D ADDRB ADDRC ADDRD Rev.1.00 Jun. 07, 2006 Page 1021 of 1102 REJ09B0294-0100 Section 24 List of Registers Register Abbreviation ADDRE Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 Bit 24/16/8/0 Module A/D ADDRF ADDRG ADDRH ADCSR ADCR TCSR TCNT RSTCSR TCR_0 TCR_1 TCSR_0 TCSR_1 TCORA_0 TCORA_1 TCORB_0 TCORB_1 TCNT_0 TCNT_1 TCCR_0 TCCR_1 TSTR TSYR TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNT_0 ADF TRGS1 OVF ADIE TRGS0 WT/IT ADST SCANE TME -- SCANS -- CH3 CKS1 -- CH2 CKS0 CKS2 CH1 -- CKS1 CH0 -- CKS0 WDT WOVF CMIEB CMIEB CMFB CMFB RSTE CMIEA CMIEA CMFA CMFA -- OVIE OVIE OVF OVF -- CCLR1 CCLR1 ADTE -- -- CCLR0 CCLR0 OS3 OS3 -- CKS2 CKS2 OS2 OS2 -- CKS1 CKS1 OS1 OS1 -- CKS0 CKS0 OS0 OS0 TMR_0 TMR_1 TMR_0 TMR_1 TMR_0 TMR_1 TMR_0 TMR_1 TMR_0 TMR_1 -- -- -- -- CCLR2 -- IOB3 IOD3 TTGE -- -- -- -- -- CCLR1 -- IOB2 IOD2 -- -- -- -- CST5 SYNC5 CCLR0 BFB IOB1 IOD1 -- -- -- -- CST4 SYNC4 CKEG1 BFA IOB0 IOD0 TCIEV TCFV TMRIS TMRIS CST3 SYNC3 CKEG0 MD3 IOA3 IOC3 TGIED TGFD -- -- CST2 SYNC2 TPSC2 MD2 IOA2 IOC2 TGIEC TGFC ICKS1 ICKS1 CST1 SYNC1 TPSC1 MD1 IOA1 IOC1 TGIEB TGFB ICKS0 ICKS0 CST0 SYNC0 TPSC0 MD0 IOA0 IOC0 TGIEA TGFA TMR_0 TMR_1 TPU TPU_0 Rev.1.00 Jun. 07, 2006 Page 1022 of 1102 REJ09B0294-0100 Section 24 List of Registers Register Abbreviation TGRA_0 Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 Bit 24/16/8/0 Module TPU_0 TGRB_0 TGRC_0 TGRD_0 TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNT_1 -- -- IOB3 TTGE TCFD CCLR1 -- IOB2 -- -- CCLR0 -- IOB1 TCIEU TCFU CKEG1 -- IOB0 TCIEV TCFV CKEG0 MD3 IOA3 -- TGFD TPSC2 MD2 IOA2 -- -- TPSC1 MD1 IOA1 TGIEB TGFB TPSC0 MD0 IOA0 TGIEA TGFA TPU_1 TGRA_1 TGRB_1 TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2 -- -- IOB3 TTGE TCFD CCLR1 -- IOB2 -- -- CCLR0 -- IOB1 TCIEU TCFU CKEG1 -- IOB0 TCIEV TCFV CKEG0 MD3 IOA3 -- -- TPSC2 MD2 IOA2 -- -- TPSC1 MD1 IOA1 TGIEB TGFB TPSC0 MD0 IOA0 TGIEA TGFA TPU_2 TGRA_2 TGRB_2 TCR_3 TMDR_3 TIORH_3 TIORL_3 TIER_3 TSR_3 CCLR2 -- IOB3 IOD3 TTGE -- CCLR1 -- IOB2 IOD2 -- -- CCLR0 BFB IOB1 IOD1 -- -- CKEG1 BFA IOB0 IOD0 TCIEV TCFV CKEG0 MD3 IOA3 IOC3 TGIED TGFD TPSC2 MD2 IOA2 IOC2 TGIEC TGFC TPSC1 MD1 IOA1 IOC1 TGIEB TGFB TPSC0 MD0 IOA0 IOC0 TGIEA TGFA TPU_3 Rev.1.00 Jun. 07, 2006 Page 1023 of 1102 REJ09B0294-0100 Section 24 List of Registers Register Abbreviation TCNT_3 Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 Bit 24/16/8/0 Module TPU_3 TGRA_3 TGRB_3 TGRC_3 TGRD_3 Notes: 1. Parts of the bit functions differ in normal mode and the smart card interface. 2. When the same output trigger is specified for pulse output groups 2 and 3 by the PCR setting, the NDRH address is H'FFF7C. When different output triggers are specified, the NDRH addresses for pulse output groups 2 and 3 are H'FFF7E and H'FFF7C, respectively. Similarly, When the same output trigger is specified for pulse output groups 0 and 1 by the PCR setting, the NDRL address is H'FFF7D. When different output triggers are specified, the NDRL addresses for pulse output groups 0 and 1 are H'FFF7F and H'FFF7D, respectively. Rev.1.00 Jun. 07, 2006 Page 1024 of 1102 REJ09B0294-0100 Section 24 List of Registers 24.3 Register Register States in Each Operating Mode Module Stop State -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- All-ModuleClock-Stop -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Software Standby -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized TMR_6 TMR_7 TMR_6 TMR_7 TMR_6 TMR_7 TMR_6 TMR_7 TMR_6 TMR_7 TMR_6 TMR_7 Module TMR_4 TMR_5 TMR_4 TMR_5 TMR_4 TMR_5 TMR_4 TMR_5 TMR_4 TMR_5 TMR_4 TMR_5 CRC Abbreviation Reset TCR_4 TCR_5 TCSR_4 TCSR_5 TCORA_4 TCORA_5 TCORB_4 TCORB_5 TCNT_4 TCNT_5 TCCR_4 TCCR_5 CRCCR CRCDIR CRCDOR TCR_6 TCR_7 TCSR_6 TCSR_7 TCORA_6 TCORA_7 TCORB_6 TCORB_7 TCNT_6 TCNT_7 TCCR_6 TCCR_7 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Rev.1.00 Jun. 07, 2006 Page 1025 of 1102 REJ09B0294-0100 Section 24 List of Registers Register Abbreviation Reset IFR0 IFR1 IFR2 IER0 IER1 IER2 ISR0 ISR1 ISR2 EPDR0i EPDR0o EPDR0s EPDR1 EPDR2 EPDR3 EPSZ0o EPSZ1 DASTS FCLR EPSTL TRG DMA CVR CTLR EPIR TRNTREG0 TRNTREG1 PMDDR PMDR PORTM PMICR Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized -- Initialized Module Stop State -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- All-ModuleClock-Stop -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Software Standby -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized -- Initialized I/O port Module USB Rev.1.00 Jun. 07, 2006 Page 1026 of 1102 REJ09B0294-0100 Section 24 List of Registers Register Abbreviation Reset SMR_5 BRR_5 SCR_5 TDR_5 SSR_5 RDR_5 SCMR_5 SEMR_5 IrCR SMR_6 BRR_6 SCR_6 TDR_6 SSR_6 RDR_6 SCMR_6 SEMR_6 TCNT32K TCR32K P1DDR P2DDR P3DDR P6DDR PADDR PBDDR PCDDR PDDDR PEDDR PFDDR Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module Stop State -- -- -- Initialized Initialized Initialized -- -- -- -- -- -- Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- All-ModuleClock-Stop -- -- -- Initialized Initialized Initialized -- -- -- -- -- -- Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- Software Standby -- -- -- Initialized Initialized Initialized -- -- -- -- -- -- Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized I/O port TM32K SCI_6 Module SCI_5 Rev.1.00 Jun. 07, 2006 Page 1027 of 1102 REJ09B0294-0100 Section 24 List of Registers Register Abbreviation Reset P1ICR P2ICR P3ICR P5ICR P6ICR PAICR PBICR PCICR PDICR PEICR PFICR PORTH PORTI PHDR PIDR PHDDR PIDDR PHICR PIICR PDPCR PEPCR PFPCR PHPCR PIPCR P2ODR PFODR PFCR0 PFCR1 PFCR2 PFCR4 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized -- -- Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module Stop State -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- All-ModuleClock-Stop -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Software Standby -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized -- -- Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module I/O port Rev.1.00 Jun. 07, 2006 Page 1028 of 1102 REJ09B0294-0100 Section 24 List of Registers Register Abbreviation Reset PFCR6 PFCR7 PFCR9 PFCRB PFCRC SSIER DSAR_0 DDAR_0 DOFR_0 DTCR_0 DBSR_0 DMDR_0 DACR_0 DSAR_1 DDAR_1 DOFR_1 DTCR_1 DBSR_1 DMDR_1 DACR_1 DSAR_2 DDAR_2 DOFR_2 DTCR_2 DBSR_2 DMDR_2 DACR_2 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module Stop State -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- All-ModuleClock-Stop -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Software Standby -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized DMAC_2 DMAC_1 INTC DMAC_0 Module I/O port Rev.1.00 Jun. 07, 2006 Page 1029 of 1102 REJ09B0294-0100 Section 24 List of Registers Register Abbreviation Reset DSAR_3 DDAR_3 DOFR_3 DTCR_3 DBSR_3 DMDR_3 DACR_3 DMRSR_0 DMRSR_1 DMRSR_2 DMRSR_3 IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRK IPRL IPRQ IPRR ISCRH ISCRL DTCVBR ABWCR ASTCR Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module Stop State -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- All-ModuleClock-Stop -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Software Standby -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized DMAC_0 DMAC_1 DMAC_2 DMAC_3 INTC Module DMAC_3 Rev.1.00 Jun. 07, 2006 Page 1030 of 1102 REJ09B0294-0100 Section 24 List of Registers Register Abbreviation Reset WTCRA WTCRB RDNCR CSACR IDLCR BCR1 BCR2 ENDIANCR SRAMCR BROMCR MPXCR DRAMCR DRACCR SDCR REFCR RTCNT RTCOR RAMER MDCR SYSCR SCKCR SBYCR MSTPCRA MSTPCRB MSTPCRC SUBCKCR SEMR_2 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module Stop State -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- All-ModuleClock-Stop -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Software Standby -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized SCI_2 SYSTEM Module BSC Rev.1.00 Jun. 07, 2006 Page 1031 of 1102 REJ09B0294-0100 Section 24 List of Registers Register Abbreviation Reset SMR_4 BRR_4 SCR_4 TDR_4 SSR_4 RDR_4 SCMR_4 FCCS FPCS FECS FKEY FTDAR ICCRA_0 ICCRB_0 ICMR_0 ICIER_0 ICSR_0 SAR_0 ICDRT_0 ICDRR_0 ICCRA_1 ICCRB_1 ICMR_1 ICIER_1 ICSR_1 SAR_1 ICDRT_1 ICDRR_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module Stop State -- -- -- Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- All-ModuleClock-Stop -- -- -- Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Software Standby -- -- -- Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized IIC2_1 IIC2_0 FLASH Module SCI_4 Rev.1.00 Jun. 07, 2006 Page 1032 of 1102 REJ09B0294-0100 Section 24 List of Registers Register Abbreviation Reset TCR_2 TCR_3 TCSR_2 TCSR_3 TCORA_2 TCORA_3 TCORB_2 TCORB_3 TCNT_2 TCNT_3 TCCR_2 TCCR_3 TCR_4 TMDR_4 TIOR_4 TIER_4 TSR_4 TCNT_4 TGRA_4 TGRB_4 TCR_5 TMDR_5 TIOR_5 TIER_5 TSR_5 TCNT_5 TGRA_5 TGRB_5 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module Stop State -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- All-ModuleClock-Stop -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Software Standby -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized TPU_5 Module TMR_2 TMR_3 TMR_2 TMR_3 TMR_2 TMR_3 TMR_2 TMR_3 TMR_2 TMR_3 TMR_2 TMR_3 TPU_4 Rev.1.00 Jun. 07, 2006 Page 1033 of 1102 REJ09B0294-0100 Section 24 List of Registers Register Abbreviation Reset DTCERA DTCERB DTCERC DTCERD DTCERE DTCERG DTCERH DTCCR INTCR CPUPCR IER ISR PORT1 PORT2 PORT3 PORT5 PORT6 PORTA PORTB PORTC PORTD PORTE PORTF P1DR P2DR P3DR P6DR PADR PBDR PCDR Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module Stop State -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- All-ModuleClock-Stop -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Software Standby -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized Initialized Initialized Initialized Initialized I/O port Module INTC Rev.1.00 Jun. 07, 2006 Page 1034 of 1102 REJ09B0294-0100 Section 24 List of Registers Register Abbreviation Reset PDDR PEDR PFDR SMR_2 BRR_2 SCR_2 TDR_2 SSR_2 RDR_2 SCMR_2 DADR0 DADR1 DACR01 PCR PMR NDERH NDERL PODRH PODRL NDRH NDRL SMR_0 BRR_0 SCR_0 TDR_0 SSR_0 RDR_0 SCMR_0 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module Stop State -- -- -- -- -- -- Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized -- Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- All-ModuleClock-Stop -- -- -- -- -- -- Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized -- Software Standby -- -- -- -- -- -- Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized -- Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized SCI_0 PPG D/A SCI_2 Module I/O port Rev.1.00 Jun. 07, 2006 Page 1035 of 1102 REJ09B0294-0100 Section 24 List of Registers Register Abbreviation Reset SMR_1 BRR_1 SCR_1 TDR_1 SSR_1 RDR_1 SCMR_1 ADDRA ADDRB ADDRC ADDRD ADDRE ADDRF ADDRG ADDRH ADCSR ADCR TCSR TCNT RSTCSR TCR_0 TCR_1 TCSR_0 TCSR_1 TCORA_0 TCORA_1 TCORB_0 TCORB_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module Stop State -- -- -- Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- All-ModuleClock-Stop -- -- -- Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Software Standby -- -- -- Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized TMR_0 TMR_1 TMR_0 TMR_1 TMR_0 TMR_1 TMR_0 TMR_1 WDT A/D Module SCI_1 Rev.1.00 Jun. 07, 2006 Page 1036 of 1102 REJ09B0294-0100 Section 24 List of Registers Register Abbreviation Reset TCNT_0 TCNT_1 TCCR_0 TCCR_1 TSTR TSYR TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNT_0 TGRA_0 TGRB_0 TGRC_0 TGRD_0 TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNT_1 TGRA_1 TGRB_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module Stop State -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- All-ModuleClock-Stop -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Software Standby -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized TPU_1 TPU_0 Module TMR_0 TMR_1 TMR_0 TMR_1 TPU Rev.1.00 Jun. 07, 2006 Page 1037 of 1102 REJ09B0294-0100 Section 24 List of Registers Register Abbreviation Reset TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2 TGRA_2 TGRB_2 TCR_3 TMDR_3 TIORH_3 TIORL_3 TIER_3 TSR_3 TCNT_3 TGRA_3 TGRB_3 TGRC_3 TGRD_3 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module Stop State -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- All-ModuleClock-Stop -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Software Standby -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized TPU_3 Module TPU_2 Rev.1.00 Jun. 07, 2006 Page 1038 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics Section 25 Electrical Characteristics 25.1 Absolute Maximum Ratings Table 25.1 Absolute Maximum Ratings Item Power supply voltage Input voltage (except for port 5) Input voltage (port 5) Reference power supply voltage Analog power supply voltage Analog input voltage Operating temperature Symbol VCC PLLVCC Vin Vin Vref AVCC VAN Topr -0.3 to VCC +0.3 -0.3 to AVCC +0.3 -0.3 to AVCC +0.3 -0.3 to +4.6 -0.3 to AVCC +0.3 Regular specifications: -20 to +75* Wide-range specifications: -40 to +85* Storage temperature Tstg -55 to +125 C Caution: Permanent damage to the LSI may result if absolute maximum ratings are exceeded. Note: * The operating temperature range during programming/erasing of the flash memory is 0C to +75C for regular specifications and 0C to +85C for wide-range specifications. V V V V V C Value -0.3 to +4.6 Unit V Rev.1.00 Jun. 07, 2006 Page 1039 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics 25.2 DC Characteristics Table 25.2 DC Characteristics (1) Conditions: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, 1 VSS = PLLVSS = DrVSS = AVSS = 0 V* , Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Schmitt IRQ input pin, trigger input TPU input pin, voltage TMR input pin, port 2, port 3 2 Port 5* Symbol VT + VT VT - VT VT - + + - - Min. VCC x 0.2 VCC x 0.06 AVCC x 0.2 Typ. Max. VCC x 0.7 AVCC x 0.7 VCC + 0.3 VCC + 0.3 Test Unit Conditions V V V V V V V VT + - VT - VT AVCC x 0.06 Input high voltage (except Schmitt trigger input pin) Input low voltage (except Schmitt trigger input pin) MD, RES, STBY, VIH EMLE, NMI EXTAL Other input pins Port 5 MD, RES, STBY, VIL EMLE EXTAL, NMI Other input pins VOH VOL |Iin| VCC x 0.9 VCC x 0.7 AVCC x 0.7 -0.3 -0.3 -0.3 VCC - 0.5 VCC - 1.0 AVCC + 0.3 VCC x 0.1 V VCC x 0.2 VCC x 0.2 0.4 1.0 10.0 1.0 1.0 V V A IOH = -200 A IOH = -1 mA IOL = 1.6 mA IOL = 10 mA Vin = 0.5 to VCC - 0.5 V Vin = 0.5 to AVCC - 0.5 V Output high All output pins voltage Output low voltage Input leakage current All output pins Port 3 RES MD, STBY, EMLE, NMI Port 5 Rev.1.00 Jun. 07, 2006 Page 1040 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics Table 25.2 DC Characteristics (2) Conditions: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, 1 VSS = PLLVSS = DrVSS = AVSS = 0 V* , Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Three-state Ports 1, 2, 3, 6, leakage current A to F, H, I, M (off state) Input pull-up MOS current Input capacitance Current 3 consumption* Symbol Min. | ITSI | Typ. Max. 1.0 Test Unit Conditions A Vin = 0.5 to VCC - 0.5 V VCC = 3.0 to 3.6 V Vin = 0 V All input pins Cin 15 pF Vin = 0 V f = 1 MHz Ta = 25C f = 50 MHz Ports D to F, H, I -Ip 10 300 A Normal operation ICC* Sleep mode Subclock operation 5 75 70 5.0 125 90 10 mA 32.768-kHz crystal resonator is used. A Ta 50C 50C < Ta mA mA A mA A V Standby mode* 4 AICC AICC VRAM 2.5 50 33 1.0 (3.0 V) 1.0 1.5 (3.0 V) 1.5 100 300 45 2.0 20 3.0 5.0 All-module-clock6 stop mode* Analog power supply current During A/D and D/A conversion Standby for A/D and D/A conversion Reference power supply current During A/D and D/A conversion Standby for A/D and D/A conversion RAM standby voltage Rev.1.00 Jun. 07, 2006 Page 1041 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics Item Vcc start voltage* 7 7 Symbol Min. VCCSTART SVCC Typ. Max. 0.8 20 Test Unit Conditions V ms/V Vcc rising gradient* Notes: 1. When the A/D and D/A converters are not used, the AVCC, Vref, and AVSS pins should not be open. Connect the AVCC and Vref pins to VCC, and the AVSS pin to VSS. 2. The case where port 5 is used as IRQ0 to IRQ7. 3. Current consumption values are for VIHmin = VCC - 0.5 V and VILmax = 0.5 V with all output pins unloaded and all input pull-up MOSs in the off state. 4. The values are for VRAM VCC < 3.0 V, VIHmin = VCC x 0.9, and VILmax = 0.3 V. 5. ICC depends on f as follows: ICCmax = 35 (mA) + 1.8 (mA/MHz) x f (normal operation) ICCmax = 30 (mA) + 1.2 (mA/MHz) x f (sleep mode) 6. The values are for reference. 7. This can be applied when the RES pin is held low at power-on. Table 25.3 Permissible Output Currents Conditions: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V*, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Permissible output low current (per pin) Permissible output low current (per pin) Permissible output low current (total) Permissible output high current (per pin) Permissible output high current (total) Caution: Note: * Output pins except port 3 Port 3 Total of all output pins All output pins Total of all output pins Symbol IOL IOL IOL -IOH -IOH Min. Typ. Max. 2.0 10 80 2.0 40 Unit mA mA mA mA mA To protect the LSI's reliability, do not exceed the output current values in table 25.3. When the A/D and D/A converters are not used, the AVCC, Vref, and AVSS pins should not be open. Connect the AVCC and Vref pins to VCC, and the AVSS pin to VSS. Rev.1.00 Jun. 07, 2006 Page 1042 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics 25.3 AC Characteristics 3V RL LSI output pin C = 30 pF RL = 2.4 k RH = 12 k Input/output timing measurement level: 1.5 V (Vcc = 3.0 V to 3.6 V) C RH Figure 25.1 Output Load Circuit 25.3.1 Clock Timing Table 25.4 Clock Timing Conditions: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, I = 8 MHz to 50 MHz, B = 8 MHz to 50 MHz, P = 8 MHz to 35 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Clock cycle time Clock high pulse width Clock low pulse width Clock rising time Clock falling time Oscillation settling time after reset (crystal) Oscillation settling time after leaving software standby mode (crystal) Symbol tcyc tCH tCL tCr tCf tOSC1 tOSC2 Min. 20 5 5 10 10 Max. 125 5 5 Unit. ns ns ns ns ns ms ms Figure 25.4 Figure 25.3 Test Conditions Figure 25.2 Rev.1.00 Jun. 07, 2006 Page 1043 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics Item Symbol Min. 1 27.7 27.7 2 32.768 30.5 Max. 5 5 32.768 30.5 Unit. ms ns ns ns ns s kHz s Test Conditions Figure 25.4 Figure 25.5 External clock output delay settling tDEXT time External clock input low pulse width tEXL tEXr tEXf tOSC3 fSUB tSUB External clock input high pulse width tEXH External clock rising time External clock falling time Subclock oscillation settling time Subclock oscillator oscillation frequency Subclock cycle time tcyc tCH B tCf tCL tCr Figure 25.2 External Bus Clock Timing Oscillator I NMI NMIEG SSBY NMI exception handling NMI exception handling NMIEG = 1 SSBY = 1 Software standby mode (power-down mode) Oscillation settling time tOSC2 SLEEP instruction Figure 25.3 Oscillation Settling Timing after Software Standby Mode Rev.1.00 Jun. 07, 2006 Page 1044 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics EXTAL tDEXT VCC tDEXT STBY tOSC1 RES tOSC1 I Figure 25.4 Oscillation Settling Timing tEXH tEXL EXTAL Vcc x 0.5 tEXr tEXf Figure 25.5 External Input Clock Timing Rev.1.00 Jun. 07, 2006 Page 1045 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics 25.3.2 Control Signal Timing Table 25.5 Control Signal Timing Conditions: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, I = 8 MHz to 50 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item RES setup time RES pulse width NMI setup time NMI hold time NMI pulse width (after leaving software standby mode) IRQ setup time IRQ hold time IRQ pulse width (after leaving software standby mode) Symbol tRESS tRESW tNMIS tNMIH tNMIW tIRQS tIRQH tIRQW Min. 200 20 150 10 200 150 10 200 Max. Unit ns tcyc ns ns ns ns ns ns Figure 25.7 Test Conditions Figure 25.6 I tRESS RES tRESW tRESS Figure 25.6 Reset Input Timing Rev.1.00 Jun. 07, 2006 Page 1046 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics I tNMIS tNMIH NMI tNMIW IRQi* (i = 0 to 11) tIRQW tIRQS tIRQH IRQ* (edge input) tIRQS IRQ* (level input) Note: * SSIER must be set to cancel software standby mode. Figure 25.7 Interrupt Input Timing 25.3.3 Bus Timing Table 25.6 Bus Timing (1) Conditions: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, B = 8 MHz to 50 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Address delay time Address setup time 1 Address setup time 2 Address setup time 3 Address setup time 4 Address hold time 1 Address hold time 2 Address hold time 3 Symbol tAD tAS1 tAS2 tAS3 tAS4 tAH1 tAH2 tAH3 Min. 0.5 x tcyc - 8 1.0 x tcyc - 8 1.5 x tcyc - 8 2.0 x tcyc - 8 0.5 x tcyc - 8 1.0 x tcyc - 8 1.5 x tcyc - 8 Max. 18 Unit ns ns ns ns ns ns ns ns Test Conditions Figures 25.8 to 25.34 Rev.1.00 Jun. 07, 2006 Page 1047 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics Item CS delay time 1 AS delay time RD delay time 1 RD delay time 2 Read data setup time 1 Read data setup time 2 Read data hold time 1 Read data hold time 2 Read data access time 2 Read data access time 4 Read data access time 5 Read data access time 6 Read data access time (from address) 1 Read data access time (from address) 2 Read data access time (from address) 3 Read data access time (from address) 4 Read data access time (from address) 5 Symbol tCSD1 tASD tRSD1 tRSD2 tRDS1 tRDS2 tRDH1 tRDH2 tAC2 tAC4 tAC5 tAC6 tAA1 tAA2 tAA3 tAA4 tAA5 Min. 1.0 15 15 1.0 0 Max. 15 15 15 15 Unit ns ns ns ns ns ns ns ns Test Conditions Figures 25.8 to 25.34 1.5 x tcyc - 30 ns 2.5 x tcyc - 30 ns 1.0 x tcyc - 30 ns 2.0 x tcyc - 30 ns 1.0 x tcyc - 30 ns 1.5 x tcyc - 30 ns 2.0 x tcyc - 30 ns 2.5 x tcyc - 30 ns 3.0 x tcyc - 30 ns Rev.1.00 Jun. 07, 2006 Page 1048 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics Table 25.6 Bus Timing (2) Conditions: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, B = 8 MHz to 50 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item WR delay time 1 WR delay time 2 WR pulse width 1 WR pulse width 2 Write data delay time Write data setup time 1 Write data setup time 2 Write data setup time 3 Write data hold time 1 Write data hold time 3 Byte control delay time Byte control pulse width 1 Byte control pulse width 2 Multiplexed address delay time 1 Multiplexed address hold time Multiplexed address setup time 1 Multiplexed address setup time 2 Symbol tWRD1 tWRD2 tWSW1 tWSW2 tWDD tWDS1 tWDS2 tWDS3 tWDH1 tWDH3 tUBD tUBW1 tUBW2 tMAD1 tMAH tMAS1 tMAS2 tAHD tAHW1 tAHW2 tWTS tWTH tBREQS tBACD tBZD tBRQOD tBSD tRWD Min. Max. 15 15 Unit ns ns ns ns ns ns ns ns ns ns ns Test Conditions Figures 25.8 to 25.34 1.0 x tcyc - 13 1.5 x tcyc - 13 20 0.5 x tcyc - 13 1.0 x tcyc - 13 1.5 x tcyc - 13 0.5 x tcyc - 8 1.5 x tcyc - 8 15 1.0 x tcyc - 15 ns 2.0 x tcyc - 15 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figures 25.13, 25.14 Figure 25.13 Figure 25.14 Figures 25.17, 25.18 18 1.0 x tcyc - 15 0.5 x tcyc - 15 1.5 x tcyc - 15 15 1.0 x tcyc - 15 2.0 x tcyc - 15 15 5.0 20 1.0 15 30 15 15 15 Address hold delay time Address hold pulse width 1 Address hold pulse width 2 WAIT setup time WAIT hold time BREQ setup time BACK delay time Bus floating time BREQO delay time BS delay time RD/WR delay time Figures 25.10, 25.18 Figure 25.33 Figure 25.34 Figures 25.8, 25.9, 25.11 to 25.14 Rev.1.00 Jun. 07, 2006 Page 1049 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics Table 25.6 Bus Timing (3) Conditions: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, B = 8 MHz to 50 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item CS delay time 2 CS delay time 3 Read data access time 1 Read data access time 3 Read data access time 7 Read data access time 8 Write data hold time 2 Read command setup time 1 Read command setup time 2 Read command hold time Write command setup time 1 Write command setup time 2 Write command hold time 1 Write command hold time 2 CAS delay time 1 CAS delay time 2 CAS setup time 1 CAS setup time 2 CAS pulse width 1 CAS pulse width 2 CAS precharge time 1 CAS precharge time 2 OE delay time 1 OE delay time 2 Precharge time 1 Precharge time 2 Symbol tCSD3 tCSD4 tAC1 tAC3 tAC7 tAC8 tWDH2 tRCS1 tRCS2 tRCH tWCS1 tWCS2 tWCH1 tWCH2 tCASD1 tCASD2 tCSR1 tCSR2 tCASW1 tCASW2 tCPW1 tCPW2 tOED1 tOED2 tPCH1 tPCH2 Min. 1.0 x tcyc - 8 Max. 15 15 Unit ns ns Test Conditions Figures 25.19 to 25.28 1.0 x tcyc - 20 ns 2.0 x tcyc - 20 ns 4.0 x tcyc - 20 ns 3.0 x tcyc - 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1.5 x tcyc - 10 2.0 x tcyc - 10 0.5 x tcyc - 10 0.5 x tcyc - 10 1.0 x tcyc - 10 0.5 x tcyc - 10 1.0 x tcyc - 10 15 15 0.5 x tcyc - 10 1.5 x tcyc - 10 1.0 x tcyc - 15 1.5 x tcyc - 15 1.0 x tcyc - 15 1.5 x tcyc - 15 15 15 1.0 x tcyc - 20 1.5 x tcyc - 20 Rev.1.00 Jun. 07, 2006 Page 1050 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics Item Precharge time 1 for self-refresh Precharge time 2 for self refresh Symbol tRPS1 tRPS2 tAD2 tCSD4 tDQMD tCKED Min. Max. Unit ns ns ns ns ns ns Test Conditions Figure 25.28 Figure 25.27 Figures 25.29 to 25.32 2.5 x tcyc - 20 3.0 x tcyc - 20 1 1 1 1 18 15 15 15 Address delay time 2 CS delay time 4 DQM delay time CKE delay time Table 25.6 Bus Timing (4) Conditions: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, B = 8 MHz to 50 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Read data setup time 3 Read data hold time 3 Read data setup time 4 Read data hold time 4 Write data delay time 2 Write data hold time 4 Symbol tRDS3 tRDH3 tRDS4 tRDH4 tWDD2 tWDH4 Min. 12 0 12 0 1 Max. 15 Unit ns ns ns ns ns ns Test Conditions Figures 25.29 to 25.32 Rev.1.00 Jun. 07, 2006 Page 1051 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics T1 B T2 tAD A23 to A0 tCSD1 CS7 to CS0 tAS1 tASD tASD tAH1 AS tBSD BS tBSD tRWD tRWD RD/WR tAS1 tRSD1 tRSD1 Read (RDNn = 1) RD tAC5 tAA2 tRDS1 tRDH1 D15 to D0 tRWD tRWD RD/WR RD tAS1 tRSD1 tRSD2 Read (RDNn = 0) D15 to D0 tAC2 tAA3 tRWD tRDS2 tRDH2 tRWD RD/WR tAS1 LHWR, LLWR tWRD2 tWRD2 tAH1 Write tWDD D15 to D0 (write) tWSW1 tWDH1 tDACD1 tDACD2 (DKC = 0) DACK0 to DACK3 (DKC = 1) DACK0 to DACK3 tDACD2 tDACD2 Figure 25.8 Basic Bus Timing: Two-State Access Rev.1.00 Jun. 07, 2006 Page 1052 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics T1 T2 T3 B tAD A23 to A0 tCSD1 CS7 to CS0 tAS1 tASD tASD tAH1 AS tBSD tBSD BS tRWD tRWD RD/WR tAS1 tRSD1 tRSD1 Read (RDNn = 1) RD tAC6 tAA4 tRWD tRDS1 tRDH1 D15 to D0 tRWD RD/WR tAS1 tRSD1 tRSD2 Read (RDNn = 0) RD tAC4 tRDS2 tRDH2 D15 to D0 tRWD tAA5 tRWD RD/WR tAS2 tWRD1 tWRD2 tAH1 Write LHWR, LLWR tWDD tWDS1 tWSW2 tWDH1 D15 to D0 (write) tDACD1 tDACD2 (DKC = 0) DACK0 to DACK3 (DKC = 1) DACK0 to DACK3 tDACD2 tDACD2 Figure 25.9 Basic Bus Timing: Three-State Access Rev.1.00 Jun. 07, 2006 Page 1053 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics T1 B T2 Tw T3 A23 to A0 CS7 to CS0 AS BS RD/WR Read (RDNn = 1) RD D15 to D0 RD/WR Read (RDNn = 0) RD D15 to D0 RD/WR Write LHWR, LLWR D15 to D0 tWTS tWTH WAIT tWTS tWTH Figure 25.10 Basic Bus Timing: Three-State Access, One Wait Rev.1.00 Jun. 07, 2006 Page 1054 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics Th B T1 T2 Tt tAD A23 to A0 tCSD1 CS7 to CS0 tAS1 tASD AS tASD tAH1 tBSD BS tBSD tRWD RD/WR tRWD tAS3 Read (RDNn = 1) tRSD1 tRSD1 tAH3 RD tAC5 D15 to D0 tRDS1 tRDH1 tRWD RD/WR tRWD tAS3 Read (RDNn = 0) tRSD1 tRSD2 tAH2 RD tAC2 D15 to D0 tRDS2 tRDH2 tRWD tRWD RD/WR tAS3 Write LHWR, LLWR tWRD2 tWRD2 tAH3 tWDD D15 to D0 (write) tWDS2 tWSW1 tWDH3 tDACD1 (DKC = 0) DACK0 to DACK3 tDACD2 tDACD2 (DKC = 1) DACK0 to DACK3 tDACD2 Figure 25.11 Basic Bus Timing: Two-State Access (CS Assertion Period Extended) Rev.1.00 Jun. 07, 2006 Page 1055 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics Th B T1 T2 T3 Tt tAD A23 to A0 tCSD1 CS7 to CS0 tAS1 tASD AS tASD tAH1 tBSD BS tBSD tRWD RD/WR tRWD tAS3 Read (RDNn = 1) tRSD1 tRSD1 tAH3 RD tAC6 D15 to D0 tRDS1 tRDH1 tRWD RD/WR tRWD tAS3 Read (RDNn = 0) tRSD1 tRSD2 tAH2 RD tAC4 D15 to D0 tRDS2 tRDH2 tRWD tRWD RD/WR tAS4 Write LHWR, LLWR tWRD2 tWRD1 tWDS3 tAH3 tWDD D15 to D0 (write) tWSW2 tWDH3 tDACD1 (DKC = 0) DACK0 to DACK3 tDACD2 tDACD2 (DKC = 1) DACK0 to DACK3 tDACD2 Figure 25.12 Basic Bus Timing: Three-State Access (CS Assertion Period Extended) Rev.1.00 Jun. 07, 2006 Page 1056 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics T1 B tAD A23 to A0 tCSD1 CS7 to CS0 tAS1 AS tBSD BS tRWD RD/WR tAS1 tRSD1 tASD tASD T2 tAH1 tBSD tRWD tRSD1 Read RD tAC5 tRDS1 tRDH1 D15 to D0 tAA2 tAC5 tUBD LUB, LLB tAS1 tRWD RD/WR tUBW1 tAH1 tRWD tUBD Write RD High tWDD tWDH1 D15 to D0 (write) Figure 25.13 Byte Control SRAM: Two-State Read/Write Access Rev.1.00 Jun. 07, 2006 Page 1057 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics T1 B tAD A23 to A0 tCSD1 CS7 to CS0 tAS1 tASD T2 T3 tASD tAH1 AS tBSD BS tRWD RD/WR tAS1 tRSD1 Read RD tAC6 tAA4 D15 to D0 tAC6 tUBD LUB, LLB tAS1 tRWD RD/WR tUBW2 tUBD tAH1 tRWD tRDS1 tRDH1 tRSD1 tRWD tBSD Write RD D15 to D0 (write) High tWDD tWDH1 Figure 25.14 Byte Control SRAM: Three-State Read/Write Access Rev.1.00 Jun. 07, 2006 Page 1058 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics T1 B T2 T1 T1 A23 to A6, A0 tAD A5 to A1 CS7 to CS0 AS BS RD/WR tRSD2 Read RD tAA1 tRDS2 tRDH2 D15 to D0 LHWR, LLWR High Figure 25.15 Burst ROM Access Timing: One-State Burst Access Rev.1.00 Jun. 07, 2006 Page 1059 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics T1 B T2 T3 T1 T2 A23 to A6, A0 tAD A5 to A1 CS7 to CS0 tAS1 AS tASD tASD tAH1 BS RD/WR tRSD2 Read RD tAA3 D15 to D0 tRDS2 tRDH2 LHWR, LLWR High Figure 25.16 Burst ROM Access Timing: Two-State Burst Access Rev.1.00 Jun. 07, 2006 Page 1060 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics Tma1 B Tma2 T1 T2 tAD A23 to A0 CS7 to CS0 tAHD AH (AS) tAHD tAHW1 RD/WR Read RD tMAD1 D15 to D0 tMAS1 tMAH tRDS2 tRDH2 RD/WR tWSW1 Write LHWR, LLWR tMAS1 tMAD1 D15 to D0 tMAH tWDD tWDH1 BS DKC = 0 DACK3 to DACK0 DKC = 1 Figure 25.17 Address/Data Multiplexed Access Timing (No Wait) (Basic, Four-State Access) Rev.1.00 Jun. 07, 2006 Page 1061 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics Tma1 B Tmaw Tma2 T1 T2 Tpw Ttw T3 tAD A23 to A0 CS7 to CS0 tAHD AH (AS) tAHD tAHW2 RD/WR Read RD tMAS2 tMAD1 D15 to D0 tMAH tRDS2 tRDH2 RD/WR Write LHWR, LLWR tMAS2 tMAD1 tMAH tWDS1 tWDH1 D15 to D0 tWDD WAIT tWTS tWTH tWTS tWTH Figure 25.18 Address/Data Multiplexed Access Timing (Wait Control) (Address Cycle Program Wait x 1 + Data Cycle Program Wait x 1 + Data Cycle Pin Wait x 1) Rev.1.00 Jun. 07, 2006 Page 1062 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics Tp Tr Tc1 Tc2 B tAD tAD A23 to A0 tAS3 tAH1 tCSD2 tCSD3 RAS tPCH2 tCASW1 LUCAS, LLCAS tBSD tAC1 tBSD BS tRWD tRWD RD/WR tOED1 tOED1 OE, RD Read WE tAC4 tAA3 tRDS2 tRDH2 D15 to D0 tRWD tRWD RD/WR OE, RD Write WE tWDD tWRD2 tWCS1 tWCH1 tWRD2 tWDS1 tWDH2 D15 to D0 AS tDACD1 tDACD2 (DKC = 0) DACK3 to DACK0 tDACD2 tDACD2 (DKC = 1) DACK3 to DACK0 Note: Timming of DACK when DDS = 0 and EDDS = 0 Timming of RAS when RAST = 0 Figure 25.19 DRAM Access Timing: Two-State Access Rev.1.00 Jun. 07, 2006 Page 1063 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics Tp Tr Tc1 Tpw Ttw Tc2 B A23 to A0 RAS BS RD/WR LUCAS, LLCAS Read OE, RD WE D15 to D0 RD/WR LUCAS, LLCAS Write OE, RD WE D15 to D0 AS tWTS tWTH tWTS tWTH WAIT (DKC = 0) DACK3 to DACK0 (DKC = 1) DACK3 to DACK0 Timming of DACK when DDS = 0 and EDDS = 0 Timming of RAS when RAST = 0 Tcw is a wait cycle inserted by the programmable wait Tcwp is a wait cycle inserted by the pin wait Note: Figure 25.20 DRAM Access Timing: Two-State Access, One Wait Rev.1.00 Jun. 07, 2006 Page 1064 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics Tp Tr Tc1 Tc2 Tc1 Tc2 B A23 to A0 RAS tCPW1 LUCAS, LLCAS BS RD/WR OE, RD Read WE tAC3 D15 to D0 RD/WR OE, RD Write WE tRCH tRCS1 D15 to D0 AS tDACD1 tDACD2 (DKC = 0) DACK3 to DACK0 tDACD2 (DKC = 1) DACK3 to DACK0 Note: Timming of DACK when DDS = 0 and EDDS = 0 Timming of RAS when RAST = 0 Figure 25.21 DRAM Access Timing: Two-State Burst Access Rev.1.00 Jun. 07, 2006 Page 1065 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics Tp Tr Tc1 Tc2 Tc3 B tAD tAD A23 to A0 tAS2 tAH2 tCSD2 tPCH1 tCASW2 tCSD3 RAS LUCAS, LLCAS tBSD tBSD tAC2 BS tRWD tRWD RD/WR tOED2 tOED1 Read OE, RD WE tAC7 tAA5 tRDS2 tRDH2 D15 to D0 tRWD tRWD RD/WR OE, RD Write WE tWDD tWRD2 tWCS2 tWCH2 tWRD2 tWDS2 tWDH3 D15 to D0 AS tDACD1 tDACD2 (DKC = 0) DACK3 to DACK0 tDACD2 tDACD2 (DKC = 1) DACK3 to DACK0 Note: Timming of DACK when DDS = 0 and EDDS = 0 Timming of RAS when RAST = 1 Figure 25.22 DRAM Access Timing: Three-State Access (RAST = 1) Rev.1.00 Jun. 07, 2006 Page 1066 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics Tp Tr Tc1 Tpw Ttw Tc2 Tc3 B A23 to A0 RAS BS RD/WR LUCAS, LLCAS Read OE, RD WE D15 to D0 RD/WR LUCAS, LLCAS OE, RD WE Write D15 to D0 tWTS WAIT tWTH tWTS tWTH (DKC = 0) DACK3 to DACK0 (DKC = 1) DACK3 to DACK0 Note: Timming of DACK when DDS = 0 and EDDS = 0 Timming of RAS when RAST = 0 Tcw is a wait cycle inserted by the programmable wait Tcwp is a wait cycle inserted by the pin wait Figure 25.23 DRAM Access Timing: Three-State Access, One Wait Rev.1.00 Jun. 07, 2006 Page 1067 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics Tp Tr Tc1 Tc2 Tc3 Tc1 Tc2 Tc3 B A23 to A0 RAS tCPW2 LUCAS, LLCAS BS RD/WR OE, RD Read WE D15 to D0 tAC8 RD/WR OE, RD Write WE tRCS2 tRCH D15 to D0 AS (DKC = 0) DACK3 to DACK0 (DKC = 1) DACK3 to DACK0 Timming of DACK when DDS = 1 and EDDS = 1 Timming of RAS when RAST = 1 Note: Figure 25.24 DRAM Access Timing: Three-State Burst Access Rev.1.00 Jun. 07, 2006 Page 1068 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics TRp B TRr TRc1 TRc2 tCSD1 RAS tCSD2 tCSR1 tCASD1 LUCAS, LLCAS tCASD1 OE Figure 25.25 CAS Before RAS Refresh Timing TRp TRrw TRr TRc1 TRcw TRc2 B tCSD1 RAS tCSD2 tCSR2 tCASD1 tCASD1 LUCAS, LLCAS OE Figure 25.26 CAS Before RAS Refresh Timing (Wait Cycle Inserted) Self refresh TRp TRr TRc3 TRc4 DRAM access Tp Tr B tCSD2 tCSD2 tRPS2 tCASD1 tCASD1 RAS LUCAS, LLCAS OE Figure 25.27 Self-Refresh Timing (After Leaving Software Standby: RAST = 0) Rev.1.00 Jun. 07, 2006 Page 1069 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics TRp TRr TRc3 Self-refresh TRc4 DRAM access Tp Tr B tCSD2 RAS tCASD1 LUCAS, LLCAS tCASD1 tRPS1 tCSD2 OE Figure 25.28 Self-Refresh Timing (After Leaving Software Standby: RAST = 1) Tp Tr Tc1 Tcl Tc2 SD tAD2 A23 to A0 Precharge-sel tCSD4 CS tBSD tBSD BS tCSD4 tCSD4 RAS tCSD4 tCSD4 CAS WE CKE tCSD4 tCSD4 Read tDQMD tDQMD tRDS3 tRDH3 DQMLU, DQMLL D15 to D0 PALL ACTV READ NOP NOP Figure 25.29 Synchronous DRAM Basic Read Access Timing (CAS Latency 2) Rev.1.00 Jun. 07, 2006 Page 1070 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics Tp Tr Tc1 Tc2 SD tAD2 A23 to A0 Precharge-sel tCSD4 CS tBSD tBSD BS tCSD4 tCSD4 RAS tCSD4 tCSD4 CAS tCSD4 tCSD4 tCSD4 tCSD4 WE Wirte CKE tDQMD tDQMD DQMLU, DQMLL tWDD tWDH4 D15 to D0 PALL ACTV NOP WRIT Figure 25.30 Synchronous DRAM Basic Write Access Timing (CAS Latency 2) Rev.1.00 Jun. 07, 2006 Page 1071 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics Tp Tr Tc1 Tcl Tsp Tc2 SD A23 to A0 Precharge-sel BS RAS CAS WE CKE tCKED tCKED DQMLU, DQMLL D15 to D0 DACK DKC = 0 DKC = 1 Figure 25.31 Extended Read Data Cycle (CAS Latency 2) Rev.1.00 Jun. 07, 2006 Page 1072 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics TRp TRr Software standby TRc2 TRc3 SD A23 to A0 Precharge-sel CS RAS CAS WE tCKED CKE tCKED Figure 25.32 Synchronous DRAM Self-Refresh Timing B tBREQS BREQ tBACD BACK tBZD A23 to A0 tBZD tBACD tBREQS CS7 to CS0 D15 to D0 AS, RD, LHWR, LLWR Figure 25.33 External Bus Release Timing Rev.1.00 Jun. 07, 2006 Page 1073 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics B BACK tBRQOD BREQO tBRQOD Figure 25.34 External Bus Request Output Timing 25.3.4 DMAC Timing Table 25.7 DMAC Timing Conditions: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, B = 8 MHz to 50 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item DREQ setup time DREQ hold time TEND delay time DACK delay time 1 DACK delay time 2 Symbol tDRQS tDRQH tTED tDACD1 tDACD2 Min. 20 5 Max. 15 15 15 Unit ns ns ns ns ns Figure 25.36 Figures 25.37, 25.38 Test Conditions Figure 25.35 B tDRQS tDRQH DREQ0 to DREQ3 Figure 25.35 DMAC (DREQ) Input Timing Rev.1.00 Jun. 07, 2006 Page 1074 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics T1 B tTED TEND0 to TEND3 T2 or T3 tTED Figure 25.36 DMAC (TEND) Output Timing T1 B A23 to A0 T2 CS7 to CS0 AS RD (read) D15 to D0 (read) LHWR, LLWR (write) D15 to D0 (write) tDACD1 DACK0 to DACK3 (DKC = 0) tDACD2 DACK0 to DACK3 (DKC = 1) BS tDACD2 tDACD2 RD/WR Figure 25.37 DMAC Single-Address Transfer Timing: Two-State Access Rev.1.00 Jun. 07, 2006 Page 1075 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics T1 B T2 T3 A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) LHWR, LLWR (write) D15 to D0 (write) tDACD1 tDACD2 DACK0 to DACK3 (DKC = 0) tDACD2 tDACD2 DACK0 to DACK3 (DKC = 1) BS RD/WR Figure 25.38 DMAC Single-Address Transfer Timing: Three-State Access Rev.1.00 Jun. 07, 2006 Page 1076 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics 25.3.5 Timing of On-Chip Peripheral Modules Table 25.8 Timing of On-Chip Peripheral Modules Conditions: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, P = 8 MHz to 35 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item I/O ports Output data delay time Input data setup time Input data hold time TPU Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width Single-edge setting Both-edge setting PPG 8-bit timer Pulse output delay time Timer output delay time Timer reset input setup time Timer clock input setup time Timer clock pulse width Single-edge setting Both-edge setting WDT SCI Overflow output delay time Input clock cycle Asynchronous Clocked synchronous tSCKW tSCKr tSCKf Symbol tPWD tPRS tPRH tTOCD tTICS tTCKS tTCKWH tTCKWL tPOD tTMOD tTMRS tTMCS tTMCWH tTMCWL tWOVD tScyc Min. 25 25 25 25 1.5 2.5 25 25 1.5 2.5 4 6 0.4 Max. 40 40 40 40 40 0.6 1.5 1.5 tScyc tcyc tcyc Unit ns ns ns ns ns ns tcyc tcyc ns ns ns ns tcyc tcyc ns tcyc Figure 25.46 Figure 25.47 Figure 25.42 Figure 25.43 Figure 25.44 Figure 25.45 Figure 25.41 Figure 25.40 Test Conditions Figure 25.39 Input clock pulse width Input clock rise time Input clock fall time Rev.1.00 Jun. 07, 2006 Page 1077 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics Item SCI Transmit data delay time Receive data setup time (clocked synchronous) Receive data hold time (clocked synchronous) A/D Trigger input setup time converter IIC2 SCL input cycle time SCL input high pulse width SCL input low pulse width SCL, SDA input falling time SCL, SDA input spike pulse removal time SDA input bus free time Symbol tTXD tRXS tRXH tTRGS tSCL tSCLH tSCLL tSf tSP tBUF tSTAS tSTOS tSDAS tSDAH Cb tSf Min. 40 40 30 12 tcyc + 600 3 tcyc + 300 5 tcyc + 300 Max. 40 300 1 tcyc Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF ns Test Conditions Figure 25.48 Figure 25.49 Figure 25.50 5 tcyc 3 tcyc 3 tcyc Start condition input hold time tSTAH Retransmit start condition input setup time Stop condition input setup time Data input setup time Data input hold time SCL, SDA capacitive load SCL, SDA falling time 1 tcyc + 20 0 0 400 300 Rev.1.00 Jun. 07, 2006 Page 1078 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics T1 P tPRS tPRH Ports 1 to 3, 5, 6, A, to F, H, I, M (read) T2 tPWD Ports 1 to 3, 6, A to F, H, I,M (write) Figure 25.39 I/O Port Input/Output Timing P tTOCD Output compare output* tTICS Input capture input* Note: * TIOCA0 to TIOCA5, TIOCB0 to TIOCB5, TIOCC0, TIOCC3, TIOCD0, TIOCD3 Figure 25.40 TPU Input/Output Timing P tTCKS TCLKA to TCLKD tTCKWL tTCKWH tTCKS Figure 25.41 TPU Clock Input Timing P tPOD PO15 to PO0 Figure 25.42 PPG Output Timing Rev.1.00 Jun. 07, 2006 Page 1079 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics P tTMOD TMO0 to TMO3 Figure 25.43 8-Bit Timer Output Timing P tTMRS TMRI0 to TMRI3 Figure 25.44 8-Bit Timer Reset Input Timing P tTMCS TMCI0 to TMCI3 tTMCWL tTMCWH tTMCS Figure 25.45 8-Bit Timer Clock Input Timing P tWOVD WDTOVF tWOVD Figure 25.46 WDT Output Timing tSCKW SCK0 to SCK2, SCK4 tScyc tSCKr tSCKf Figure 25.47 SCK Clock Input Timing Rev.1.00 Jun. 07, 2006 Page 1080 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics SCK0 to SCK2, SCK4 TxD0 to TxD2, TxD4 (transmit data) RxD0 to RxD2, RxD4 (receive data) tTXD tRXS tRXH Figure 25.48 SCI Input/Output Timing: Clocked Synchronous Mode P tTRGS ADTRG0 Figure 25.49 A/D Converter External Trigger Input Timing SDA0 to SDA1 tBUF VIH VIL tSTAH SCL0 to SCL1 P* S* tSf tSCLL tSCL Note: tSCLH tSTAS tSP tSTOS Sr* tSr tSDAH tSDAS P* S, P, and Sr represent the following conditions: S: Start condition P: Stop condition Sr: Retransmit start condition Figure 25.50 I C Bus Interface2 Input/Output Timing (Option) 2 Rev.1.00 Jun. 07, 2006 Page 1081 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics 25.4 USB Characteristics Table 25.9 USB Characteristics when On-Chip USB Transceiver is Used (USD+, USD- pin characteristics) Conditions: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V, VSS = PLLVSS = DrVSS = AVSS = 0 V, CKU = 48 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Input Input high voltage Input low voltage Differential input sensitivity Differential common mode range Output Output high voltage Output low voltage Crossover voltage Rising time Falling time Ratio of rising time to falling time Output resistance Symbol VIH VIL VDI VCM VOH VOL VCRS tR tF tRFM ZDRV Min. 2.0 0.2 0.8 2.8 1.3 4 4 90 28 Max. 0.8 2.5 0.3 2.0 20 20 111.11 44 Unit Test Conditions V V V V V V V ns ns % (TR/TF) Including RS = 22 IOH = -200 A IOL = 2 mA (D+) - (D-) Figures 25.51, 25.52 Rev.1.00 Jun. 07, 2006 Page 1082 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics Rise time USD+, USDVCRS 10% Differential data lines tR 90% Fall time 90% 10% tF Figure 25.51 Data Signal Timing USD+ RS = 22 Test point CL = 50 pF USD- RS = 22 Test point CL = 50 pF Figure 25.52 Load Condition Rev.1.00 Jun. 07, 2006 Page 1083 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics 25.5 A/D Conversion Characteristics Table 25.10 A/D Conversion Characteristics Conditions: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, P = 8 MHz to 35 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Resolution Conversion time Analog input capacitance Permissible signal source impedance Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Min. 10 7.6 Typ. 10 0.5 Max. 10 20 5 7.5 7.5 7.5 8.0 Unit Bit s pF k LSB LSB LSB LSB LSB 25.6 D/A Conversion Characteristics Table 25.11 D/A Conversion Characteristics Conditions: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, P = 8 MHz to 35 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Resolution Conversion time Absolute accuracy Min. 8 Typ. 8 2.0 Max. 8 10 3.0 2.0 Unit Bit s LSB LSB 20-pF capacitive load 2-M resistive load 4-M resistive load Test Conditions Rev.1.00 Jun. 07, 2006 Page 1084 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics 25.7 25.7.1 Flash Memory Characteristics H8SX/1663 Table 25.12 Flash Memory Characteristics Conditions: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, Operating temperature range during programming/erasing: Ta = 0C to +75C (regular specifications), Ta = 0C to +85C (wide-range specifications) Item Programming time* * * Erasure time* * * 1, 2, 4 1, 2, 4 Symbol tP tE Min. Typ. 3 160 1000 2000 8 15 23 3 Max. 30 800 5000 10000 23 45 68 Unit ms/128 bytes ms/4-kbyte block ms/32-kbyte block ms/64-kbyte block s/384 kbytes s/384 kbytes s/384 kbytes times years Test Conditions Programming time 1, 2, 4 (total)* * * Erasure time (total)* * * Programming, Erasure 1, 2, 4 time (total)* * * Overwrite count Data save time* 5 1, 2, 4 tP tE tPE NWEC TDRP 100* 10 Ta = 25C, for all 0s Ta = 25C Ta = 25C Notes: 1. Programming time and erase time depend on data in the flash memory. 2. Programming time and erase time do not include time for data transfer. 3. All the characteristics after programming are guaranteed within this value (guaranteed value is from 1 to Min. value). 4. Characteristics when programming is performed within the Min. value Rev.1.00 Jun. 07, 2006 Page 1085 of 1102 REJ09B0294-0100 Section 25 Electrical Characteristics 25.7.2 H8SX/1664 Table 25.13 Flash Memory Characteristics Conditions: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, Operating temperature range during programming/erasing: Ta = 0C to +75C (regular specifications), Ta = 0C to +85C (wide-range specifications) Item Programming time* * * Erasure time* * * 1, 2, 4 1, 2, 4 Symbol tP tE Min. Typ. 3 160 1000 2000 10 20 30 3 Max. 30 800 5000 10000 30 60 90 Unit ms/128 bytes ms/4-kbyte block ms/32-kbyte block ms/64-kbyte block s/512 kbytes s/512 kbytes s/512 kbytes times years Test Conditions Programming time 1, 2, 4 (total)* * * Erasure time (total)* * * Programming, Erasure 1, 2, 4 time (total)* * * Overwrite count Data save time* 5 1, 2, 4 tP tE tPE NWEC TDRP 100* 10 Ta = 25C, for all 0s Ta = 25C Ta = 25C Notes: 1. Programming time and erase time depend on data in the flash memory. 2. Programming time and erase time do not include time for data transfer. 3. All the characteristics after programming are guaranteed within this value (guaranteed value is from 1 to Min. value). 4. Characteristics when programming is performed within the Min. value Rev.1.00 Jun. 07, 2006 Page 1086 of 1102 REJ09B0294-0100 Appendix Appendix A. Port States in Each Pin State Port States in Each Pin State MCU Operating Mode Reset All All All All All Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hardware Standby Mode Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Software Standby Mode OPE = 1 Keep Keep Keep Hi-Z [DAOE0 = 1] Keep [DAOE0 = 0] Hi-Z [DAOE1 = 1] Keep [DAOE1 = 0] Hi-Z Keep [BREQO output] Hi-Z [BS output] Keep [Other than above] Keep [BACK output] Hi-Z [RD/WR output] Keep [Other than above] Keep OPE = 0 Keep Keep Keep Hi-Z [DAOE0 = 1] Keep [DAOE0 = 0] Hi-Z [DAOE1 = 1] Keep [DAOE1 = 0] Hi-Z Keep [BREQO output] Hi-Z [BS output] Hi-Z [Other than above] Keep [BACK output] Hi-Z [RD/WR output] Hi-Z [Other than above] Keep Bus Released State Keep Keep Keep Keep Keep Table A.1 Port Name Port 1 Port 2 Port 3 P55 to P50 P56/ AN6/ DA0/ IRQ6-B P57/ AN7/ DA1/ IRQ7-B P65 to P60 PA0/ BREQO/ BS-A All Hi-Z Hi-Z Keep All All Hi-Z Hi-Z Hi-Z Hi-Z Keep [BREQO output] BREQO [BS output] Hi-Z [Other than above] Keep [BACK output] BACK PA1/ BACK/ (RD/WR) All Hi-Z Hi-Z Rev.1.00 Jun. 07, 2006 Page 1087 of 1102 REJ09B0294-0100 Appendix Hardware Standby Mode Hi-Z Software Standby Mode OPE = 1 [BREQ input] Hi-Z [WAIT input] Hi-Z [Other than above] Keep Keep H Keep [LHWR, LUB output] H [Other than above] Keep Keep H [AS, BS output] H [AH output] L [Other than above] Keep PA7/B Single-chip mode (EXPE = 0) External extended mode (EXPE = 1) PB0/ CS0/ CS4/ CS5-B Single-chip mode (EXPE = 0) External extended mode (EXPE = 1) Hi-Z Hi-Z [Clock output] H [Other than above] Keep Hi-Z H Hi-Z [CS output] H [Other than above] Keep [Clock output] H [Other than above] Keep [CS output] Hi-Z [Other than above] Keep [Clock output] Clock output [Other than above] Keep [CS output] Hi-Z [Other than above] Keep OPE = 0 [BREQ input] Hi-Z [WAIT input] Hi-Z [Other than above] Keep Keep Hi-Z Keep [LHWR, LUB output] Hi-Z [Other than above] Keep Keep Hi-Z [AS, AH, BS output] Hi-Z [Other than above] Keep Bus Released State [BREQ input] Hi-Z (BREQ) [WAIT input] Hi-Z (WAIT) MCU Operating Port Name Mode PA2/ BREQ/ WAIT All Reset Hi-Z PA3/ LLWR/ LLB PA4/ LHWR/ LUB Single-chip mode (EXPE = 0) External extended mode (EXPE = 1) Single-chip mode (EXPE = 0) External extended mode (EXPE = 1) Hi-Z H Hi-Z H Hi-Z Hi-Z Hi-Z Hi-Z Keep Hi-Z Keep [LHWR, LUB output] Hi-Z [Other than above] Keep Keep Hi-Z [AS, AH, BS output] Hi-Z [Other than above] Keep PA5/RD Single-chip mode (EXPE = 0) External extended mode (EXPE = 1) Hi-Z H Hi-Z H Hi-Z Hi-Z Hi-Z PA6/ AS/ AH/ BS-B Single-chip mode (EXPE = 0) External extended mode (EXPE = 1) Clock output Hi-Z Rev.1.00 Jun. 07, 2006 Page 1088 of 1102 REJ09B0294-0100 Appendix Hardware Standby Mode Hi-Z Software Standby Mode OPE = 1 [CS output] H [Other than above] Keep [CS output] H [Other than above] Keep PB3/ CS3/ CS7-A All Hi-Z Hi-Z [CS output] H [Other than above] Keep PC2/ LUCAS/ DQMLU All Hi-Z Hi-Z [LUCAS, DQMLU output] H [Other than above] Keep PC3/ LLCAS/ DQMLL All Hi-Z Hi-Z [LLCAS, DQMLL output] H [Other than above] Keep Keep Keep OPE = 0 [CS output] Hi-Z [Other than above] Keep [CS output] Hi-Z [Other than above] Keep [CS output] Hi-Z [Other than above] Keep [LUCAS, DQMLU output] Hi-Z [Other than above] Keep [LLCAS, DQMLL output] Hi-Z [Other than above] Keep Hi-Z [Address output] Hi-Z [Other than above] Keep Single-chip mode (EXPE = 0) Hi-Z Hi-Z Keep Keep Bus Released State [CS output] Hi-Z [Other than above] Keep [CS output] Hi-Z [Other than above] Keep [CS output] Hi-Z [Other than above] Keep [LUCAS, DQMLU output] Hi-Z [Other than above] Keep [LLCAS, DQMLL output] Hi-Z [Other than above] Keep Hi-Z [Address output] Hi-Z [Other than above] Keep Keep MCU Operating Port Name Mode PB1/ CS1/ CS2-B/ CS5-A/ CS6-B/ CS7-B PB2/ CS2-A/ CS6-A All Reset Hi-Z All Hi-Z Hi-Z Port D External extended mode (EXPE = 1) ROM enabled extended mode L Hi-Z Hi-Z Hi-Z Rev.1.00 Jun. 07, 2006 Page 1089 of 1102 REJ09B0294-0100 Appendix Hardware Standby Mode Hi-Z Hi-Z Software Standby Mode OPE = 1 Keep Keep OPE = 0 Hi-Z [Address output] Hi-Z [Other than above] Keep Single-chip mode (EXPE = 0) PF7 to PF4 External extended mode (EXPE = 1) Hi-Z L/ Hi-Z* Hi-Z Hi-Z Keep Keep Keep [Address output] Hi-Z [Other than above] Keep Single-chip mode (EXPE = 0) Port H Single-chip mode (EXPE = 0) External extended mode (EXPE = 1) Port I Single-chip mode (EXPE = 0) External extended mode (EXPE = 1) 8-bit bus mode 16-bit bus mode 32-bit bus mode Port M All Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Keep Keep Hi-Z Keep Keep Keep Keep Hi-Z Keep Keep Bus Released State Hi-Z [Address output] Hi-Z [Other than above] Keep Keep [Address output] Hi-Z [Other than above] Keep Keep Keep Hi-Z Keep Keep MCU Operating Port Name Mode Port E External extended mode (EXPE = 1) ROM enabled extended mode Reset L Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Keep Keep Keep [Legend] H: High-level output L: Low-level output Keep: Input pins become high-impedance, output pins retain their state. Hi-Z: High impedance Rev.1.00 Jun. 07, 2006 Page 1090 of 1102 REJ09B0294-0100 Appendix B. Product Lineup Product Model R5F61663 R5F61664 Marking R5F61663 R5F61664 Package (Package Code) FP-144LV* FP-144LV* Product Classification H8SX/1663 H8SX/1664 Note: * Pb-free version Rev.1.00 Jun. 07, 2006 Page 1091 of 1102 REJ09B0294-0100 C. Appendix E HE c1 c *2 A 36 F ZE A1 For the package dimensions, data in the Renesas IC Package General Catalog has priority. Figure C.1 Package Dimensions (FP-144LV) 1 ZD Index mark A2 L L1 c REJ09B0294-0100 RENESAS Code PLQP0144KA-A Previous Code 144P6Q-A / FP-144L / FP-144LV MASS[Typ.] 1.2g HD JEITA Package Code P-LQFP144-20x20-0.50 *1 D 108 73 Package Dimensions 109 72 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. Rev.1.00 Jun. 07, 2006 Page 1092 of 1102 bp b1 Reference Symbol Dimension in Millimeters Terminal cross section 144 37 D E A2 HD HE A A1 bp b1 c c1 *3 y x bp e Detail F e x y ZD ZE L L1 Min Nom Max 19.9 20.0 20.1 19.9 20.0 20.1 1.4 21.8 22.0 22.2 21.8 22.0 22.2 1.7 0.05 0.1 0.15 0.17 0.22 0.27 0.20 0.09 0.145 0.20 0.125 0 8 0.5 0.08 0.10 1.25 1.25 0.35 0.5 0.65 1.0 Appendix D. Treatment of Unused Pins The treatments of unused pins are listed in table D.1 Table D.1 Pin Name RES STBY EMLE MD_CLK MD3, MD2, MD1, MD0 NMI EXTAL XTAL OSC1 OSC2 WDTOVF USD+ USDVBUS Port 1 Port 2 Port 3 Port 6 PA2 to PA0 PB7 to PB1 Port C PF7 to PF5 Port M Port 5 * Connect these pins to AVcc via a pull-up resistor or to AVss via a pull-down resistor, respectively Treatment of Unused Pins Mode 4 * * Mode 5 Mode 6 Mode 7 (Always used as a reset pin) Connect this pin to VCC via a pull-up resistor Connect this pin to VSS via a pull-down resistor (Always used as a mode pin) (Always used as mode pins) * * * * * * * * * Connect this pin to VCC via a pull-up resistor (Always used as a clock pin) Leave this pin open Connect this pin to VSS via a pull-down resistor Leave this pin open Leave this pin open Leave this pin open Leave this pin open Connect this pin to VSS via a pull-down resistor Connect these pins to VCC via a pull-up resistor or to VSS via a pull-down resistor, respectively Rev.1.00 Jun. 07, 2006 Page 1093 of 1102 REJ09B0294-0100 Appendix Pin Name PA7 PA6 PA5 PA4 PA3 PB0 Port D Port E PF4 to PF0 Port H Port I Mode 4 * * * * * * * Mode 5 Mode 6 Mode 7 Connect these pins to VCC via a pull-up resistor or to VSS via a pulldown resistor, respectively This pin is left open in the initial state for the B output. * This pin is left open in the initial state for the AS output. This pin is left open in the initial state for the RD output. This pin is left open in the initial state for the LHWR output. This pin is left open in the initial state for the LLWR output. This pin is left open in the initial state for the CS0 output. These pins are left open in the initial state for the address output. (Used as a data bus) (Used as a data bus) * Connect these pins to VCC via a pull-up resistor or to VSS via a pulldown resistor, respectively, in the initial state for the general input. Vref * Connect this pin to AVcc Notes: 1. Do not change the initial value (input-buffer disabled) of PnICR, where n corresponds to an unused pin. 2. When the pin function is changed from its initial state, use a pull-up or pull-down resistor as needed. Rev.1.00 Jun. 07, 2006 Page 1094 of 1102 REJ09B0294-0100 Index Numerics clock output control ............................. 992 0-output/1-output .................................... 540 16-bit access space.................................. 190 16-bit counter mode................................ 628 16-bit timer pulse unit (TPU).................. 497 32K timer (TM32K) ............................... 637 8-bit access space.................................... 189 8-bit timers (TMR) ................................. 605 B Basic bus interface .......................... 181, 192 Big endian ............................................... 180 Bit rate..................................................... 681 Bit synchronous circuit ........................... 847 Block diagram............................................. 2 Block structure ........................................ 879 Block transfer mode ........................ 349, 417 Boot mode....................................... 877, 903 Buffer operation ...................................... 545 Bulk-in transfer ....................................... 802 Bulk-out transfer ..................................... 801 Burst access mode................................... 355 Burst ROM interface....................... 181, 213 Bus access modes.................................... 354 Bus arbitration......................................... 311 Bus configuration.................................... 168 Bus controller (BSC)............................... 131 Bus cycle division ................................... 411 Bus release .............................................. 304 Bus width ................................................ 180 Byte control SRAM interface ......... 181, 205 A A/D conversion accuracy........................ 861 A/D converter ......................................... 849 Absolute accuracy................................... 861 Acknowledge .......................................... 833 Address error ............................................ 84 Address map ............................................. 73 Address modes........................................ 343 Address/data multiplexed I/O interface .......................................... 182, 218 All-module-clock-stop mode .................. 972 Area 0 ..................................................... 184 Area 1 ..................................................... 185 Area 2 ..................................................... 185 Area 3 ..................................................... 186 Area 4 ..................................................... 186 Area 5 ..................................................... 187 Area 6 ..................................................... 188 Area 7 ..................................................... 188 Area division........................................... 177 Asynchronous mode ............................... 698 AT-cut parallel-resonance type............... 963 Available output signal and settings in each port ............................................. 476 Average transfer rate generator............... 654 C Cascaded connection............................... 628 Cascaded operation ................................. 549 Chain transfer.......................................... 418 Chip select signals................................... 178 Clock pulse generator.............................. 957 Clock synchronization cycle (Tsy).......... 170 Clocked synchronous mode .................... 715 Communications protocol ....................... 932 Compare match A ................................... 626 Compare match B ................................... 627 Compare match count mode ................... 629 Compare match signal............................. 626 Rev.1.00 Jun. 07, 2006 Page 1095 of 1102 REJ09B0294-0100 Control transfer....................................... 795 Counter operation ................................... 537 CPU priority control function over DTC and DMAC ............................................. 125 CRC Operation Circuit ........................... 744 Crystal resonator..................................... 963 Cycle stealing mode................................ 354 External clock ......................................... 964 External interrupts................................... 109 F Flash erase block select parameter.......... 901 Flash memory ......................................... 875 Flash multipurpose address area parameter ................................................ 899 Flash multipurpose data destination parameter ................................................ 900 Flash pass and fail parameter .................. 894 Flash program/erase frequency parameter ................................................ 898 Free-running count operation.................. 538 Frequency divider ........................... 957, 965 Full address mode ................................... 405 Full-scale error........................................ 861 D D/A converter ......................................... 867 Data direction register ............................ 437 Data register............................................ 438 Data stage ............................................... 797 Data transfer controller (DTC) ............... 395 Direct convention ................................... 723 DMA controller (DMAC)....................... 317 Double-buffered structure....................... 698 Download pass/fail result parameter....... 893 DRAM interface ..................................... 228 DRAM Interface ..................................... 182 DTC vector address ................................ 407 DTC vector address offset ...................... 407 Dual address mode.................................. 343 G General illegal instructions ....................... 89 H E Endian and data alignment...................... 189 Endian format ......................................... 180 Error protection ...................................... 925 Error signal ............................................. 723 Exception handling ................................... 77 Extended repeat area............................... 341 Extended repeat area function ................ 356 Extension of chip select (CS) assertion period...................................................... 202 External access bus................................. 168 External bus ............................................ 173 External bus clock (B) .................. 169, 957 External bus interface ............................. 179 Rev.1.00 Jun. 07, 2006 Page 1096 of 1102 REJ09B0294-0100 Hardware protection................................ 924 Hardware standby mode ................. 972, 987 I I/O ports .................................................. 429 I2C bus format ......................................... 833 I2C bus interface2 (IIC2)......................... 817 ID code.................................................... 709 Idle cycle................................................. 291 Illegal instruction ...................................... 89 Input buffer control register .................... 439 Input capture function ............................. 541 Internal interrupts.................................... 110 Internal peripheral bus ............................ 168 Internal system bus ................................. 168 Interrupt .................................................... 86 Interrupt control mode 0 ......................... 116 Interrupt control mode 2 ......................... 118 Interrupt controller.................................... 93 Interrupt exception handling sequence ... 120 Interrupt exception handling vector table 111 Interrupt response times.......................... 121 Interrupt sources ..................................... 109 Interrupt sources and vector address offsets ................................................................ 111 Interrupt-in transfer................................. 804 Interval timer .......................................... 648 Interval timer mode................................. 648 Inverse convention.................................. 724 IRQn interrupts ....................................... 109 N NMI interrupt .......................................... 109 Noise canceler ......................................... 842 Nonlinearity error.................................... 861 Non-overlapping pulse output................. 597 Normal transfer mode ............................. 414 Normal transfer mode ............................. 347 Number of Access Cycles ....................... 181 O Offset addition ........................................ 359 Offset error.............................................. 861 On-board programming........................... 903 On-board programming mode................. 903 On-chip baud rate generator.................... 701 On-chip ROM disabled extended mode ................ 65 On-chip ROM enabled extended mode ................. 65 Open-drain control register ..................... 441 Oscillator................................................. 963 Output buffer control .............................. 441 Output trigger.......................................... 596 Overflow ......................................... 628, 646 L Little endian............................................ 180 M Mark state ....................................... 698, 739 Master receive mode............................... 836 Master transmit mode ............................. 834 MCU operating modes.............................. 65 Mode 2...................................................... 70 Mode 4...................................................... 70 Mode 5...................................................... 70 Mode 6...................................................... 71 Mode 7...................................................... 71 Mode pin................................................... 65 Module stop function.............................. 981 Multi-clock function ............................... 980 Multiprocessor bit................................... 709 Multiprocessor communication function................................................... 709 P Package ....................................................... 2 Package dimensions .................... 1094, 1095 Parity bit.................................................. 698 Periodic count operation ......................... 538 Peripheral module clock (P).......... 169, 957 Phase counting mode .............................. 556 Pin assignments........................................... 3 Pin configuration in each operating mode............................................................ 4 Pin functions ............................................... 9 PLL circuit ...................................... 957, 965 Port function controller ........................... 483 Port register............................................. 438 Power-down modes................................. 971 Rev.1.00 Jun. 07, 2006 Page 1097 of 1102 REJ09B0294-0100 Product lineup....................................... 1093 Programmable pulse generator (PPG) .... 583 Programmer mode .......................... 877, 930 Programming/erasing interface............... 881 Programming/erasing interface parameters............................................... 891 Programming/erasing interface register .................................................... 885 Protection................................................ 924 Pull-up MOS control register.................. 440 PWM modes ........................................... 551 Q Quantization error................................... 861 R RAM ....................................................... 873 Read strobe (RD) timing......................... 201 Register addresses ..................................... 996 Register Bits ........................................... 1008 Register configuration in each port......... 436 Registers ABWCR ................135, 1000, 1015, 1030 ADCR ....................855, 1005, 1022, 1036 ADCSR..................853, 1005, 1022, 1036 ADDR....................852, 1005, 1021, 1036 ASTCR ..................136, 1000, 1016, 1030 BCR1 .....................148, 1001, 1016, 1031 BCR2 .....................150, 1001, 1016, 1031 BROMCR ..............153, 1001, 1016, 1031 BRR .......................681, 1005, 1021, 1035 CCR ...................................................... 33 CPUPCR..................97, 1003, 1019, 1034 CRA.................................................... 401 CRB .................................................... 402 CRCCR....................745, 996, 1008, 1025 CRCDIR ..................746, 996, 1008, 1025 CRCDOR.................746, 996, 1008, 1025 Rev.1.00 Jun. 07, 2006 Page 1098 of 1102 REJ09B0294-0100 CSACR ................. 143, 1001, 1016, 1031 CTLR ...................... 776, 997, 1009, 1026 CVR ........................ 776, 997, 1009, 1026 DACR ..................... 336, 999, 1012, 1029 DACR01 ............... 869, 1004, 1020, 1035 DADR0 ................. 868, 1004, 1020, 1035 DADR1 ................. 868, 1004, 1020, 1035 DAR .................................................... 401 DASTS.................... 770, 997, 1009, 1026 DBSR ...................... 326, 999, 1012, 1029 DDAR ..................... 323, 999, 1011, 1029 DDR ........................ 437, 998, 1010, 1027 DMA ....................... 772, 997, 1009, 1026 DMDR .................... 327, 999, 1012, 1029 DMRSR ................ 342, 1000, 1014, 1030 DOFR...................... 324, 999, 1012, 1029 DPFR .................................................. 893 DR......................... 438, 1004, 1020, 1034 DRACCR .............. 160, 1001, 1016, 1031 DRAMCR ............. 156, 1001, 1016, 1031 DSAR...................... 322, 999, 1011, 1029 DTCCR ................. 403, 1003, 1019, 1034 DTCER ................. 402, 1003, 1019, 1034 DTCR...................... 325, 999, 1012, 1029 DTCVBR .............. 405, 1000, 1015, 1030 ENDIANCR.......... 151, 1001, 1016, 1031 EPDR .................................................. 766 EPDR0i ................... 764, 997, 1009, 1026 EPDR0o .................. 765, 997, 1009, 1026 EPDR0s................... 765, 997, 1009, 1026 EPIR........................ 778, 997, 1009, 1026 EPSTL..................... 775, 997, 1009, 1026 EPSZ0o ................... 767, 997, 1009, 1026 EPSZ1 ..................... 768, 997, 1009, 1026 EXR ...................................................... 34 FCCS..................... 885, 1002, 1017, 1032 FCLR ...................... 771, 997, 1009, 1026 FEBS................................................... 901 FECS..................... 888, 1002, 1017, 1032 FKEY .................... 889, 1002, 1017, 1032 FMPAR............................................... 899 FMPDR............................................... 900 FPCS..................... 888, 1002, 1017, 1032 FPEFEQ.............................................. 898 FPFR................................................... 894 FTDAR ................. 890, 1002, 1017, 1032 General registers ................................... 31 ICCRA .................. 821, 1002, 1017, 1032 ICCRB .................. 822, 1002, 1017, 1032 ICDRR .................. 832, 1002, 1018, 1032 ICDRS ................................................ 832 ICDRT .................. 832, 1002, 1018, 1032 ICIER.................... 825, 1002, 1017, 1032 ICMR .................... 824, 1002, 1017, 1032 ICR ......................... 439, 998, 1010, 1028 ICSR ..................... 828, 1002, 1017, 1032 IDLCR .................. 146, 1001, 1016, 1031 IER........................ 100, 1003, 1019, 1034 IER (USB) .............. 762, 996, 1008, 1026 IFR (USB)............... 754, 996, 1008, 1026 INTCR .................... 96, 1003, 1019, 1034 IPR.......................... 98, 1000, 1015, 1030 IrCR ........................ 697, 997, 1010, 1027 ISCRH .................. 102, 1000, 1015, 1030 ISCRL................... 102, 1000, 1015, 1030 ISR ........................ 106, 1003, 1019, 1034 ISR (USB)............... 759, 997, 1009, 1026 MAC ..................................................... 35 MDCR .................... 66, 1001, 1017, 1031 MPXCR ................ 155, 1001, 1016, 1031 MRA ................................................... 398 MRB ................................................... 399 MSTPCRA............ 976, 1001, 1017, 1031 MSTPCRB............ 976, 1001, 1017, 1031 MSTPCRC............ 979, 1001, 1017, 1031 NDERH ................ 585, 1004, 1021, 1035 NDERL................. 585, 1004, 1021, 1035 NDRH................... 588, 1004, 1021, 1035 NDRL ................... 588, 1004, 1021, 1035 ODR........................ 441, 999, 1011, 1028 PC.......................................................... 32 PCR..................................................... 591 PCR (I/O port)......... 440, 999, 1011, 1028 PCR (PPG) .................... 1004, 1021, 1035 PFCR0..................... 483, 999, 1011, 1028 PFCR1..................... 484, 999, 1011, 1028 PFCR2..................... 485, 999, 1011, 1028 PFCR4..................... 487, 999, 1011, 1028 PFCR6..................... 489, 999, 1011, 1029 PFCR7..................... 490, 999, 1011, 1029 PFCR9..................... 491, 999, 1011, 1029 PFCRB .................... 493, 999, 1011, 1029 PFCRC .................... 494, 999, 1011, 1029 PMR ...................... 592, 1004, 1021, 1035 PODRH ................. 587, 1004, 1021, 1035 PODRL ................. 587, 1004, 1021, 1035 PORT .................... 438, 1003, 1020, 1034 RAMER ................ 902, 1001, 1016, 1031 RDNCR................. 142, 1001, 1016, 1031 RDR ...................... 661, 1005, 1021, 1035 REFCR.................. 163, 1001, 1016, 1031 RSR..................................................... 661 RSTCSR................ 645, 1005, 1022, 1036 RTCNT ................. 167, 1001, 1016, 1031 RTCOR ................. 167, 1001, 1016, 1031 SAR............... 400, 831, 1002, 1017, 1032 SBR....................................................... 35 SBYCR ................. 974, 1001, 1017, 1031 SCKCR ................. 959, 1001, 1017, 1031 SCMR ................... 680, 1005, 1021, 1035 SCR....................... 666, 1005, 1021, 1035 SDCR .................... 162, 1001, 1016, 1031 SEMR.................... 688, 1001, 1017, 1031 SMR ...................... 662, 1005, 1021, 1035 SRAMCR.............. 152, 1001, 1016, 1031 SSIER...................... 107, 999, 1011, 1029 SSR ....................... 671, 1005, 1021, 1035 SUBCKCR.................... 1001, 1017, 1031 SYSCR.................... 68, 1001, 1017, 1031 TCCR .................... 616, 1006, 1022, 1037 Rev.1.00 Jun. 07, 2006 Page 1099 of 1102 REJ09B0294-0100 TCNT.................................................. 534 TCNT (TMR) ........613, 1006, 1022, 1037 TCNT (TPU)..................1006, 1022, 1037 TCNT (WDT) ........643, 1005, 1022, 1036 TCNT32K................638, 998, 1010, 1027 TCORA..................613, 1005, 1022, 1036 TCORB..................614, 1005, 1022, 1036 TCR .................................................... 504 TCR (TMR) ...........614, 1005, 1022, 1036 TCR (TPU) ....................1006, 1022, 1037 TCR32K ..................638, 998, 1010, 1027 TCSR (TMR).........619, 1005, 1022, 1036 TCSR (WDT) ........643, 1005, 1022, 1036 TDR .......................662, 1005, 1021, 1035 TGR .......................534, 1006, 1023, 1037 TIER ......................528, 1006, 1022, 1037 TIOR......................510, 1006, 1022, 1037 TMDR....................509, 1006, 1022, 1037 TRG .........................768, 997, 1009, 1026 TRNTREG...............782, 997, 1009, 1026 TSR............................................. 530, 662 TSR (TPU).....................1006, 1022, 1037 TSTR .....................535, 1006, 1022, 1037 TSYR.....................536, 1006, 1022, 1037 VBR...................................................... 35 WTCRA.................137, 1000, 1016, 1031 WTCRB.................137, 1000, 1016, 1031 Repeat transfer mode ...................... 348, 415 Reset ......................................................... 80 Resolution............................................... 861 Single mode ............................................ 856 Slave receive mode ................................. 841 Slave transmit mode................................ 838 Sleep instruction exception handling ........ 88 Sleep mode...................................... 972, 981 Slot illegal instructions ............................. 89 Smart card interface ................................ 722 Software protection................................. 925 Software standby mode................... 972, 983 Space state .............................................. 698 Stack status after exception handling........ 90 Stall operations ....................................... 806 Standard serial communication interface specifications for boot mode .... 930 Start bit.................................................... 698 Status stage ............................................. 799 Stop bit.................................................... 698 Strobe assert/negate timing ..................... 184 Synchronous clearing.............................. 543 Synchronous DRAM interface................ 254 Synchronous operation............................ 543 Synchronous presetting........................... 543 System clock (I) ............................ 169, 957 T Toggle output.......................................... 540 Trace exception handling .......................... 83 Transfer information ............................... 405 Transfer information read skip function ................................................... 413 Transfer information writeback skip function ................................................... 414 Transfer modes ....................................... 347 Transmit/receive data.............................. 698 Trap instruction exception handling ......... 87 S Sample-and-hold circuit ......................... 859 Scan mode .............................................. 857 SDRAM interface ................................... 182 Serial communication interface (SCI) .... 653 Setup stage.............................................. 796 Short address mode................................. 405 Single address mode ............................... 344 Rev.1.00 Jun. 07, 2006 Page 1100 of 1102 REJ09B0294-0100 U USB function module ............................. 751 USB standard commands........................ 805 User program mode ........................ 877, 911 W Wait control ............................................ 199 Watchdog timer (WDT) .......................... 641 Watchdog timer mode............................. 646 Waveform output by compare match ...... 539 Write data buffer function....................... 309 Write data buffer function for external data bus ................................................... 309 Write data buffer function for peripheral modules.................................. 310 V Vector table address.................................. 78 Vector table address offset........................ 78 Rev.1.00 Jun. 07, 2006 Page 1101 of 1102 REJ09B0294-0100 Rev.1.00 Jun. 07, 2006 Page 1102 of 1102 REJ09B0294-0100 Renesas 32-Bit CISC Microcomputer Hardware Manual H8SX/1663 Group Publication Date: Rev.1.00, Jun. 07, 2006 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. 2006. Renesas Technology Corp., All rights reserved. Printed in Japan. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145 http://www.renesas.com Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510 Colophon 6.0 H8SX/1663 Group Hardware Manual |
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